Add VQFN-32-1EP_5x5mm_P0.5mm_EP3.15x3.15mm #619
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scripts/Packages/Package_NoLead__DFN_QFN_LGA_SON/size_definitions/qfn/vqfn.yaml
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scripts/Packages/Package_NoLead__DFN_QFN_LGA_SON/size_definitions/qfn/vqfn.yaml
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| paste_via_clearance: 0.1 | ||
| EP_paste_coverage: 0.7 | ||
| grid: [1.2, 1.2] |
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Why did you choose those values?
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Sorry I had not updated all the values in this section from VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm.
The grid values I have updated to 1.0, 1.0 to match the datasheet.
I note that paste_via_clearance and EP_paste_coverage have default values in the script, so for now I have removed them from this definition entirely. If that is not correct I would appreciate some guidance on how to select the values.
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Good choice on using defaults for the EP parameters.
I suggest to do the same with the grid.
This footprint is supposed to be build according to IPC spec (it has no Texas_ prefix). With the current values (grid, thermal_vias, EP_num_paste_pads) you are mixing both. Resulting in vias below the paste which will lead to solder loss.
Without the grid-setting, the vias are placed no-overlapping with the paste.
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Thanks for the explanation, I have removed the grid line to allow the defaults, as you say the vias now don't overlap with the paste.
I've added a screenshot of the ThermalVias variant to the top of the PR.
* More compact specification of EP_size_x * Correct thermal via grid to match datasheet * Remove paste_via_clearance and EP_paste_coverage
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Is there a corresponding PR in the footprints repo. I failed to find it. |
This is for the VQFN-32 with a nominal 3.15x3.15mm EP.
It's used in this TI part:
https://www.ti.com/lit/ds/slvs589d/slvs589d.pdf#page=33
I used VQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm as a basis, updating from the datasheet and removing commented lines. However I'm not sure if the conventions have changed since that part was defined.
Apologies if I made some incorrect assumptions (or indeed if the whole part is redundant).