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Relicensing requests for BES of partially open sourced files. #93

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OneDeuxTriSeiGo opened this issue Mar 19, 2024 · 7 comments

Open

Tracked by

Relicensing requests for BES of partially open sourced files. #93

OneDeuxTriSeiGo opened this issue Mar 19, 2024 · 7 comments

OneDeuxTriSeiGo commented Mar 19, 2024

Parent Issue: #76

The list below are files that have been released in the past by BES. These files are largely similar to those previous releases but include changes that have not been explicitly licensed publicly under an open source license.

Included are the license declared in the SDK, the license we would like the source file relicensed to, and a diff between the reconstruction and the SDK.

Unless indicated otherwise, all files below were previously made public by BES under the Apache-2.0 license.

The text was updated successfully, but these errors were encountered:

Author

OneDeuxTriSeiGo commented Mar 19, 2024

platform/hal/best2300p/hal_cmu_best2300p.c

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/hal_cmu_best2300p.c bes/platform/hal/best2300p/hal_cmu_best2300p.c
index 931c69bb481..3c5f9065ef3 100644
--- a/platform/hal/best2300p/hal_cmu_best2300p.c
+++ b/platform/hal/best2300p/hal_cmu_best2300p.c
@@ -23,6 +23,7 @@
 #include "hal_codec.h"
 #include "hal_location.h"
 #include "hal_psc.h"
+#include "hal_sleep_core_pd.h"
 #include "hal_sysfreq.h"
 #include "hal_timer.h"
 #include "hal_trace.h"
@@ -30,7 +31,13 @@
 #include "pmu.h"
 #include "system_cp.h"
 
+#ifdef USB_HIGH_SPEED
+#ifndef USB_USE_USBPLL
+#define USB_USE_USBPLL
+#endif
+#endif
 
+#define CODEC_CLK_FROM_ANA
 
 #define HAL_CMU_USB_PLL_CLOCK           (192 * 1000 * 1000)
 #define HAL_CMU_AUD_PLL_CLOCK           (CODEC_FREQ_48K_SERIES * CODEC_CMU_DIV)
@@ -38,16 +45,25 @@
 #define HAL_CMU_USB_CLOCK_60M           (60 * 1000 * 1000)
 #define HAL_CMU_USB_CLOCK_48M           (48 * 1000 * 1000)
 
-#define HAL_CMU_PWM_SLOW_CLOCK          (32 * 1000)
 #define HAL_CMU_PLL_LOCKED_TIMEOUT      US_TO_TICKS(200)
-#define HAL_CMU_26M_READY_TIMEOUT       MS_TO_TICKS(3)
+#define HAL_CMU_26M_READY_TIMEOUT       MS_TO_TICKS(4)
 #define HAL_CMU_LPU_EXTRA_TIMEOUT       MS_TO_TICKS(1)
 
+#ifdef CORE_SLEEP_POWER_DOWN
+#define TIMER1_SEL_LOC                  BOOT_TEXT_SRAM_LOC
+#else
+#define TIMER1_SEL_LOC                  BOOT_TEXT_FLASH_LOC
+#endif
 
 enum CMU_USB_CLK_SRC_T {
-    CMU_USB_CLK_SRC_PLL_48M         = 0,
-    CMU_USB_CLK_SRC_PLL_60M         = 1,
-    CMU_USB_CLK_SRC_OSC_24M_X2      = 2,
+    CMU_USB_CLK_SRC_PLL_60M         = 0,
+    CMU_USB_CLK_SRC_PLL_60M_ALT     = 1,
+    CMU_USB_CLK_SRC_PLL_48M         = 2,
+    CMU_USB_CLK_SRC_TS              = 3,
+    CMU_USB_CLK_SRC_OSC_48M         = 4,
+    CMU_USB_CLK_SRC_OSC_24M_X2      = 5,
+    CMU_USB_CLK_SRC_OSC_26M_X4      = 6,
+    CMU_USB_CLK_SRC_OSC_26M_X2      = 7,
 };
 
 enum CMU_AUD_26M_X4_USER_T {
@@ -70,6 +86,7 @@ enum CMU_DEBUG_REG_SEL_T {
 struct CP_STARTUP_CFG_T {
     __IO uint32_t stack;
     __IO uint32_t reset_hdlr;
+    __IO uint32_t entry;
 };
 
 static struct CMU_T * const cmu = (struct CMU_T *)CMU_BASE;
@@ -78,13 +95,23 @@ static struct AONCMU_T * const aoncmu = (struct AONCMU_T *)AON_CMU_BASE;
 
 static struct BTCMU_T * const POSSIBLY_UNUSED btcmu = (struct BTCMU_T *)BT_CMU_BASE;
 
-static struct WLANCMU_T * const POSSIBLY_UNUSED wlancmu = (struct WLANCMU_T *)WIFI_CMU_BASE;
+static struct CP_STARTUP_CFG_T * const cp_cfg = (struct CP_STARTUP_CFG_T *)0x200F7FE0;
 
-static uint32_t cp_entry;
-
-static uint8_t BOOT_BSS_LOC pll_user_map[HAL_CMU_PLL_QTY];
+#define HAL_CMU_PLL_USB_HS              HAL_CMU_PLL_QTY
+#ifdef USB_USE_USBPLL
+#define PLL_USER_MAP_NUM                (HAL_CMU_PLL_QTY + 1)
+#else
+#define PLL_USER_MAP_NUM                HAL_CMU_PLL_QTY
+#endif
+static uint8_t BOOT_BSS_LOC pll_user_map[PLL_USER_MAP_NUM];
 STATIC_ASSERT(HAL_CMU_PLL_USER_QTY <= sizeof(pll_user_map[0]) * 8, "Too many PLL users");
 
+#ifdef ROM_BUILD
+static enum HAL_CMU_USB_CLOCK_SEL_T usb_clk_sel;
+#endif
+
+static bool anc_enabled;
+
 #ifdef __AUDIO_RESAMPLE__
 static bool aud_resample_en = true;
 #ifdef ANA_26M_X4_ENABLE
@@ -94,7 +121,8 @@ STATIC_ASSERT(CMU_AUD_26M_X4_USER_QTY <= sizeof(aud_26m_x4_map) * 8, "Too many a
 #endif
 
 #ifdef LOW_SYS_FREQ
-static enum HAL_CMU_FREQ_T BOOT_BSS_LOC cmu_sys_freq;
+static enum HAL_CMU_LOW_SYS_FREQ_T BOOT_BSS_LOC low_sys_freq;
+static bool BOOT_BSS_LOC low_sys_freq_en;
 #endif
 
 void hal_cmu_audio_resample_enable(void)
@@ -128,7 +156,7 @@ static inline void aocmu_reg_update_wait(void)
 
 int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)
 {
-    if (id >= HAL_CMU_AON_A7) {
+    if (id >= HAL_CMU_AON_MCU) {
         return 1;
     }
 
@@ -136,10 +164,8 @@ int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)
         cmu->HCLK_ENABLE = (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         cmu->PCLK_ENABLE = (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        cmu->OCLK_ENABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        cmu->QCLK_ENABLE = (1 << (id - HAL_CMU_MOD_Q_NULL));
+        cmu->OCLK_ENABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
         aoncmu->MOD_CLK_ENABLE = (1 << (id - HAL_CMU_AON_A_CMU));
         aocmu_reg_update_wait();
@@ -150,21 +176,16 @@ int hal_cmu_clock_enable(enum HAL_CMU_MOD_ID_T id)
 
 int hal_cmu_clock_disable(enum HAL_CMU_MOD_ID_T id)
 {
-    if (id >= HAL_CMU_AON_A7) {
+    if (id >= HAL_CMU_AON_MCU) {
         return 1;
     }
 
-    if (id == HAL_CMU_MOD_P_TZC)
-        return 0;
-
     if (id < HAL_CMU_MOD_P_CMU) {
         cmu->HCLK_DISABLE = (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         cmu->PCLK_DISABLE = (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        cmu->OCLK_DISABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        cmu->QCLK_DISABLE = (1 << (id - HAL_CMU_MOD_Q_NULL));
+        cmu->OCLK_DISABLE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
         aoncmu->MOD_CLK_DISABLE = (1 << (id - HAL_CMU_AON_A_CMU));
     }
@@ -176,7 +197,7 @@ enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id)
 {
     uint32_t status;
 
-    if (id >= HAL_CMU_AON_A7) {
+    if (id >= HAL_CMU_AON_MCU) {
         return HAL_CMU_CLK_DISABLED;
     }
 
@@ -184,10 +205,8 @@ enum HAL_CMU_CLK_STATUS_T hal_cmu_clock_get_status(enum HAL_CMU_MOD_ID_T id)
         status = cmu->HCLK_ENABLE & (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         status = cmu->PCLK_ENABLE & (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        status = cmu->OCLK_ENABLE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        status = cmu->QCLK_ENABLE & (1 << (id - HAL_CMU_MOD_Q_NULL));
+        status = cmu->OCLK_ENABLE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
         status = aoncmu->MOD_CLK_ENABLE & (1 << (id - HAL_CMU_AON_A_CMU));
     }
@@ -201,7 +220,7 @@ int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mod
     uint32_t val;
     uint32_t lock;
 
-    if (id >= HAL_CMU_AON_A7) {
+    if (id >= HAL_CMU_AON_MCU) {
         return 1;
     }
 
@@ -211,12 +230,9 @@ int hal_cmu_clock_set_mode(enum HAL_CMU_MOD_ID_T id, enum HAL_CMU_CLK_MODE_T mod
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         reg = &cmu->PCLK_MODE;
         val = (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
+    } else if (id < HAL_CMU_AON_A_CMU) {
         reg = &cmu->OCLK_MODE;
         val = (1 << (id - HAL_CMU_MOD_O_SLEEP));
-    } else if (id < HAL_CMU_AON_A_CMU) {
-        reg = &cmu->QCLK_MODE;
-        val = (1 << (id - HAL_CMU_MOD_Q_NULL));
     } else {
         reg = &aoncmu->MOD_CLK_MODE;
         val = (1 << (id - HAL_CMU_AON_A_CMU));
@@ -237,7 +253,7 @@ enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id)
 {
     uint32_t mode;
 
-    if (id >= HAL_CMU_AON_A7) {
+    if (id >= HAL_CMU_AON_MCU) {
         return HAL_CMU_CLK_AUTO;
     }
 
@@ -245,10 +261,8 @@ enum HAL_CMU_CLK_MODE_T hal_cmu_clock_get_mode(enum HAL_CMU_MOD_ID_T id)
         mode = cmu->HCLK_MODE & (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         mode = cmu->PCLK_MODE & (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        mode = cmu->OCLK_MODE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        mode = cmu->QCLK_MODE & (1 << (id - HAL_CMU_MOD_Q_NULL));
+        mode = cmu->OCLK_MODE & (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
         mode = aoncmu->MOD_CLK_MODE & (1 << (id - HAL_CMU_AON_A_CMU));
     }
@@ -262,21 +276,14 @@ int hal_cmu_reset_set(enum HAL_CMU_MOD_ID_T id)
         return 1;
     }
 
-    if (id == HAL_CMU_MOD_P_TZC)
-        return 0;
-
     if (id < HAL_CMU_MOD_P_CMU) {
         cmu->HRESET_SET = (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         cmu->PRESET_SET = (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        cmu->ORESET_SET = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        cmu->QRESET_SET = (1 << (id - HAL_CMU_MOD_Q_NULL));
-    } else if (id < HAL_CMU_AON_A7) {
-        aoncmu->RESET_SET = (1 << (id - HAL_CMU_AON_A_CMU));
+        cmu->ORESET_SET = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
-        aoncmu->SOFT_RSTN_SET = (1 << (id - HAL_CMU_AON_A7));
+        aoncmu->RESET_SET = (1 << (id - HAL_CMU_AON_A_CMU));
     }
 
     return 0;
@@ -290,25 +297,14 @@ int hal_cmu_reset_clear(enum HAL_CMU_MOD_ID_T id)
 
     if (id < HAL_CMU_MOD_P_CMU) {
         cmu->HRESET_CLR = (1 << id);
-        asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
-        asm volatile("nop; nop; nop; nop;");
+        asm volatile("nop; nop;");
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         cmu->PRESET_CLR = (1 << (id - HAL_CMU_MOD_P_CMU));
-        asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
-        asm volatile("nop; nop; nop; nop;");
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        cmu->ORESET_CLR = (1 << (id - HAL_CMU_MOD_O_SLEEP));
-        asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
         asm volatile("nop; nop; nop; nop;");
     } else if (id < HAL_CMU_AON_A_CMU) {
-        cmu->QRESET_CLR = (1 << (id - HAL_CMU_MOD_Q_NULL));
-        asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;");
-        asm volatile("nop; nop; nop; nop;");
-    } else if (id < HAL_CMU_AON_A7) {
-        aoncmu->RESET_CLR = (1 << (id - HAL_CMU_AON_A_CMU));
-        aocmu_reg_update_wait();
+        cmu->ORESET_CLR = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
-        aoncmu->SOFT_RSTN_CLR = (1 << (id - HAL_CMU_AON_A7));
+        aoncmu->RESET_CLR = (1 << (id - HAL_CMU_AON_A_CMU));
         aocmu_reg_update_wait();
     }
 
@@ -327,14 +323,10 @@ enum HAL_CMU_RST_STATUS_T hal_cmu_reset_get_status(enum HAL_CMU_MOD_ID_T id)
         status = cmu->HRESET_SET & (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         status = cmu->PRESET_SET & (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        status = cmu->ORESET_SET & (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        status = cmu->QRESET_SET & (1 << (id - HAL_CMU_MOD_Q_NULL));
-    } else if (id < HAL_CMU_AON_A7) {
-        status = aoncmu->RESET_SET & (1 << (id - HAL_CMU_AON_A_CMU));
+        status = cmu->ORESET_SET & (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
-        status = aoncmu->SOFT_RSTN_SET & (1 << (id - HAL_CMU_AON_A7));
+        status = aoncmu->RESET_SET & (1 << (id - HAL_CMU_AON_A_CMU));
     }
 
     return status ? HAL_CMU_RST_CLR : HAL_CMU_RST_SET;
@@ -356,20 +348,10 @@ int hal_cmu_reset_pulse(enum HAL_CMU_MOD_ID_T id)
         cmu->HRESET_PULSE = (1 << id);
     } else if (id < HAL_CMU_MOD_O_SLEEP) {
         cmu->PRESET_PULSE = (1 << (id - HAL_CMU_MOD_P_CMU));
-    } else if (id < HAL_CMU_MOD_Q_NULL) {
-        cmu->ORESET_PULSE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else if (id < HAL_CMU_AON_A_CMU) {
-        cmu->QRESET_PULSE = (1 << (id - HAL_CMU_MOD_Q_NULL));
-    } else if (id < HAL_CMU_AON_A7) {
-        aoncmu->RESET_PULSE = (1 << (id - HAL_CMU_AON_A_CMU));
-        // Total 3 CLK-26M cycles needed
-        // AOCMU runs in 26M clock domain and its read operations consume at least 1 26M-clock cycle.
-        // (Whereas its write operations will finish at 1 HCLK cycle -- finish once in async bridge fifo)
-        aoncmu->CHIP_ID;
-        aoncmu->CHIP_ID;
-        aoncmu->CHIP_ID;
+        cmu->ORESET_PULSE = (1 << (id - HAL_CMU_MOD_O_SLEEP));
     } else {
-        aoncmu->SOFT_RSTN_PULSE = (1 << (id - HAL_CMU_AON_A7));
+        aoncmu->RESET_PULSE = (1 << (id - HAL_CMU_AON_A_CMU));
         // Total 3 CLK-26M cycles needed
         // AOCMU runs in 26M clock domain and its read operations consume at least 1 26M-clock cycle.
         // (Whereas its write operations will finish at 1 HCLK cycle -- finish once in async bridge fifo)
@@ -415,7 +397,7 @@ int hal_cmu_timer_set_div(enum HAL_CMU_TIMER_ID_T id, uint32_t div)
     return 0;
 }
 
-void hal_cmu_timer0_select_fast(void)
+void BOOT_TEXT_FLASH_LOC hal_cmu_timer0_select_fast(void)
 {
     uint32_t lock;
 
@@ -423,7 +405,7 @@ void hal_cmu_timer0_select_fast(void)
     // 6.5M
     cmu->PERIPH_CLK |= (1 << CMU_SEL_TIMER_FAST_SHIFT);
     // AON Timer
-    aoncmu->TIMER_CLK |= AON_CMU_SEL_TIMER_FAST;
+    aoncmu->CLK_SELECT |= AON_CMU_SEL_TIMER_FAST;
     int_unlock(lock);
 }
 
@@ -435,11 +417,11 @@ void BOOT_TEXT_FLASH_LOC hal_cmu_timer0_select_slow(void)
     // 16K
     cmu->PERIPH_CLK &= ~(1 << CMU_SEL_TIMER_FAST_SHIFT);
     // AON Timer
-    aoncmu->TIMER_CLK &= ~AON_CMU_SEL_TIMER_FAST;
+    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_TIMER_FAST;
     int_unlock(lock);
 }
 
-void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_fast(void)
+void TIMER1_SEL_LOC hal_cmu_timer1_select_fast(void)
 {
     uint32_t lock;
 
@@ -449,7 +431,7 @@ void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_fast(void)
     int_unlock(lock);
 }
 
-void BOOT_TEXT_FLASH_LOC hal_cmu_timer1_select_slow(void)
+void TIMER1_SEL_LOC hal_cmu_timer1_select_slow(void)
 {
     uint32_t lock;
 
@@ -479,46 +461,6 @@ void hal_cmu_timer2_select_slow(void)
     int_unlock(lock);
 }
 
-void hal_cmu_dsp_timer0_select_fast(void)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    // 6.5M
-    cmu->DSP_DIV |= (1 << CMU_SEL_TIMER_FAST_AP_SHIFT);
-    int_unlock(lock);
-}
-
-void hal_cmu_dsp_timer0_select_slow(void)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    // 16K
-    cmu->DSP_DIV &= ~(1 << CMU_SEL_TIMER_FAST_AP_SHIFT);
-    int_unlock(lock);
-}
-
-void hal_cmu_dsp_timer1_select_fast(void)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    // 6.5M
-    cmu->DSP_DIV |= (1 << (CMU_SEL_TIMER_FAST_AP_SHIFT + 1));
-    int_unlock(lock);
-}
-
-void hal_cmu_dsp_timer1_select_slow(void)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    // 16K
-    cmu->DSP_DIV &= ~(1 << (CMU_SEL_TIMER_FAST_AP_SHIFT + 1));
-    int_unlock(lock);
-}
-
 int hal_cmu_sdmmc_set_pll_div(uint32_t div)
 {
     uint32_t lock;
@@ -536,709 +478,317 @@ int hal_cmu_sdmmc_set_pll_div(uint32_t div)
     return 0;
 }
 
-int BOOT_TEXT_SRAM_LOC hal_cmu_flash_set_freq(enum HAL_CMU_FREQ_T freq)
-{
-    uint32_t set;
-    uint32_t clr;
-    uint32_t lock;
-    bool clk_en;
-
-    if (freq >= HAL_CMU_FREQ_QTY) {
-        return 1;
-    }
-    if (freq == HAL_CMU_FREQ_32K) {
-        return 2;
-    }
-
-    switch (freq) {
-    case HAL_CMU_FREQ_26M:
-        set = 0;
-        clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4 | AON_CMU_SEL_FLS_PLL;
-        break;
-    case HAL_CMU_FREQ_52M:
-        set = AON_CMU_SEL_FLS_OSCX2;
-        clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX4 | AON_CMU_SEL_FLS_PLL;
-        break;
-    case HAL_CMU_FREQ_78M:
-    case HAL_CMU_FREQ_104M:
 #ifdef OSC_26M_X4_AUD2BB
-        set = AON_CMU_SEL_FLS_OSCX4;
-        clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_PLL;
-        break;
-#endif
-    case HAL_CMU_FREQ_156M:
-    case HAL_CMU_FREQ_208M:
-    case HAL_CMU_FREQ_260M:
-        set = AON_CMU_RSTN_DIV_FLS | AON_CMU_SEL_FLS_PLL;
-        clr = AON_CMU_CFG_DIV_FLS_MASK | AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4;
-        if (0) {
-#ifndef OSC_26M_X4_AUD2BB
-        } else if (freq <= HAL_CMU_FREQ_78M) {
-            set |= AON_CMU_CFG_DIV_FLS(3);
-        } else if (freq <= HAL_CMU_FREQ_104M) {
-            set |= AON_CMU_CFG_DIV_FLS(2);
-#endif
-        } else if (freq <= HAL_CMU_FREQ_156M) {
-            set |= AON_CMU_CFG_DIV_FLS(1);
-        } else { // 208M or 260M
-            set |= AON_CMU_CFG_DIV_FLS(0);
-        }
-        break;
-    case HAL_CMU_FREQ_390M:
-    case HAL_CMU_FREQ_780M:
-    default:
-        set = AON_CMU_BYPASS_DIV_FLS | AON_CMU_SEL_FLS_PLL;
-        clr = AON_CMU_RSTN_DIV_FLS | AON_CMU_SEL_FLS_OSCX2 | AON_CMU_SEL_FLS_OSCX4;
-        break;
-    };
 
-    lock = int_lock();
-    clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_FLASH);
-    if (clk_en) {
-        cmu->OCLK_DISABLE = SYS_OCLK_FLASH;
-        cmu->HCLK_DISABLE = SYS_HCLK_FLASH;
-        // Wait at least 2 cycles of flash controller. The min freq is 26M, the same as AON.
-        aocmu_reg_update_wait();
-        aocmu_reg_update_wait();
-    }
-    aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
-    if (clk_en) {
-        cmu->HCLK_ENABLE = SYS_HCLK_FLASH;
-        cmu->OCLK_ENABLE = SYS_OCLK_FLASH;
-    }
-    int_unlock(lock);
+// Any of 78M/104M/208M is changed to 26M x4 (104M)
 
-    return 0;
+#define SYS_SET_FREQ_FUNC(f, F, CLK_OV) \
+int hal_cmu_ ##f## _set_freq(enum HAL_CMU_FREQ_T freq) \
+{ \
+    uint32_t enable; \
+    uint32_t disable; \
+    if (freq >= HAL_CMU_FREQ_QTY) { \
+        return 1; \
+    } \
+    if (freq == HAL_CMU_FREQ_32K) { \
+        enable = 0; \
+        disable = CMU_SEL_OSC_ ##F## _DISABLE | CMU_SEL_OSCX2_ ##F## _DISABLE | \
+            CMU_SEL_PLL_ ##F## _DISABLE | CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE; \
+    } else if (freq == HAL_CMU_FREQ_26M) { \
+        enable = CMU_SEL_OSC_ ##F## _ENABLE; \
+        disable = CMU_SEL_OSCX2_ ##F## _DISABLE | \
+            CMU_SEL_PLL_ ##F## _DISABLE | CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE; \
+    } else if (freq == HAL_CMU_FREQ_52M) { \
+        enable = CMU_SEL_OSCX2_ ##F## _ENABLE; \
+        disable = CMU_SEL_PLL_ ##F## _DISABLE | CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE; \
+    } else { \
+        enable = CMU_SEL_PLL_ ##F## _ENABLE | CMU_BYPASS_DIV_ ##F## _ENABLE; \
+        disable = CMU_RSTN_DIV_ ##F## _DISABLE; \
+    } \
+    if (enable & CMU_SEL_PLL_ ##F## _ENABLE) { \
+        CLK_OV; \
+        cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_ ##F## _ENABLE; \
+        if (enable & CMU_BYPASS_DIV_ ##F## _ENABLE) { \
+            cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_ ##F## _ENABLE; \
+        } else { \
+            cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_ ##F## _DISABLE; \
+        } \
+    } \
+    cmu->SYS_CLK_ENABLE = enable; \
+    if (enable & CMU_SEL_PLL_ ##F## _ENABLE) { \
+        cmu->SYS_CLK_DISABLE = disable; \
+    } else { \
+        cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE); \
+        cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_ ##F## _DISABLE; \
+        cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_ ##F## _DISABLE; \
+    } \
+    return 0; \
 }
 
-int BOOT_TEXT_SRAM_LOC hal_cmu_flash1_set_freq(enum HAL_CMU_FREQ_T freq)
-{
-    aoncmu->FLASH_IOCFG |= AON_CMU_PU_FLASH1_IO;
-    //TODO: 2003 flash0 and flash1 use same clock source, so don't change clk freq in case of flash0 error
-#ifdef ROM_BUILD //2003 rom only use one flash
-    return hal_cmu_flash_set_freq(freq);
-#else
-    return 0;
-#endif
+#else // !OSC_26M_X4_AUD2BB
+
+#define SYS_SET_FREQ_FUNC(f, F, CLK_OV) \
+int hal_cmu_ ##f## _set_freq(enum HAL_CMU_FREQ_T freq) \
+{ \
+    uint32_t lock; \
+    uint32_t enable; \
+    uint32_t disable; \
+    int div = -1; \
+    if (freq >= HAL_CMU_FREQ_QTY) { \
+        return 1; \
+    } \
+    if (freq == HAL_CMU_FREQ_32K) { \
+        enable = 0; \
+        disable = CMU_SEL_OSC_ ##F## _DISABLE | CMU_SEL_OSCX2_ ##F## _DISABLE | \
+            CMU_SEL_PLL_ ##F## _DISABLE | CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE; \
+    } else if (freq == HAL_CMU_FREQ_26M) { \
+        enable = CMU_SEL_OSC_ ##F## _ENABLE; \
+        disable = CMU_SEL_OSCX2_ ##F## _DISABLE | \
+            CMU_SEL_PLL_ ##F## _DISABLE | CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE; \
+    } else if (freq == HAL_CMU_FREQ_52M) { \
+        enable = CMU_SEL_OSCX2_ ##F## _ENABLE; \
+        disable = CMU_SEL_PLL_ ##F## _DISABLE | CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE; \
+    } else if (freq == HAL_CMU_FREQ_78M) { \
+        enable = CMU_SEL_PLL_ ##F## _ENABLE | CMU_RSTN_DIV_ ##F## _ENABLE; \
+        disable = CMU_BYPASS_DIV_ ##F## _DISABLE; \
+        div = 1; \
+    } else if (freq == HAL_CMU_FREQ_104M) { \
+        enable = CMU_SEL_PLL_ ##F## _ENABLE | CMU_RSTN_DIV_ ##F## _ENABLE; \
+        disable = CMU_BYPASS_DIV_ ##F## _DISABLE; \
+        div = 0; \
+    } else { \
+        enable = CMU_SEL_PLL_ ##F## _ENABLE | CMU_BYPASS_DIV_ ##F## _ENABLE; \
+        disable = CMU_RSTN_DIV_ ##F## _DISABLE; \
+    } \
+    if (div >= 0) { \
+        CLK_OV; \
+        lock = int_lock(); \
+        cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_ ##F, div); \
+        int_unlock(lock); \
+    } \
+    if (enable & CMU_SEL_PLL_ ##F## _ENABLE) { \
+        cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_ ##F## _ENABLE; \
+        if (enable & CMU_BYPASS_DIV_ ##F## _ENABLE) { \
+            cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_ ##F## _ENABLE; \
+        } else { \
+            cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_ ##F## _DISABLE; \
+        } \
+    } \
+    cmu->SYS_CLK_ENABLE = enable; \
+    if (enable & CMU_SEL_PLL_ ##F## _ENABLE) { \
+        cmu->SYS_CLK_DISABLE = disable; \
+    } else { \
+        cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_ ##F## _DISABLE | CMU_BYPASS_DIV_ ##F## _DISABLE); \
+        cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_ ##F## _DISABLE; \
+        cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_ ##F## _DISABLE; \
+    } \
+    return 0; \
 }
 
-int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq)
-{
-    uint32_t set;
-    uint32_t clr;
-    uint32_t lock;
-    bool clk_en;
+#endif // !OSC_26M_X4_AUD2BB
 
-    if (freq >= HAL_CMU_FREQ_QTY) {
-        return 1;
-    }
-    if (freq == HAL_CMU_FREQ_32K) {
-        return 2;
-    }
+#ifdef MCU_SYS_CLOCK_400M
+#define FLASH_DIV_OFFSET                2
+#elif defined(MCU_SYS_CLOCK_300M)
+#define FLASH_DIV_OFFSET                1
+#else
+#define FLASH_DIV_OFFSET                0
+#endif
 
-    // 2003 psram ctrl use 400M clk from bbpsram
-    switch (freq) {
-    case HAL_CMU_FREQ_26M:
-        set = 0;
-        clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4 | AON_CMU_SEL_PSR_PLL;
-        break;
-    case HAL_CMU_FREQ_52M:
-        set = AON_CMU_SEL_PSR_OSCX2;
-        clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX4 | AON_CMU_SEL_PSR_PLL;
-        break;
-    case HAL_CMU_FREQ_78M:
-    case HAL_CMU_FREQ_104M:
 #ifdef OSC_26M_X4_AUD2BB
-        set = AON_CMU_SEL_PSR_OSCX4;
-        clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_PLL;
-        break;
-#endif
-    case HAL_CMU_FREQ_156M:
-    case HAL_CMU_FREQ_208M:
-    case HAL_CMU_FREQ_260M:
-        set = AON_CMU_RSTN_DIV_PSR | AON_CMU_SEL_PSR_PLL | AON_CMU_SEL_PSR_INT;
-        clr = AON_CMU_CFG_DIV_PSR_MASK | AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4;
-        if (0) {
-#ifndef OSC_26M_X4_AUD2BB
-        } else if (freq <= HAL_CMU_FREQ_78M) {
-            set |= AON_CMU_CFG_DIV_PSR(3);
-        } else if (freq <= HAL_CMU_FREQ_104M) {
-            set |= AON_CMU_CFG_DIV_PSR(2);
-#endif
-        } else if (freq <= HAL_CMU_FREQ_156M) {
-            set |= AON_CMU_CFG_DIV_PSR(1);
-        } else { // 208M or 260M
-            set |= AON_CMU_CFG_DIV_PSR(0);
-        }
-        break;
-    case HAL_CMU_FREQ_390M:
-    case HAL_CMU_FREQ_780M:
-    default:
-        set = AON_CMU_BYPASS_DIV_PSR | AON_CMU_SEL_PSR_PLL | AON_CMU_SEL_PSR_INT;
-        clr = AON_CMU_RSTN_DIV_PSR | AON_CMU_SEL_PSR_OSCX2 | AON_CMU_SEL_PSR_OSCX4;
-        break;
-    };
-
-    lock = int_lock();
-    clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_PSRAM200);
-    if (clk_en) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PHY_PS_DISABLE;
-        cmu->OCLK_DISABLE = SYS_OCLK_PSRAM200;
-        cmu->HCLK_DISABLE = SYS_HCLK_PSRAM200;
-        // Wait at least 2 cycles of psram controller. The min freq is 26M, the same as AON.
-        aocmu_reg_update_wait();
-        aocmu_reg_update_wait();
-    }
-    aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PHY_PS_ENABLE;
-    if (clk_en) {
-        cmu->HCLK_ENABLE = SYS_HCLK_PSRAM200;
-        cmu->OCLK_ENABLE = SYS_OCLK_PSRAM200;
-    }
-    int_unlock(lock);
+#define FLASH_FREQ_OV                   { aoncmu->CLK_OUT |= AON_CMU_SEL_X4_FLS; }
+#else
+#define FLASH_FREQ_OV                   { div += FLASH_DIV_OFFSET; }
+#endif
 
-    return 0;
-}
+BOOT_TEXT_SRAM_LOC SYS_SET_FREQ_FUNC(flash, FLS, FLASH_FREQ_OV);
 
-int hal_cmu_ddr_clock_enable()
+#ifdef LOW_SYS_FREQ
+void hal_cmu_low_sys_clock_set(enum HAL_CMU_LOW_SYS_FREQ_T freq)
 {
-    uint32_t set;
-    uint32_t clr;
     uint32_t lock;
-    bool clk_en;
-
-    hal_cmu_pll_enable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_PSRAM);
-#if 1
-    //pxclk use xclk, works in synchronous mode
-    //a7 can change sys freq in this mode
-    cmu->PERIPH_CLK &= ~CMU_SEL_PSRAMX2;
-    *(volatile uint32_t *)(GPV_PSRAM1G_BASE+0x42020) = 0;
-#else
-    //pxclk use psram2, works in asynchronous mode
-    *(volatile uint32_t *)(GPV_PSRAM1G_BASE+0x42020) = 4;
-    cmu->PERIPH_CLK |= CMU_SEL_PSRAMX2;
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_PSRAMX2_ENABLE;
-#endif
-
-    // PSRAMUHS can't use ddr pll divider
-    set = AON_CMU_BYPASS_DIV_DDR | AON_CMU_SEL_DDR_PLL | AON_CMU_CFG_DIV_PSRAMX2(2);
-    clr = AON_CMU_RSTN_DIV_DDR | AON_CMU_SEL_DDR_OSCX2 | AON_CMU_SEL_DDR_OSCX4 | AON_CMU_CFG_DIV_PSRAMX2_MASK;
 
-    lock = int_lock();
-    clk_en = !!(cmu->OCLK_DISABLE & SYS_OCLK_PSRAM1G);
-    if (clk_en) {
-        cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G;
-        cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G;
-        // Wait at least 2 cycles of psram controller. The min freq is 26M, the same as AON.
-        aocmu_reg_update_wait();
-        aocmu_reg_update_wait();
+    if (hal_get_chip_metal_id() == HAL_CHIP_METAL_ID_0) {
+        return;
     }
-    aoncmu->DDR_CLK = (aoncmu->DDR_CLK & ~clr) | set;
-
-    cmu->XCLK_ENABLE = SYS_XCLK_PSRAM1G | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_PSRAM1G;
-    cmu->HCLK_ENABLE = SYS_HCLK_PSRAM1G;
-    cmu->OCLK_ENABLE = SYS_OCLK_PSRAM1G;
 
+    lock = int_lock();
+    low_sys_freq = freq;
+    hal_cmu_sys_set_freq(hal_sysfreq_get_hw_freq());
     int_unlock(lock);
-
-    return 0;
-}
-
-void hal_cmu_ddr_clock_disable()
-{
-    cmu->XCLK_DISABLE = SYS_XCLK_PSRAM1G | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_PSRAM1G;
-    cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G;
-    cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G;
-    hal_cmu_pll_disable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_PSRAM);
-}
-
-void hal_cmu_ddr_reset_set()
-{
-    cmu->XRESET_SET = SYS_XRST_PSRAM1G | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_PSRAM1G;
-    cmu->ORESET_SET = SYS_ORST_PSRAM1G;
-    cmu->HRESET_SET = SYS_HRST_PSRAM1G;
-}
-
-void hal_cmu_ddr_reset_clear()
-{
-    cmu->XRESET_CLR = SYS_XRST_PSRAM1G | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_PSRAM1G;
-    cmu->ORESET_CLR = SYS_ORST_PSRAM1G;
-    cmu->HRESET_CLR = SYS_HRST_PSRAM1G;
-}
-
-int hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq);
-
-void hal_cmu_dsi_phy_reset_set(void)
-{
-    hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_32K);
-    hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_PN);
-    hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_TV);
-    hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_PIX);
-    hal_cmu_reset_set(HAL_CMU_MOD_Q_DSI_DSI);
 }
 
-void hal_cmu_dsi_phy_reset_clear(void)
-{
-    // TODO: Move clock enable APIs out
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_32K);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PN);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_TV);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PIX);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_DSI);
-
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_32K);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PN);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_TV);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PIX);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_DSI);
-}
-
-void hal_cmu_dsi_clock_enable(void)
-{
-#if !defined(DSP_ENABLE) && !defined(CHIP_BEST2003_DSP)
-    hal_cmu_dsp_clock_enable();
-    hal_cmu_dsp_reset_clear();
-    hal_sys_timer_delay(US_TO_TICKS(10));
-#endif
-    hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
-    cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
-    hal_cmu_pll_enable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
-    cmu->APCLK_ENABLE = SYS_APCLK_DISPLAY;
-    aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN |
-        SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, 0x4);
-    cmu->QCLK_ENABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
-    hal_sys_timer_delay_us(10);
-    hal_cmu_dsi_reset_set();//QR DSI/PIX CLK bit 4/5; APR APB CLK bit 8
-    hal_sys_timer_delay(US_TO_TICKS(10));
-    hal_cmu_dsi_reset_clear();
-}
-
-void hal_cmu_dsi_clock_enable_v2(uint8_t pixel_div)
-{
-    hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
-    cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
-    hal_cmu_pll_enable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
-    cmu->APCLK_ENABLE = SYS_APCLK_DISPLAY;
-    aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN |
-        SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_DSI, pixel_div);
-    cmu->QCLK_ENABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
-    hal_sys_timer_delay_us(10);
-}
-
-void hal_cmu_dsi_clock_disable(void)
-{
-    aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_DSI | AON_CMU_POL_CLK_DSI_IN);
-    cmu->QCLK_DISABLE = SYS_QCLK_DSI_DSI | SYS_QCLK_DSI_PIX;
-    cmu->APCLK_DISABLE = SYS_APCLK_DISPLAY;
-    hal_cmu_pll_disable(HAL_CMU_PLL_DSI, HAL_CMU_PLL_USER_DSI);
-}
-
-void hal_cmu_dsi_reset_set(void)
-{
-    cmu->QRESET_SET = SYS_QRST_DSI_DSI | SYS_QRST_DSI_PIX;
-    cmu->APRESET_SET = SYS_APRST_DISPLAY;
-}
-
-void hal_cmu_dsi_reset_clear(void)
-{
-    cmu->APRESET_CLR = SYS_APRST_DISPLAY;
-    cmu->QRESET_CLR = SYS_QRST_DSI_DSI | SYS_QRST_DSI_PIX;
-    hal_sys_timer_delay_us(10);
-}
-
-void hal_cmu_dsi_sleep(void)
-{
-    hal_cmu_dsi_clock_disable();
-}
-
-void hal_cmu_dsi_wakeup(void)
-{
-    hal_cmu_dsi_clock_enable();
-}
-
-void hal_cmu_lcdc_clock_enable(void)
-{
-    hal_cmu_lcdc_reset_clear();
-    cmu->XCLK_ENABLE = SYS_XCLK_DSI | SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH;
-    cmu->QCLK_ENABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV;
-
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_32K);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PN);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_TV);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_PIX);
-    hal_cmu_clock_enable(HAL_CMU_MOD_Q_DSI_DSI);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_32K);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PN);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_TV);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_PIX);
-    hal_cmu_reset_clear(HAL_CMU_MOD_Q_DSI_DSI);
-}
-
-void hal_cmu_lcdc_clock_disable(void)
-{
-    cmu->QCLK_DISABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV;
-    cmu->XCLK_DISABLE = SYS_XCLK_DSI | SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH;
-}
-
-void hal_cmu_lcdc_reset_set(void)
-{
-    cmu->QRESET_SET = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV;
-    cmu->XRESET_SET = SYS_XRST_DSI | SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH;
-}
-
-void hal_cmu_lcdc_reset_clear(void)
-{
-    cmu->XRESET_CLR = SYS_XRST_DSI | SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH;
-    cmu->QRESET_CLR = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV;
-    hal_sys_timer_delay_us(10);
-}
-
-void hal_cmu_lcdc_sleep(void)
-{
-    hal_cmu_lcdc_clock_disable();
-}
-
-void hal_cmu_lcdc_wakeup(void)
-{
-    hal_cmu_lcdc_clock_enable();
-}
-void hal_cmu_csi_clock_enable(void)
-{
-    cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_APCLK, 0x0);
-    aoncmu->MIPI_CLK = AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_CSI_IN |
-        SET_BITFIELD(aoncmu->MIPI_CLK, AON_CMU_CFG_DIV_PIX_CSI, 0x7); //0xa:240M 1lane
-    cmu->APCLK_ENABLE = SYS_APCLK_CSI;
-    cmu->XCLK_ENABLE = SYS_XCLK_CSI;
-    cmu->QCLK_ENABLE = SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG;
-
-    hal_cmu_clock_set_mode(HAL_CMU_MOD_Q_CSI_LANE, HAL_CMU_CLK_AUTO);
-    hal_cmu_clock_set_mode(HAL_CMU_MOD_Q_CSI_PIX, HAL_CMU_CLK_AUTO);
-    hal_cmu_clock_set_mode(HAL_CMU_MOD_Q_CSI_LANG, HAL_CMU_CLK_AUTO);
-}
-
-void hal_cmu_csi_clock_disable(void)
-{
-    cmu->XCLK_DISABLE = SYS_XCLK_CSI;
-    cmu->QCLK_ENABLE = SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG;
-    cmu->APCLK_DISABLE = SYS_APCLK_CSI;
-    aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_CSI_IN);
-}
-
-void hal_cmu_csi_reset_set(void)
+int hal_cmu_fast_timer_offline(void)
 {
-    cmu->XRESET_SET = SYS_XRST_CSI;
-    cmu->QRESET_SET = SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG;
-    cmu->APRESET_SET = SYS_APRST_CSI;
+    return low_sys_freq_en && low_sys_freq != HAL_CMU_LOW_SYS_FREQ_13M;
 }
 
-void hal_cmu_csi_reset_clear(void)
+static void hal_cmu_osc_to_dig_x4_enable(void)
 {
-    cmu->APRESET_CLR = SYS_APRST_CSI;
-    cmu->XRESET_CLR = SYS_XRST_CSI;
-    cmu->QRESET_CLR = SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG;
-    hal_sys_timer_delay_us(10);
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_X4_ANA_ENABLE;
+    aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_SYS;
+    aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_DIG;
+    aoncmu->RESERVED_03C |= AON_CMU_OSC_TO_DIG_X4;
 }
 
-#ifdef LOW_SYS_FREQ
-#ifdef LOW_SYS_FREQ_6P5M
-int hal_cmu_fast_timer_offline(void)
+static void hal_cmu_osc_to_dig_x4_disable(void)
 {
-    return (cmu_sys_freq == HAL_CMU_FREQ_6P5M);
-}
+    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_DIG;
+    aoncmu->RESERVED_03C &= ~AON_CMU_OSC_TO_DIG_X4;
+#ifndef OSC_26M_X4_AUD2BB
+    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_SYS;
 #endif
+#ifndef ANA_26M_X4_ENABLE
+    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_X4_ANA_DISABLE;
 #endif
-
-#ifdef CHIP_BEST2003_DSP
-
-int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq) __attribute__((alias("hal_cmu_dsp_set_freq")));
-
-enum HAL_CMU_FREQ_T hal_cmu_sys_get_freq(void) __attribute__((alias("hal_cmu_dsp_get_freq")));
-
-#else // !CHIP_BEST2003_DSP
+}
 
 int hal_cmu_sys_set_freq(enum HAL_CMU_FREQ_T freq)
 {
+    uint32_t lock;
     uint32_t enable;
     uint32_t disable;
-    int div;
-    uint32_t lock;
+    int div = -1;
+    bool low_sys_set, low_sys_clr;
 
     if (freq >= HAL_CMU_FREQ_QTY) {
         return 1;
     }
 
-#ifdef LOW_SYS_FREQ
-    cmu_sys_freq = freq;
-#endif
-
-    div = -1;
-
-    switch (freq) {
-    case HAL_CMU_FREQ_32K:
-        enable = 0;
-        disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_OSC_4_DISABLE | CMU_SEL_MCU_OSC_2_DISABLE |
-            CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_SLOW_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-        break;
-    case HAL_CMU_FREQ_6P5M:
-#if defined(LOW_SYS_FREQ) && defined(LOW_SYS_FREQ_6P5M)
-        enable = CMU_SEL_MCU_OSC_4_ENABLE;
-        disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
-            CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_SLOW_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-        break;
-#endif
-    case HAL_CMU_FREQ_13M:
-#ifdef LOW_SYS_FREQ
-        enable = CMU_SEL_MCU_OSC_2_ENABLE | CMU_SEL_MCU_SLOW_ENABLE;
-        disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
-            CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-        break;
-#endif
-    case HAL_CMU_FREQ_26M:
-        enable = CMU_SEL_MCU_SLOW_ENABLE;
-        disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_OSC_2_ENABLE |
-            CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-        break;
-    case HAL_CMU_FREQ_52M:
-        enable = CMU_SEL_MCU_FAST_ENABLE;
-        disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE |
-            CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-        break;
-    case HAL_CMU_FREQ_78M:
-    case HAL_CMU_FREQ_104M:
-#ifdef OSC_26M_X4_AUD2BB
-        enable = CMU_SEL_MCU_OSCX4_ENABLE | CMU_SEL_MCU_FAST_ENABLE;
-        disable = CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-        break;
-#endif
-    case HAL_CMU_FREQ_156M:
-    case HAL_CMU_FREQ_208M:
-    case HAL_CMU_FREQ_260M:
-        enable = CMU_RSTN_DIV_MCU_ENABLE | CMU_SEL_MCU_PLL_ENABLE;
-        disable = CMU_BYPASS_DIV_MCU_DISABLE;
-        if (0) {
-#ifndef OSC_26M_X4_AUD2BB
-        } else if (freq <= HAL_CMU_FREQ_78M) {
-            div = 3;
-        } else if (freq <= HAL_CMU_FREQ_104M) {
-            div = 2;
-#endif
-        } else if (freq <= HAL_CMU_FREQ_156M) {
-            div = 1;
-        } else { // 208M or 260M
-            div = 0;
-        }
-        break;
-    case HAL_CMU_FREQ_390M:
-    case HAL_CMU_FREQ_780M:
-    default:
-        enable = CMU_BYPASS_DIV_MCU_ENABLE | CMU_SEL_MCU_PLL_ENABLE;
-        disable = CMU_RSTN_DIV_MCU_DISABLE;
-        break;
-    };
+    low_sys_set = false;
+    low_sys_clr = false;
 
-    if (div >= 0) {
-        lock = int_lock();
-        cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_MCU, div);
-        int_unlock(lock);
-    }
+    lock = int_lock();
 
-    if (enable & CMU_SEL_MCU_PLL_ENABLE) {
-        cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_MCU_ENABLE;
-        if (enable & CMU_BYPASS_DIV_MCU_ENABLE) {
-            cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_MCU_ENABLE;
-        } else {
-            cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_MCU_DISABLE;
+    if (low_sys_freq == HAL_CMU_LOW_SYS_FREQ_NONE) {
+        if (aoncmu->RESERVED_03C & AON_CMU_OSC_TO_DIG_X4) {
+            low_sys_clr = true;
         }
-    }
-    cmu->SYS_CLK_ENABLE = enable;
-    if (enable & CMU_SEL_MCU_PLL_ENABLE) {
-        cmu->SYS_CLK_DISABLE = disable;
     } else {
-        cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_MCU_DISABLE | CMU_BYPASS_DIV_MCU_DISABLE);
-        cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_MCU_DISABLE;
-        cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_MCU_DISABLE;
-    }
-
-    return 0;
-}
-
-enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_sys_get_freq(void)
-{
-    uint32_t sys_clk;
-    uint32_t div;
-
-    sys_clk = cmu->SYS_CLK_ENABLE;
-
-    if (sys_clk & CMU_SEL_MCU_PLL_ENABLE) {
-        if (sys_clk & CMU_BYPASS_DIV_MCU_ENABLE) {
-            // 384M
-            return HAL_CMU_FREQ_390M;
-        } else {
-            div = GET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_MCU);
-            if (div == 0) {
-                // 192M
-                return HAL_CMU_FREQ_208M;
-            } else if (div == 1) {
-                // 128M
-                return HAL_CMU_FREQ_156M;
-            } else if (div == 2) {
-                // 96M
-                return HAL_CMU_FREQ_104M;
-            } else { // div == 3
-                // 76.8M
-                return HAL_CMU_FREQ_78M;
+        if (freq == HAL_CMU_FREQ_26M) {
+            low_sys_set = true;
+        } else if (freq > HAL_CMU_FREQ_26M) {
+            if (aoncmu->RESERVED_03C & AON_CMU_OSC_TO_DIG_X4) {
+                low_sys_clr = true;
             }
         }
-    } else if (sys_clk & CMU_SEL_MCU_FAST_ENABLE) {
-        if (sys_clk & CMU_SEL_MCU_OSCX4_ENABLE) {
-            return HAL_CMU_FREQ_104M;
-        } else {
-            return HAL_CMU_FREQ_52M;
-        }
-    } else if (sys_clk & CMU_SEL_MCU_SLOW_ENABLE) {
-        return HAL_CMU_FREQ_26M;
-    } else {
-        return HAL_CMU_FREQ_32K;
     }
-}
-
-#endif // !CHIP_BEST2003_DSP
-
-int hal_cmu_dsp_set_freq(enum HAL_CMU_FREQ_T freq)
-{
-    uint32_t enable;
-    uint32_t disable;
-    int div;
-    uint32_t lock;
 
-    if (freq >= HAL_CMU_FREQ_QTY) {
-        return 1;
+    if (low_sys_clr) {
+        low_sys_freq_en = false;
+        cmu->SYS_CLK_ENABLE = CMU_SEL_OSC_SYS_ENABLE;
+        cmu->SYS_CLK_DISABLE = CMU_SEL_OSCX2_SYS_DISABLE | CMU_SEL_PLL_SYS_DISABLE;
+        hal_cmu_osc_to_dig_x4_disable();
+    }
+    if (low_sys_set) {
+        low_sys_freq_en = true;
+        cmu->SYS_CLK_ENABLE = CMU_SEL_OSC_SYS_ENABLE;
+        cmu->SYS_CLK_DISABLE = CMU_SEL_OSCX2_SYS_DISABLE | CMU_SEL_PLL_SYS_DISABLE;
+        hal_cmu_osc_to_dig_x4_enable();
+        freq = HAL_CMU_FREQ_208M;
     }
 
-#ifdef CHIP_BEST2003_DSP
-#ifdef LOW_SYS_FREQ
-    cmu_sys_freq = freq;
-#endif
-#endif
-
-    div = -1;
-
-    switch (freq) {
-    case HAL_CMU_FREQ_32K:
+    if (freq == HAL_CMU_FREQ_32K) {
         enable = 0;
-        disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_OSC_4_DISABLE | CMU_SEL_A7_OSC_2_DISABLE |
-            CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_SLOW_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
-        break;
-    case HAL_CMU_FREQ_6P5M:
-#if defined(LOW_SYS_FREQ) && defined(LOW_SYS_FREQ_6P5M)
-        enable = CMU_SEL_A7_OSC_4_ENABLE;
-        disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
-            CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_SLOW_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
-        break;
-#endif
-    case HAL_CMU_FREQ_13M:
-#ifdef LOW_SYS_FREQ
-        enable = CMU_SEL_A7_OSC_2_ENABLE | CMU_SEL_A7_SLOW_ENABLE;
-        disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
-            CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
-        break;
-#endif
-    case HAL_CMU_FREQ_26M:
-        enable = CMU_SEL_A7_SLOW_ENABLE;
-        disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_OSC_2_DISABLE |
-            CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_FAST_DISABLE | CMU_SEL_A7_PLL_DISABLE;
-        break;
-    case HAL_CMU_FREQ_52M:
-        enable = CMU_SEL_A7_FAST_ENABLE;
-        disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE |
-            CMU_SEL_A7_OSCX4_DISABLE | CMU_SEL_A7_PLL_DISABLE;
-        break;
-    case HAL_CMU_FREQ_78M:
-    case HAL_CMU_FREQ_104M:
-#ifdef OSC_26M_X4_AUD2BB
-        enable = CMU_SEL_A7_OSCX4_ENABLE | CMU_SEL_A7_FAST_ENABLE;
-        disable = CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE | CMU_SEL_A7_PLL_DISABLE;
-        break;
-#endif
-    case HAL_CMU_FREQ_156M:
-    case HAL_CMU_FREQ_208M:
-    case HAL_CMU_FREQ_260M:
-    case HAL_CMU_FREQ_390M:
-        enable = CMU_RSTN_DIV_A7_ENABLE | CMU_SEL_A7_PLL_ENABLE;
-        disable = CMU_BYPASS_DIV_A7_DISABLE;
-        if (0) {
-        } else if (freq <= HAL_CMU_FREQ_156M) {
-            div = 3;
-        } else if (freq <= HAL_CMU_FREQ_208M) {
-            div = 2;
-        } else if (freq <= HAL_CMU_FREQ_260M) {
-            div = 1;
-        } else { // 390M
-            div = 0;
+        disable = CMU_SEL_OSC_SYS_DISABLE | CMU_SEL_OSCX2_SYS_DISABLE |
+            CMU_SEL_PLL_SYS_DISABLE | CMU_RSTN_DIV_SYS_DISABLE | CMU_BYPASS_DIV_SYS_DISABLE;
+    } else if (freq == HAL_CMU_FREQ_26M) {
+        enable = CMU_SEL_OSC_SYS_ENABLE;
+        disable = CMU_SEL_OSCX2_SYS_DISABLE |
+            CMU_SEL_PLL_SYS_DISABLE | CMU_RSTN_DIV_SYS_DISABLE | CMU_BYPASS_DIV_SYS_DISABLE;
+    } else if (freq == HAL_CMU_FREQ_52M) {
+        enable = CMU_SEL_OSCX2_SYS_ENABLE;
+        disable = CMU_SEL_PLL_SYS_DISABLE | CMU_RSTN_DIV_SYS_DISABLE | CMU_BYPASS_DIV_SYS_DISABLE;
+#ifndef OSC_26M_X4_AUD2BB
+    } else if (freq == HAL_CMU_FREQ_78M) {
+        enable = CMU_SEL_PLL_SYS_ENABLE | CMU_RSTN_DIV_SYS_ENABLE;
+        disable = CMU_BYPASS_DIV_SYS_DISABLE;
+        div = 1;
+    } else if (freq == HAL_CMU_FREQ_104M) {
+        enable = CMU_SEL_PLL_SYS_ENABLE | CMU_RSTN_DIV_SYS_ENABLE;
+        disable = CMU_BYPASS_DIV_SYS_DISABLE;
+        div = 0;
+#endif
+    } else {
+        if (low_sys_set) {
+            if (low_sys_freq == HAL_CMU_LOW_SYS_FREQ_13M) {
+                enable = CMU_SEL_PLL_SYS_ENABLE | CMU_BYPASS_DIV_SYS_ENABLE;
+                disable = CMU_RSTN_DIV_SYS_DISABLE;
+            } else {
+                enable = CMU_SEL_PLL_SYS_ENABLE | CMU_RSTN_DIV_SYS_ENABLE;
+                disable = CMU_BYPASS_DIV_SYS_DISABLE;
+                if (low_sys_freq == HAL_CMU_LOW_SYS_FREQ_6P5M) {
+                    div = 0;
+                } else if (low_sys_freq == HAL_CMU_LOW_SYS_FREQ_4P33M) {
+                    div = 1;
+                } else {
+                    div = 2;
+                }
+            }
+        } else {
+            enable = CMU_SEL_PLL_SYS_ENABLE | CMU_BYPASS_DIV_SYS_ENABLE;
+            disable = CMU_RSTN_DIV_SYS_DISABLE;
         }
-        break;
-    case HAL_CMU_FREQ_780M:
-    default:
-        enable = CMU_BYPASS_DIV_A7_ENABLE | CMU_SEL_A7_PLL_ENABLE;
-        disable = CMU_RSTN_DIV_A7_DISABLE;
-        break;
-    };
-
+    }
     if (div >= 0) {
-        lock = int_lock();
-        cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_A7, div);
-        int_unlock(lock);
+        cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_SYS, div);
     }
-
-    if (enable & CMU_SEL_A7_PLL_ENABLE) {
-        cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_A7_ENABLE;
-        if (enable & CMU_BYPASS_DIV_A7_ENABLE) {
-            cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_A7_ENABLE;
+    if (enable & CMU_SEL_PLL_SYS_ENABLE) {
+        cmu->SYS_CLK_ENABLE = CMU_RSTN_DIV_SYS_ENABLE;
+        if (enable & CMU_BYPASS_DIV_SYS_ENABLE) {
+            cmu->SYS_CLK_ENABLE = CMU_BYPASS_DIV_SYS_ENABLE;
         } else {
-            cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_A7_DISABLE;
+            cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_SYS_DISABLE;
         }
     }
     cmu->SYS_CLK_ENABLE = enable;
-    if (enable & CMU_SEL_A7_PLL_ENABLE) {
+    if (enable & CMU_SEL_PLL_SYS_ENABLE) {
         cmu->SYS_CLK_DISABLE = disable;
     } else {
-        cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_A7_DISABLE | CMU_BYPASS_DIV_A7_DISABLE);
-        cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_A7_DISABLE;
-        cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_A7_DISABLE;
+        cmu->SYS_CLK_DISABLE = disable & ~(CMU_RSTN_DIV_SYS_DISABLE | CMU_BYPASS_DIV_SYS_DISABLE);
+        cmu->SYS_CLK_DISABLE = CMU_BYPASS_DIV_SYS_DISABLE;
+        cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_SYS_DISABLE;
     }
 
+    int_unlock(lock);
+
     return 0;
 }
+#else
+SYS_SET_FREQ_FUNC(sys, SYS, {});
+#endif
 
-enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_dsp_get_freq(void)
+int hal_cmu_mem_set_freq(enum HAL_CMU_FREQ_T freq)
+{
+    return 0;
+}
+
+enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_sys_get_freq(void)
 {
     uint32_t sys_clk;
     uint32_t div;
 
     sys_clk = cmu->SYS_CLK_ENABLE;
 
-    if (sys_clk & CMU_SEL_A7_PLL_ENABLE) {
-        if (sys_clk & CMU_BYPASS_DIV_A7_ENABLE) {
-            return HAL_CMU_FREQ_780M;
+    if (sys_clk & CMU_SEL_PLL_SYS_ENABLE) {
+        if (sys_clk & CMU_BYPASS_DIV_SYS_ENABLE) {
+            return HAL_CMU_FREQ_208M;
         } else {
-            div = GET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_A7);
+            div = GET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_SYS);
             if (div == 0) {
-                return HAL_CMU_FREQ_390M;
+                return HAL_CMU_FREQ_104M;
             } else if (div == 1) {
-                return HAL_CMU_FREQ_260M;
-            } else if (div == 2) {
-                return HAL_CMU_FREQ_208M;
-            } else { // div == 3
-                return HAL_CMU_FREQ_156M;
+                // (div == 1): 69M
+                return HAL_CMU_FREQ_78M;
+            } else {
+                // (div == 2): 52M
+                // (div == 3): 42M
+                return HAL_CMU_FREQ_52M;
             }
         }
-    } else if (sys_clk & CMU_SEL_A7_FAST_ENABLE) {
-        if (sys_clk & CMU_SEL_A7_OSCX4_ENABLE) {
-            return HAL_CMU_FREQ_104M;
-        } else {
-            return HAL_CMU_FREQ_52M;
-        }
-    } else if (sys_clk & CMU_SEL_A7_SLOW_ENABLE) {
+    } else if (sys_clk & CMU_SEL_OSCX2_SYS_ENABLE) {
+        return HAL_CMU_FREQ_52M;
+    } else if (sys_clk & CMU_SEL_OSC_SYS_ENABLE) {
         return HAL_CMU_FREQ_26M;
     } else {
         return HAL_CMU_FREQ_32K;
@@ -1247,113 +797,47 @@ enum HAL_CMU_FREQ_T BOOT_TEXT_SRAM_LOC hal_cmu_dsp_get_freq(void)
 
 int BOOT_TEXT_SRAM_LOC hal_cmu_flash_select_pll(enum HAL_CMU_PLL_T pll)
 {
-    return 0;
-}
-
-int BOOT_TEXT_SRAM_LOC hal_cmu_flash1_select_pll(enum HAL_CMU_PLL_T pll)
-{
-    return 0;
+    return hal_cmu_sys_select_pll(pll);
 }
 
 int hal_cmu_mem_select_pll(enum HAL_CMU_PLL_T pll)
 {
-    return 0;
+    return hal_cmu_sys_select_pll(pll);
 }
 
-int hal_cmu_dsp_select_pll(enum HAL_CMU_PLL_T pll)
+// hal_cmu_flash_select_pll() requires in BOOT_TEXT_SRAM_LOC
+int BOOT_TEXT_SRAM_LOC hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll)
 {
     uint32_t lock;
-    uint32_t set;
-    uint32_t clr;
-
-    if (pll == HAL_CMU_PLL_USB) {
-        set = AON_CMU_SEL_A7_PLLUSB | AON_CMU_SEL_A7_PLLBB;
-        clr = 0;
-    } else if (pll == HAL_CMU_PLL_DSP) {
-        set = 0;
-        clr = AON_CMU_SEL_A7_PLLUSB | AON_CMU_SEL_A7_PLLBB;
-    } else if (pll == HAL_CMU_PLL_BB) {
-        set = AON_CMU_SEL_A7_PLLBB;
-        clr = AON_CMU_SEL_A7_PLLUSB;
-    } else {
-        // == HAL_CMU_PLL_DDR or == HAL_CMU_PLL_BB_PSRAM or >= HAL_CMU_PLL_QTY
-        return 1;
-    }
-
-    lock = int_lock();
-    aoncmu->DSP_PLL_SELECT = (aoncmu->DSP_PLL_SELECT & ~clr) | set;
-    int_unlock(lock);
-
-    return 0;
-}
+    uint32_t sel;
 
-int BOOT_TEXT_FLASH_LOC hal_cmu_sys_select_pll(enum HAL_CMU_PLL_T pll)
-{
-    uint32_t lock;
-    uint32_t set;
-    uint32_t clr;
-
-    if (pll == HAL_CMU_PLL_USB) {
-        set = AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
-        clr = AON_CMU_SEL_MCU_PLLBB_PS;
-    } else if (pll == HAL_CMU_PLL_DSP) {
-        set = AON_CMU_SEL_MCU_PLLA7USB;
-        clr = AON_CMU_SEL_MCU_PLLBB_PS | AON_CMU_SEL_MCU_PLLUSB;
-    } else if (pll == HAL_CMU_PLL_BB) {
-        set = 0;
-        clr = AON_CMU_SEL_MCU_PLLBB_PS | AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
-    } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
-        set = AON_CMU_SEL_MCU_PLLBB_PS;
-        clr = AON_CMU_SEL_MCU_PLLUSB | AON_CMU_SEL_MCU_PLLA7USB;
-    } else {
-        // == HAL_CMU_PLL_DDR or >= HAL_CMU_PLL_QTY
+    if (pll >= HAL_CMU_PLL_QTY) {
         return 1;
     }
 
     lock = int_lock();
-    aoncmu->FLS_PSR_CLK = (aoncmu->FLS_PSR_CLK & ~clr) | set;
+    // 0/1:bbpll, 2:audpll, 3:usbpll
+    sel = (pll == HAL_CMU_PLL_AUD) ? 2 : 0;
+    aoncmu->CLK_SELECT = SET_BITFIELD(aoncmu->CLK_SELECT, AON_CMU_SEL_PLL_SYS, sel);
     int_unlock(lock);
 
     return 0;
 }
 
-int BOOT_TEXT_FLASH_LOC hal_cmu_audio_select_pll(enum HAL_CMU_PLL_T pll)
-{
-    if (pll == HAL_CMU_PLL_BB) {
-        aoncmu->PCM_I2S_CLK &= ~AON_CMU_SEL_AUD_PLLUSB;
-    } else {
-        aoncmu->PCM_I2S_CLK |= AON_CMU_SEL_AUD_PLLUSB;
-    }
-
-    return 0;
-}
-
 int hal_cmu_get_pll_status(enum HAL_CMU_PLL_T pll)
 {
-    bool en;
-
-    if (pll == HAL_CMU_PLL_USB) {
-        en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE);
-    } else if (pll == HAL_CMU_PLL_DDR) {
-        en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE);
-    } else if (pll == HAL_CMU_PLL_DSP) {
-        en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLA7_ENABLE);
-    } else if (pll == HAL_CMU_PLL_BB) {
-        en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLBB_ENABLE);
-    } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
-        en = !!(aoncmu->TOP_CLK_ENABLE & AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE);
-    } else {
-        en = false;
-    }
-
-    return en;
+    return !!(aoncmu->TOP_CLK_ENABLE & ((pll == HAL_CMU_PLL_AUD) ? AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE : AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE));
 }
 
-int BOOT_TEXT_FLASH_LOC hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
+int hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
 {
     uint32_t pu_val;
     uint32_t en_val;
+    uint32_t check;
     uint32_t lock;
+    uint32_t sel;
+    uint32_t start;
+    uint32_t timeout;
 
     if (pll >= HAL_CMU_PLL_QTY) {
         return 1;
@@ -1362,66 +846,80 @@ int BOOT_TEXT_FLASH_LOC hal_cmu_pll_enable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_
         return 2;
     }
 
-    if (pll == HAL_CMU_PLL_USB) {
-        pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_PS_ENABLE;
-        en_val = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
-    } else if (pll == HAL_CMU_PLL_DDR) {
-        pu_val = AON_CMU_PU_PLLDDR_ENABLE;
-        en_val = AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE;
-    } else if (pll == HAL_CMU_PLL_DSP) {
-        pu_val = AON_CMU_PU_PLLA7_ENABLE;
-        en_val = AON_CMU_EN_CLK_TOP_PLLA7_ENABLE;
-    } else if (pll == HAL_CMU_PLL_BB) {
-#ifdef BBPLL_USE_DSI_MCUPLL
-        pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_MCU_ENABLE;
-#else
-        pu_val = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_MCU_ENABLE;
+#ifdef USB_USE_USBPLL
+    if (pll == HAL_CMU_PLL_USB && user == HAL_CMU_PLL_USER_USB) {
+        pll = HAL_CMU_PLL_USB_HS;
+    }
 #endif
-        en_val = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
-    } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
-#ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
-        pu_val = AON_CMU_PU_PLLDSI_ENABLE | AON_CMU_PU_PLLDSI_DIV_PS_ENABLE;
-#else
-        pu_val = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_PS_ENABLE;
+
+    if (pll == HAL_CMU_PLL_AUD) {
+        pu_val = AON_CMU_PU_PLLAUD_ENABLE;
+        en_val = AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE;
+        check = AON_CMU_LOCK_PLLAUD;
+#ifdef USB_USE_USBPLL
+    } else if (pll == HAL_CMU_PLL_USB_HS) {
+        pu_val = AON_CMU_PU_PLLUSB_ENABLE;
+        en_val = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
+        check = AON_CMU_LOCK_PLLUSB;
 #endif
-        en_val = AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE;
-    } else if (pll == HAL_CMU_PLL_DSI) {
-        pu_val = AON_CMU_PU_PLLDSI_ENABLE;
-        en_val = 0;
     } else {
-        pu_val = 0;
-        en_val = 0;
+        pu_val = AON_CMU_PU_PLLBB_ENABLE;
+        en_val = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
+        check = AON_CMU_LOCK_PLLBB;
     }
 
     lock = int_lock();
-
     if (pll_user_map[pll] == 0 || user == HAL_CMU_PLL_USER_ALL) {
 #ifndef ROM_BUILD
         pmu_pll_div_reset_set(pll);
 #endif
-        aoncmu->PLL_ENABLE = pu_val;
+        aoncmu->TOP_CLK_ENABLE = pu_val;
 #ifndef ROM_BUILD
         hal_sys_timer_delay_us(20);
         pmu_pll_div_reset_clear(pll);
         // Wait at least 10us for clock ready
-        hal_sys_timer_delay_us(10);
 #endif
-        aoncmu->TOP_CLK_ENABLE = en_val;
+    } else {
+        check = 0;
     }
     if (user < HAL_CMU_PLL_USER_QTY) {
         pll_user_map[pll] |= (1 << user);
-    } else if (user == HAL_CMU_PLL_USER_ALL) {
-        pll_user_map[pll] |= ((1 << user) - 1);
     }
+    if (user == HAL_CMU_PLL_USER_AUD) {
+        // 0/1:audpll, 2:bbpll, 3:usbpll
+        sel = (pll == HAL_CMU_PLL_AUD) ? 0 : 2;
+        aoncmu->CLK_SELECT = SET_BITFIELD(aoncmu->CLK_SELECT, AON_CMU_SEL_PLL_AUD, sel);
+    }
+    // HAL_CMU_PLL_USER_SYS selects PLL in hal_cmu_sys_select_pll()
     int_unlock(lock);
 
-    return 0;
+    start = hal_sys_timer_get();
+    timeout = HAL_CMU_PLL_LOCKED_TIMEOUT;
+    do {
+        if (check) {
+            if (aoncmu->CODEC_DIV & check) {
+                //break;
+            }
+        } else {
+            if (aoncmu->TOP_CLK_ENABLE & en_val) {
+                break;
+            }
+        }
+    } while ((hal_sys_timer_get() - start) < timeout);
+
+    aoncmu->TOP_CLK_ENABLE = en_val;
+
+#ifndef USB_USE_USBPLL
+    if (pll == HAL_CMU_PLL_USB && user == HAL_CMU_PLL_USER_USB) {
+        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB2_ENABLE;
+    }
+#endif
+
+    return (aoncmu->CODEC_DIV & check) ? 0 : 2;
 }
 
-int BOOT_TEXT_FLASH_LOC hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
+int hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU_PLL_USER_T user)
 {
-    uint32_t pu_val;
-    uint32_t en_val;
     uint32_t lock;
 
     if (pll >= HAL_CMU_PLL_QTY) {
@@ -1431,75 +929,31 @@ int BOOT_TEXT_FLASH_LOC hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU
         return 2;
     }
 
-    if (pll == HAL_CMU_PLL_USB) {
-        pu_val = 0;
-        en_val = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
-    } else if (pll == HAL_CMU_PLL_DDR) {
-        pu_val = AON_CMU_PU_PLLDDR_DISABLE;
-        en_val = AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE;
-    } else if (pll == HAL_CMU_PLL_DSP) {
-        pu_val = AON_CMU_PU_PLLA7_DISABLE;
-        en_val = AON_CMU_EN_CLK_TOP_PLLA7_DISABLE;
-    } else if (pll == HAL_CMU_PLL_BB) {
-#ifdef BBPLL_USE_DSI_MCUPLL
-        pu_val = AON_CMU_PU_PLLDSI_DIV_MCU_DISABLE;
-#else
-        pu_val = AON_CMU_PU_PLLBB_DIV_MCU_DISABLE;
-#endif
-        en_val = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
-    } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
-#ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
-        pu_val = AON_CMU_PU_PLLDSI_DIV_PS_DISABLE;
+    if (pll == HAL_CMU_PLL_USB && user == HAL_CMU_PLL_USER_USB) {
+#ifdef USB_USE_USBPLL
+        pll = HAL_CMU_PLL_USB_HS;
 #else
-        pu_val = AON_CMU_PU_PLLBB_DIV_PS_DISABLE;
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB2_DISABLE;
 #endif
-        en_val = AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE;
-    } else if (pll == HAL_CMU_PLL_DSI) {
-        pu_val = 0;
-        en_val = 0;
-    } else {
-        pu_val = 0;
-        en_val = 0;
     }
 
     lock = int_lock();
     if (user < HAL_CMU_PLL_USER_ALL) {
         pll_user_map[pll] &= ~(1 << user);
-    } else if (user == HAL_CMU_PLL_USER_ALL) {
-        pll_user_map[pll] = 0;
     }
     if (pll_user_map[pll] == 0 || user == HAL_CMU_PLL_USER_ALL) {
-#if defined(BBPLL_USE_DSI_MCUPLL) && defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
-        if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0 &&
-            pll_user_map[HAL_CMU_PLL_USB] == 0 && pll_user_map[HAL_CMU_PLL_DSI] == 0)
-            pu_val |= AON_CMU_PU_PLLBB_DISABLE;
-#elif defined(BBPLL_USE_DSI_MCUPLL) && !defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
-        if (pll == HAL_CMU_PLL_BB || pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
-            if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_USB] == 0 &&
-                    pll_user_map[HAL_CMU_PLL_DSI] == 0)
-                pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
-        } else if (pll == HAL_CMU_PLL_BB_PSRAM) {
-            pu_val |= AON_CMU_PU_PLLBB_DISABLE;
-        }
-#elif !defined(BBPLL_USE_DSI_MCUPLL) && defined(BB_PSRAMPLL_USE_DSI_PSRAMPLL)
-        if (pll == HAL_CMU_PLL_BB_PSRAM || pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
-            if (pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0 && pll_user_map[HAL_CMU_PLL_USB] == 0 &&
-                    pll_user_map[HAL_CMU_PLL_DSI] == 0)
-                pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
-        } else if (pll == HAL_CMU_PLL_BB) {
-            pu_val |= AON_CMU_PU_PLLBB_DISABLE;
-        }
-#else
-        if (pll == HAL_CMU_PLL_USB || pll == HAL_CMU_PLL_DSI) {
-            if (pll_user_map[HAL_CMU_PLL_USB] == 0 && pll_user_map[HAL_CMU_PLL_DSI] == 0)
-                pu_val |= AON_CMU_PU_PLLDSI_DISABLE;
-        } else if (pll == HAL_CMU_PLL_BB || pll == HAL_CMU_PLL_BB_PSRAM) {
-            if (pll_user_map[HAL_CMU_PLL_BB] == 0 && pll_user_map[HAL_CMU_PLL_BB_PSRAM] == 0)
-                pu_val |= AON_CMU_PU_PLLBB_DISABLE;
-        }
+        if (pll == HAL_CMU_PLL_AUD) {
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLAUD_DISABLE;
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLAUD_DISABLE;
+#ifdef USB_USE_USBPLL
+        } else if (pll == HAL_CMU_PLL_USB_HS) {
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLUSB_DISABLE;
 #endif
-        aoncmu->TOP_CLK_DISABLE = en_val;
-        aoncmu->PLL_DISABLE = pu_val;
+        } else {
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLBB_DISABLE;
+        }
     }
     int_unlock(lock);
 
@@ -1508,159 +962,119 @@ int BOOT_TEXT_FLASH_LOC hal_cmu_pll_disable(enum HAL_CMU_PLL_T pll, enum HAL_CMU
 
 void BOOT_TEXT_FLASH_LOC hal_cmu_low_freq_mode_init(void)
 {
+#if defined(MCU_HIGH_PERFORMANCE_MODE)
+    hal_cmu_sys_select_pll(HAL_CMU_PLL_USB);
+#else
+    // No need to switch to USB PLL, for there is a clock gate and a clock mux
+    // in front of the AUD/USB switch
+    hal_cmu_sys_select_pll(HAL_CMU_PLL_AUD);
+#endif
+
+//#ifdef FLASH_LOW_SPEED
+#ifdef OSC_26M_X4_AUD2BB
+    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_SYS;
+#endif
+//#endif
 }
 
 void hal_cmu_low_freq_mode_enable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq)
 {
-    enum HAL_CMU_PLL_T pll;
-    enum HAL_CMU_FREQ_T switch_freq;
-
-    // TODO: Select the PLL used by sys
-    pll = HAL_CMU_PLL_BB;
+    // TODO: Need to lock irq?
+    enum HAL_CMU_PLL_T POSSIBLY_UNUSED pll;
 
-#ifdef OSC_26M_X4_AUD2BB
-    switch_freq = HAL_CMU_FREQ_104M;
+#if defined(MCU_HIGH_PERFORMANCE_MODE)
+    pll = HAL_CMU_PLL_USB;
 #else
-    switch_freq = HAL_CMU_FREQ_52M;
+    pll = HAL_CMU_PLL_AUD;
 #endif
 
-    if (old_freq > switch_freq && new_freq <= switch_freq) {
+#ifdef OSC_26M_X4_AUD2BB
+    if (new_freq <= HAL_CMU_FREQ_52M) {
+        aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_SYS;
+    }
+    if (new_freq <= HAL_CMU_FREQ_104M && old_freq > HAL_CMU_FREQ_104M) {
+        if (new_freq > HAL_CMU_FREQ_52M) {
+            // PLL is in use now. Switch to X2 first.
+            hal_cmu_sys_set_freq(HAL_CMU_FREQ_52M);
+            aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_SYS;
+            // X4 is in use now
+            hal_cmu_sys_set_freq(new_freq);
+        }
+        hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_SYS);
+    }
+#else
+#ifdef FLASH_LOW_SPEED
+    if (old_freq > HAL_CMU_FREQ_52M && new_freq <= HAL_CMU_FREQ_52M) {
         hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_SYS);
     }
+#endif
+#endif
 }
 
 void hal_cmu_low_freq_mode_disable(enum HAL_CMU_FREQ_T old_freq, enum HAL_CMU_FREQ_T new_freq)
 {
-    enum HAL_CMU_PLL_T pll;
-    enum HAL_CMU_FREQ_T switch_freq;
-
-    // TODO: Select the PLL used by sys
-    pll = HAL_CMU_PLL_BB;
+    // TODO: Need to lock irq?
+    enum HAL_CMU_PLL_T POSSIBLY_UNUSED pll;
 
-#ifdef OSC_26M_X4_AUD2BB
-    switch_freq = HAL_CMU_FREQ_104M;
+#if defined(MCU_HIGH_PERFORMANCE_MODE)
+    pll = HAL_CMU_PLL_USB;
 #else
-    switch_freq = HAL_CMU_FREQ_52M;
+    pll = HAL_CMU_PLL_AUD;
 #endif
 
-    if (old_freq <= switch_freq && new_freq > switch_freq) {
+#ifdef OSC_26M_X4_AUD2BB
+    if (new_freq <= HAL_CMU_FREQ_52M) {
+        aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_SYS;
+    } else if (new_freq <= HAL_CMU_FREQ_104M) {
+        aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_SYS;
+    } else {
+        if (old_freq <= HAL_CMU_FREQ_104M) {
+            hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_SYS);
+            if (old_freq > HAL_CMU_FREQ_52M) {
+                // X4 is in use now. Switch to X2 before stopping X4
+                hal_cmu_sys_set_freq(HAL_CMU_FREQ_52M);
+            }
+            aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_SYS;
+        }
+    }
+#else
+#ifdef FLASH_LOW_SPEED
+    if (old_freq <= HAL_CMU_FREQ_52M && new_freq > HAL_CMU_FREQ_52M) {
         hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_SYS);
     }
-}
-
-void hal_cmu_rom_enable_pll(void)
-{
-    hal_cmu_sys_select_pll(HAL_CMU_PLL_BB);
-    hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_SYS);
-
-#if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
-    hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
+#endif
 #endif
 }
 
-void BOOT_TEXT_FLASH_LOC hal_cmu_sram_init()
+int hal_cmu_codec_adc_set_div(uint32_t div)
 {
-    uint32_t mcu_ram_size;
-
-#if defined(ARM_CMSE)
-    mcu_ram_size = RAM5_BASE + RAM5_SIZE - RAM0_BASE;
-#elif defined(ARM_CMNS)
-    mcu_ram_size = RAM_SIZE + RAM_S_SIZE;
-#else
-    mcu_ram_size = RAM_SIZE;
-#endif
-#if defined(CHIP_HAS_CP) && ((RAMCP_SIZE > 0) || (RAMCPX_SIZE > 0))
-    mcu_ram_size += (RAMCP_SIZE + RAMCPX_SIZE);
-#endif
-#ifdef __BT_RAMRUN__
-    mcu_ram_size += BT_RAMRUN_SIZE;
-#endif
+    uint32_t lock;
 
-    switch (mcu_ram_size) {
-    case RAM1_BASE - RAM0_BASE: //RAM0
-        cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x0);
-        break;
-    case RAM2_BASE - RAM0_BASE: //RAM0,1
-        cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x1);
-        break;
-    case RAM3_BASE - RAM0_BASE: //RAM0,1,2
-        cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x3);
-        break;
-    case RAM4_BASE - RAM0_BASE: //RAM0,1,2,3
-        cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x7);
-        break;
-    case RAM5_BASE - RAM0_BASE: //RAM0,1,2,3,4
-        cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0xF);
-        break;
-    case (RAM5_BASE + RAM5_SIZE - RAM0_BASE): //RAM0,1,2,3,4,5
-    default:
-        cmu->WAKEUP_CLK_CFG = SET_BITFIELD(cmu->WAKEUP_CLK_CFG, CMU_CFG_SRAM_IN_M33, 0x1F);
-        break;
+    if (div < 2) {
+        return 1;
     }
-}
 
-void hal_cmu_programmer_enable_pll(void)
-{
-    hal_cmu_sram_init();
-    hal_cmu_dma_req_init();
-
-    hal_cmu_flash_select_pll(HAL_CMU_PLL_BB);
-    hal_cmu_sys_select_pll(HAL_CMU_PLL_BB);
-    hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_SYS);
+    div -= 2;
+    lock = int_lock();
+    aoncmu->CODEC_DIV = SET_BITFIELD(aoncmu->CODEC_DIV, AON_CMU_CFG_DIV_CODEC, div);
+    int_unlock(lock);
 
-#if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
-    hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
-#endif
+    return 0;
 }
 
-void BOOT_TEXT_FLASH_LOC hal_cmu_init_pll_selection(void)
+uint32_t hal_cmu_codec_adc_get_div(void)
 {
-    enum HAL_CMU_PLL_T sys;
-
-#if !defined(ARM_CMNS)
-    // Disable the PLL which might be enabled in ROM
-    hal_cmu_pll_disable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_ALL);
-#endif
-
-#ifdef BBPLL_USE_DSI_MCUPLL
-    aoncmu->FLS_PSR_CLK |= AON_CMU_SEL_MCU_PLLDSI;
-#endif
-
-#ifdef BB_PSRAMPLL_USE_DSI_PSRAMPLL
-    aoncmu->FLS_PSR_CLK |= AON_CMU_SEL_PSR_PLLDSI;
-#endif
-
-#ifdef SYS_USE_USBPLL
-    sys = HAL_CMU_PLL_USB;
-#elif defined(SYS_USE_BB_PSRAMPLL)
-    sys = HAL_CMU_PLL_BB_PSRAM;
-#elif defined(SYS_USE_DSPPLL)
-    sys = HAL_CMU_PLL_DSP;
-#else
-    sys = HAL_CMU_PLL_BB;
-#endif
-    hal_cmu_sys_select_pll(sys);
-
-#ifdef AUDIO_USE_BBPLL
-    hal_cmu_audio_select_pll(HAL_CMU_PLL_BB);
-#else
-    hal_cmu_audio_select_pll(HAL_CMU_PLL_USB);
-#endif
+    return GET_BITFIELD(aoncmu->CODEC_DIV, AON_CMU_CFG_DIV_CODEC) + 2;
+}
 
-#ifndef ULTRA_LOW_POWER
-    hal_cmu_pll_enable(sys, HAL_CMU_PLL_USER_SYS);
-#endif
-#if !(defined(FLASH_LOW_SPEED) || defined(OSC_26M_X4_AUD2BB))
-    hal_cmu_pll_enable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_FLASH);
-#endif
-#if defined(PSRAM_ENABLE) && !defined(PSRAM_LOW_SPEED)
-    hal_cmu_pll_enable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_PSRAM);
-#endif
+int hal_cmu_codec_dac_set_div(uint32_t div)
+{
+    return hal_cmu_codec_adc_set_div(div);
+}
 
-    hal_cmu_dsp_timer0_select_slow();
-#ifdef TIMER1_BASE
-    hal_cmu_dsp_timer1_select_fast();
-#endif
+uint32_t hal_cmu_codec_dac_get_div(void)
+{
+    return hal_cmu_codec_adc_get_div();;
 }
 
 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
@@ -1675,7 +1089,7 @@ void hal_cmu_audio_26m_x4_enable(enum CMU_AUD_26M_X4_USER_T user)
     lock = int_lock();
 
     if (aud_26m_x4_map == 0) {
-        aoncmu->PCM_I2S_CLK |= AON_CMU_SEL_AUD_X4;
+        aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_AUD;
     }
     aud_26m_x4_map |= (1 << user);
 
@@ -1695,7 +1109,7 @@ void hal_cmu_audio_26m_x4_disable(enum CMU_AUD_26M_X4_USER_T user)
     if (aud_26m_x4_map & (1 << user)) {
         aud_26m_x4_map &= ~(1 << user);
         if (aud_26m_x4_map == 0) {
-            aoncmu->PCM_I2S_CLK &= ~AON_CMU_SEL_AUD_X4;
+            aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_AUD;
         }
     }
 
@@ -1711,14 +1125,14 @@ void hal_cmu_codec_iir_enable(uint32_t speed)
     uint32_t div;
     uint32_t cfg_speed = 0;
 
-    mask = AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2 | AON_CMU_BYPASS_DIV_CODECIIR;
+    mask = AON_CMU_SEL_OSC_CODECIIR | AON_CMU_SEL_OSCX2_CODECIIR | AON_CMU_BYPASS_DIV_CODECIIR;
     val = 0;
 
     if (speed <= 26000000) {
-        val |= AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2;
+        val |= AON_CMU_SEL_OSC_CODECIIR | AON_CMU_SEL_OSCX2_CODECIIR;
         cfg_speed = 26000000;
     } else if (speed <= 52000000) {
-        val |= AON_CMU_SEL_CODECIIR_OSCX2;
+        val |= AON_CMU_SEL_OSCX2_CODECIIR;
         cfg_speed = 52000000;
     } else {
 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
@@ -1739,11 +1153,7 @@ void hal_cmu_codec_iir_enable(uint32_t speed)
                 val |= AON_CMU_BYPASS_DIV_CODECIIR;
                 cfg_speed = HAL_CMU_AUD_PLL_CLOCK;
             }
-            analog_aud_freq_pll_config(CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV);
-            analog_aud_pll_open(ANA_AUD_PLL_USER_IIR);
         }
-
-       //pmu_iir_freq_config(cfg_speed);
     }
 
     ASSERT(speed <= cfg_speed, "%s: speed %u should <= cfg_speed %u", __func__, speed, cfg_speed);
@@ -1752,7 +1162,7 @@ void hal_cmu_codec_iir_enable(uint32_t speed)
     aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~mask) | val;
     int_unlock(lock);
 
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECIIR_ENABLE;
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODEC_IIR_ENABLE;
 
     aocmu_reg_update_wait();
 }
@@ -1761,26 +1171,18 @@ void hal_cmu_codec_iir_disable(void)
 {
     uint32_t lock;
     uint32_t val;
-    bool high_speed;
 
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECIIR_DISABLE;
+    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_IIR_DISABLE;
 
 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
     hal_cmu_audio_26m_x4_disable(CMU_AUD_26M_X4_USER_IIR);
 #endif
 
-    high_speed = !(aoncmu->CODEC_IIR & AON_CMU_SEL_CODECIIR_OSC);
-
-    val = AON_CMU_SEL_CODECIIR_OSC | AON_CMU_SEL_CODECIIR_OSCX2;
+    val = AON_CMU_SEL_OSC_CODECIIR | AON_CMU_SEL_OSCX2_CODECIIR;
 
     lock = int_lock();
     aoncmu->CODEC_IIR |= val;
     int_unlock(lock);
-
-    if (high_speed) {
-        //pmu_iir_freq_config(0);
-    }
-    analog_aud_pll_close(ANA_AUD_PLL_USER_IIR);
 }
 
 int hal_cmu_codec_iir_set_div(uint32_t div)
@@ -1807,24 +1209,20 @@ void hal_cmu_codec_rs_enable(uint32_t speed)
     uint32_t div;
     uint32_t cfg_speed = 0;
 
-    mask = AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2 | AON_CMU_BYPASS_DIV_CODECRS0;
-    mask |= AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2 | AON_CMU_BYPASS_DIV_CODECRS1;
+    mask = AON_CMU_SEL_OSC_CODECRS | AON_CMU_SEL_OSCX2_CODECRS | AON_CMU_BYPASS_DIV_CODECRS;
     val = 0;
 
     if (speed <= 26000000) {
-        val |= AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2;
-        val |= AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2;
+        val |= AON_CMU_SEL_OSC_CODECRS | AON_CMU_SEL_OSCX2_CODECRS;
         cfg_speed = 26000000;
     } else if (speed <= 52000000) {
-        val |= AON_CMU_SEL_CODECRS0_OSCX2;
-        val |= AON_CMU_SEL_CODECRS1_OSCX2;
+        val |= AON_CMU_SEL_OSCX2_CODECRS;
         cfg_speed = 52000000;
     } else {
 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
         if (hal_cmu_get_audio_resample_status()) {
             hal_cmu_audio_26m_x4_enable(CMU_AUD_26M_X4_USER_RS);
-            val |= AON_CMU_BYPASS_DIV_CODECRS0;
-            val |= AON_CMU_BYPASS_DIV_CODECRS1;
+            val |= AON_CMU_BYPASS_DIV_CODECRS;
             cfg_speed = 104000000;
         }
         else
@@ -1836,13 +1234,12 @@ void hal_cmu_codec_rs_enable(uint32_t speed)
                 hal_cmu_codec_rs_set_div(div);
                 cfg_speed = HAL_CMU_AUD_PLL_CLOCK / div;
             } else {
-                val |= AON_CMU_BYPASS_DIV_CODECRS0;
-                val |= AON_CMU_BYPASS_DIV_CODECRS1;
+                val |= AON_CMU_BYPASS_DIV_CODECRS;
                 cfg_speed = HAL_CMU_AUD_PLL_CLOCK;
             }
-            analog_aud_freq_pll_config(CODEC_FREQ_48K_SERIES, CODEC_PLL_DIV);
-            analog_aud_pll_open(ANA_AUD_PLL_USER_RS);
         }
+
+        pmu_rs_freq_config(cfg_speed);
     }
 
     ASSERT(speed <= cfg_speed, "%s: speed %u should <= cfg_speed %u", __func__, speed, cfg_speed);
@@ -1851,7 +1248,7 @@ void hal_cmu_codec_rs_enable(uint32_t speed)
     aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~mask) | val;
     int_unlock(lock);
 
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECRS0_ENABLE | AON_CMU_EN_CLK_CODECRS1_ENABLE;
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODEC_RS_ENABLE;
 
     aocmu_reg_update_wait();
 }
@@ -1859,19 +1256,23 @@ void hal_cmu_codec_rs_enable(uint32_t speed)
 void hal_cmu_codec_rs_disable(void)
 {
     uint32_t lock;
-    //bool high_speed;
+    bool high_speed;
 
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECRS0_DISABLE | AON_CMU_EN_CLK_CODECRS1_DISABLE;
+    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_RS_DISABLE;
 
 #if defined(__AUDIO_RESAMPLE__) && defined(ANA_26M_X4_ENABLE)
     hal_cmu_audio_26m_x4_disable(CMU_AUD_26M_X4_USER_RS);
 #endif
 
+    high_speed = !(aoncmu->CODEC_IIR & AON_CMU_SEL_OSC_CODECRS);
+
     lock = int_lock();
-    aoncmu->CODEC_IIR |= AON_CMU_SEL_CODECRS0_OSC | AON_CMU_SEL_CODECRS0_OSCX2 | AON_CMU_SEL_CODECRS1_OSC | AON_CMU_SEL_CODECRS1_OSCX2;
+    aoncmu->CODEC_IIR |= AON_CMU_SEL_OSC_CODECRS | AON_CMU_SEL_OSCX2_CODECRS;
     int_unlock(lock);
 
-    analog_aud_pll_close(ANA_AUD_PLL_USER_RS);
+    if (high_speed) {
+        pmu_rs_freq_config(0);
+    }
 }
 
 int hal_cmu_codec_rs_set_div(uint32_t div)
@@ -1884,69 +1285,106 @@ int hal_cmu_codec_rs_set_div(uint32_t div)
 
     div -= 2;
     lock = int_lock();
-    aoncmu->CODEC_IIR = (aoncmu->CODEC_IIR & ~(AON_CMU_CFG_DIV_CODECRS0_MASK | AON_CMU_CFG_DIV_CODECRS1_MASK)) |
-        AON_CMU_CFG_DIV_CODECRS0(div) | AON_CMU_CFG_DIV_CODECRS1(div);
+    aoncmu->CODEC_IIR = SET_BITFIELD(aoncmu->CODEC_IIR, AON_CMU_CFG_DIV_CODECRS, div);
     int_unlock(lock);
 
     return 0;
 }
 
-void hal_cmu_codec_clock_enable(void)
+void hal_cmu_anc_enable(enum HAL_CMU_ANC_CLK_USER_T user)
 {
-    uint32_t lock;
-
-    lock = int_lock();
-    aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~(AON_CMU_SEL_CODEC_OSC | AON_CMU_SEL_CODECHCLK_OSCX2 | AON_CMU_SEL_CODEC_ANA_2 | AON_CMU_SEL_CODECHCLK_PLL)) |
-       AON_CMU_SEL_CODEC_OSC_2;
-    int_unlock(lock);
+    anc_enabled = true;
+}
 
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODECHCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
-    hal_cmu_clock_enable(HAL_CMU_MOD_H_CODEC);
+void hal_cmu_anc_disable(enum HAL_CMU_ANC_CLK_USER_T user)
+{
+    anc_enabled = false;
 }
 
-void hal_cmu_codec_clock_disable(void)
+int hal_cmu_anc_get_status(enum HAL_CMU_ANC_CLK_USER_T user)
 {
-    hal_cmu_clock_disable(HAL_CMU_MOD_H_CODEC);
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECHCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE;
+    return anc_enabled;
 }
 
-void hal_cmu_codec_vad_clock_enable(int type)
+void hal_cmu_codec_clock_enable(void)
 {
-    uint32_t lock;
+    uint32_t clk;
 
-    lock = int_lock();
-    aoncmu->CODEC_DIV |= (AON_CMU_EN_VAD_IIR | AON_CMU_EN_VAD_RS);
-    int_unlock(lock);
+#ifdef CODEC_CLK_FROM_ANA
+    // Always use ANA clock
+    clk = AON_CMU_EN_CLK_CODEC_HCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
+#else
+#ifdef __AUDIO_RESAMPLE__
+    if (hal_cmu_get_audio_resample_status()) {
+        uint32_t lock;
+        lock = int_lock();
+        aoncmu->CODEC_DIV |= AON_CMU_SEL_OSC_CODEC;
+        int_unlock(lock);
 
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSC_ENABLE | AON_CMU_EN_CLK_VAD32K_ENABLE;
-    if (type == AUD_VAD_TYPE_MIX) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_DISABLE;
+#ifdef RESAMPLE_CODEC_CLK_ANA
+        clk = AON_CMU_EN_CLK_CODEC_HCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
+#else
+        clk = AON_CMU_EN_CLK_PLL_CODEC_ENABLE | AON_CMU_EN_CLK_CODEC_HCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
+        if (hal_get_chip_metal_id() == HAL_CHIP_METAL_ID_0) {
+            // Force codec to use analog clock
+            clk &= ~AON_CMU_EN_CLK_PLL_CODEC_ENABLE;
+        }
+#endif
+    }
+    else
+#endif
+    {
+        clk = AON_CMU_EN_CLK_PLL_CODEC_ENABLE | AON_CMU_EN_CLK_CODEC_HCLK_ENABLE | AON_CMU_EN_CLK_CODEC_ENABLE;
     }
+#endif
+    aoncmu->TOP_CLK_ENABLE = clk;
+    hal_cmu_clock_enable(HAL_CMU_MOD_H_CODEC);
 }
 
-void hal_cmu_codec_vad_clock_disable(int type)
+void hal_cmu_codec_clock_disable(void)
 {
-    uint32_t lock;
+    uint32_t clk;
 
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSC_DISABLE | AON_CMU_EN_CLK_VAD32K_DISABLE;
-    if (type == AUD_VAD_TYPE_MIX) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_CODEC_ENABLE;
+    hal_cmu_clock_disable(HAL_CMU_MOD_H_CODEC);
+
+#ifdef CODEC_CLK_FROM_ANA
+    clk = AON_CMU_EN_CLK_CODEC_HCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE;
+#else
+#ifdef __AUDIO_RESAMPLE__
+    if (hal_cmu_get_audio_resample_status()) {
+        uint32_t lock;
+        lock = int_lock();
+        aoncmu->CODEC_DIV &= ~AON_CMU_SEL_OSC_CODEC;
+        int_unlock(lock);
+
+        clk = AON_CMU_EN_CLK_CODEC_HCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE;
     }
+    else
+#endif
+    {
+        clk = AON_CMU_EN_CLK_PLL_CODEC_DISABLE | AON_CMU_EN_CLK_CODEC_HCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE;
+    }
+#endif
+    aoncmu->TOP_CLK_DISABLE = clk;
+}
 
-    lock = int_lock();
-    aoncmu->CODEC_DIV &= ~(AON_CMU_EN_VAD_IIR | AON_CMU_EN_VAD_RS);
-    int_unlock(lock);
+void hal_cmu_codec_vad_clock_enable(uint32_t enabled)
+{
+    if (enabled) {
+        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSC_ENABLE | AON_CMU_EN_CLK_32K_CODEC_ENABLE;
+    } else {
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSC_DISABLE | AON_CMU_EN_CLK_32K_CODEC_DISABLE;
+    }
 }
 
 void hal_cmu_codec_reset_set(void)
 {
-    aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_CODEC_SET;
+    aoncmu->RESET_SET = AON_CMU_SOFT_RSTN_CODEC_SET;
 }
 
 void hal_cmu_codec_reset_clear(void)
 {
-    hal_cmu_reset_clear(HAL_CMU_MOD_H_CODEC);
-    aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_CODEC_CLR;
+    aoncmu->RESET_CLR = AON_CMU_SOFT_RSTN_CODEC_CLR;
     aocmu_reg_update_wait();
 }
 
@@ -2247,22 +1685,9 @@ void hal_cmu_usb_set_host_mode(void)
 }
 
 #ifdef ROM_BUILD
-enum HAL_CMU_USB_CLOCK_SEL_T hal_cmu_usb_rom_select_clock_source(int pll_en, unsigned int crystal)
-{
-    enum HAL_CMU_USB_CLOCK_SEL_T sel;
-
-    if (crystal == 24000000) {
-        sel = HAL_CMU_USB_CLOCK_SEL_24M_X2;
-    } else {
-        sel = HAL_CMU_USB_CLOCK_SEL_PLL;
-    }
-
-    hal_cmu_usb_rom_set_clock_source(sel);
-
-    return sel;
-}
 void hal_cmu_usb_rom_set_clock_source(enum HAL_CMU_USB_CLOCK_SEL_T sel)
 {
+    usb_clk_sel = sel;
 }
 #endif
 
@@ -2270,17 +1695,53 @@ static uint32_t hal_cmu_usb_get_clock_source(void)
 {
     uint32_t src;
 
+#if defined(USB_CLK_SRC_26M_X4) || defined(USB_CLK_SRC_26M_X2) || defined(USB_CLK_SRC_24M_X2) || defined(USB_CLK_SRC_48M)
 #ifdef USB_HIGH_SPEED
+#error "USB HIGH-SPEED must use PLL"
+#endif
+#if defined(USB_CLK_SRC_26M_X4) && !defined(ANA_26M_X4_ENABLE)
+#error "USB_CLK_SRC_26M_X4 must use ANA_26M_X4_ENABLE"
+#endif
+#endif
+
+#ifdef ROM_BUILD
+
+#ifdef USB_USE_USBPLL
     src = CMU_USB_CLK_SRC_PLL_60M;
 #else
-#ifndef USB_USE_USBPLL
-    if (hal_cmu_get_crystal_freq() == 24000000)
+    if (usb_clk_sel == HAL_CMU_USB_CLOCK_SEL_24M_X2) {
         src = CMU_USB_CLK_SRC_OSC_24M_X2;
-    else
-#endif
+    } else if (usb_clk_sel == HAL_CMU_USB_CLOCK_SEL_48M) {
+        src = CMU_USB_CLK_SRC_OSC_48M;
+    } else if (usb_clk_sel == HAL_CMU_USB_CLOCK_SEL_26M_X2) {
+        src = CMU_USB_CLK_SRC_OSC_26M_X2;
+    } else if (usb_clk_sel == HAL_CMU_USB_CLOCK_SEL_26M_X4) {
+        src = CMU_USB_CLK_SRC_OSC_26M_X4;
+    } else {
         src = CMU_USB_CLK_SRC_PLL_48M;
+    }
+#endif
+
+#else // !ROM_BUILD
+
+#ifdef USB_USE_USBPLL
+    src = CMU_USB_CLK_SRC_PLL_60M;
+#else
+#ifdef USB_CLK_SRC_24M_X2
+    src = CMU_USB_CLK_SRC_OSC_24M_X2;
+#elif defined(USB_CLK_SRC_48M)
+    src = CMU_USB_CLK_SRC_OSC_48M;
+#elif defined(USB_CLK_SRC_26M_X4)
+    src = CMU_USB_CLK_SRC_OSC_26M_X4;
+#elif defined(USB_CLK_SRC_26M_X2)
+    src = CMU_USB_CLK_SRC_OSC_26M_X2;
+#else
+    src = CMU_USB_CLK_SRC_PLL_48M;
+#endif
 #endif
 
+#endif // !ROM_BUILD
+
     return src;
 }
 
@@ -2289,38 +1750,20 @@ void hal_cmu_usb_clock_enable(void)
     enum HAL_CMU_PLL_T pll;
     uint32_t lock;
     uint32_t src;
-    POSSIBLY_UNUSED uint32_t div;
 
-#if !defined(USB_HIGH_SPEED) && defined(USB_USE_USBPLL)
     pll = HAL_CMU_PLL_USB;
-#else
-    pll = HAL_CMU_PLL_BB;
-#endif
     src = hal_cmu_usb_get_clock_source();
-    if (src != CMU_USB_CLK_SRC_OSC_24M_X2)
+
+    if (src == CMU_USB_CLK_SRC_PLL_60M || src == CMU_USB_CLK_SRC_PLL_60M_ALT ||
+            src == CMU_USB_CLK_SRC_PLL_48M) {
         hal_cmu_pll_enable(pll, HAL_CMU_PLL_USER_USB);
+    }
 
     lock = int_lock();
-#ifdef USB_HIGH_SPEED
-    cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, 1);
-#else
-    cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, 0);
-    if (src == CMU_USB_CLK_SRC_OSC_24M_X2) {
-        aoncmu->CLK_SELECT |= AON_CMU_SEL_USB_OSCX2;
-    } else {
-#ifdef USB_USE_USBPLL
-        aoncmu->CLK_SELECT |= AON_CMU_SEL_USB_PLLUSB;
-        // DSI PSRAMPLL to dig: ?
-        div = 8;///TODO:
-#else // USB usb BBPLL
-        aoncmu->CLK_SELECT &= ~AON_CMU_SEL_USB_PLLUSB;
-        // BBPLL to dig: 384M
-        div = 8;
-#endif
-        aoncmu->CLK_SELECT = SET_BITFIELD(aoncmu->CLK_SELECT, AON_CMU_CFG_DIV_USB, div-2);
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_USB_PLL_ENABLE;
-    }
-#endif /*USB_HIGH_SPEED*/
+#ifdef USB_CLK_SRC_26M_X4
+    aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_USB;
+#endif
+    cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_SEL_USB_SRC, src);
     int_unlock(lock);
     hal_cmu_clock_enable(HAL_CMU_MOD_H_USBC);
 #ifdef USB_HIGH_SPEED
@@ -2346,12 +1789,10 @@ void hal_cmu_usb_clock_enable(void)
 void hal_cmu_usb_clock_disable(void)
 {
     enum HAL_CMU_PLL_T pll;
+    uint32_t src;
 
-#if !defined(USB_HIGH_SPEED) && defined(USB_USE_USBPLL)
     pll = HAL_CMU_PLL_USB;
-#else
-    pll = HAL_CMU_PLL_BB;
-#endif
+    src = hal_cmu_usb_get_clock_source();
 
     hal_cmu_reset_set(HAL_CMU_MOD_O_USB);
     hal_cmu_reset_set(HAL_CMU_MOD_O_USB32K);
@@ -2365,18 +1806,17 @@ void hal_cmu_usb_clock_disable(void)
     hal_cmu_clock_disable(HAL_CMU_MOD_H_USBH);
 #endif
     hal_cmu_clock_disable(HAL_CMU_MOD_H_USBC);
-#ifndef USB_HIGH_SPEED
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_USB_PLL_DISABLE;
-#endif
 
-    if (hal_cmu_usb_get_clock_source() != CMU_USB_CLK_SRC_OSC_24M_X2)
+    if (src == CMU_USB_CLK_SRC_PLL_60M || src == CMU_USB_CLK_SRC_PLL_60M_ALT ||
+            src == CMU_USB_CLK_SRC_PLL_48M) {
         hal_cmu_pll_disable(pll, HAL_CMU_PLL_USER_USB);
+    }
 }
 #endif
 
 void BOOT_TEXT_FLASH_LOC hal_cmu_apb_init_div(void)
 {
-    // Divider defaults to 2 (div = reg_val + 2)
+    // Divider defaults to 2 (reg_val = div - 2)
     //cmu->SYS_DIV = SET_BITFIELD(cmu->SYS_DIV, CMU_CFG_DIV_PCLK, 0);
 }
 
@@ -2386,7 +1826,10 @@ int hal_cmu_periph_set_div(uint32_t div)
     int ret = 0;
 
     if (div == 0 || div > ((AON_CMU_CFG_DIV_PER_MASK >> AON_CMU_CFG_DIV_PER_SHIFT) + 2)) {
-        ret = 1;
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_PLL_PER_DISABLE;
+        if (div > ((AON_CMU_CFG_DIV_PER_MASK >> AON_CMU_CFG_DIV_PER_SHIFT) + 2)) {
+            ret = 1;
+        }
     } else {
         lock = int_lock();
         if (div == 1) {
@@ -2397,6 +1840,7 @@ int hal_cmu_periph_set_div(uint32_t div)
                 AON_CMU_CFG_DIV_PER(div);
         }
         int_unlock(lock);
+        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_PLL_PER_ENABLE;
     }
 
     return ret;
@@ -2424,9 +1868,8 @@ int hal_cmu_ ##f## _set_div(uint32_t div) \
 PERPH_SET_DIV_FUNC(uart0, UART0, UART_CLK);
 PERPH_SET_DIV_FUNC(uart1, UART1, UART_CLK);
 PERPH_SET_DIV_FUNC(uart2, UART2, UART_CLK);
-PERPH_SET_DIV_FUNC(uart3, UART3, UART_CLK);
-PERPH_SET_DIV_FUNC(spi, SPI0, SYS_DIV);
-PERPH_SET_DIV_FUNC(slcd, SPI1, SYS_DIV);
+PERPH_SET_DIV_FUNC(spi, SPI1, SYS_DIV);
+PERPH_SET_DIV_FUNC(slcd, SPI0, SYS_DIV);
 PERPH_SET_DIV_FUNC(sdmmc, SDMMC, PERIPH_CLK);
 PERPH_SET_DIV_FUNC(i2c, I2C, I2C_CLK);
 
@@ -2450,9 +1893,8 @@ int hal_cmu_ ##f## _set_freq(enum HAL_CMU_PERIPH_FREQ_T freq) \
 PERPH_SET_FREQ_FUNC(uart0, UART0, UART_CLK);
 PERPH_SET_FREQ_FUNC(uart1, UART1, UART_CLK);
 PERPH_SET_FREQ_FUNC(uart2, UART2, UART_CLK);
-PERPH_SET_FREQ_FUNC(uart3, UART3, UART_CLK);
-PERPH_SET_FREQ_FUNC(spi, SPI0, SYS_DIV);
-PERPH_SET_FREQ_FUNC(slcd, SPI1, SYS_DIV);
+PERPH_SET_FREQ_FUNC(spi, SPI1, SYS_DIV);
+PERPH_SET_FREQ_FUNC(slcd, SPI0, SYS_DIV);
 PERPH_SET_FREQ_FUNC(sdmmc, SDMMC, PERIPH_CLK);
 PERPH_SET_FREQ_FUNC(i2c, I2C, I2C_CLK);
 
@@ -2474,22 +1916,6 @@ int hal_cmu_ispi_set_freq(enum HAL_CMU_PERIPH_FREQ_T freq)
     return ret;
 }
 
-void hal_cmu_sec_eng_clock_enable(void)
-{
-    hal_cmu_clock_enable(HAL_CMU_MOD_H_SEC_ENG);
-    hal_cmu_clock_enable(HAL_CMU_MOD_P_SEC_ENG);
-    hal_cmu_reset_clear(HAL_CMU_MOD_H_SEC_ENG);
-    hal_cmu_reset_clear(HAL_CMU_MOD_P_SEC_ENG);
-}
-
-void hal_cmu_sec_eng_clock_disable(void)
-{
-    hal_cmu_reset_set(HAL_CMU_MOD_H_SEC_ENG);
-    hal_cmu_reset_set(HAL_CMU_MOD_P_SEC_ENG);
-    hal_cmu_clock_disable(HAL_CMU_MOD_H_SEC_ENG);
-    hal_cmu_clock_disable(HAL_CMU_MOD_P_SEC_ENG);
-}
-
 int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)
 {
     uint32_t lock;
@@ -2501,7 +1927,6 @@ int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)
         CMU_CLK_OUT_SEL_CODEC   = 1,
         CMU_CLK_OUT_SEL_BT      = 2,
         CMU_CLK_OUT_SEL_MCU     = 3,
-        CMU_CLK_OUT_SEL_WF      = 4,
 
         CMU_CLK_OUT_SEL_QTY
     };
@@ -2512,7 +1937,7 @@ int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)
     if (id <= HAL_CMU_CLOCK_OUT_AON_SYS) {
         sel = CMU_CLK_OUT_SEL_AON;
         cfg = id - HAL_CMU_CLOCK_OUT_AON_32K;
-    } else if (HAL_CMU_CLOCK_OUT_MCU_32K <= id && id <= HAL_CMU_CLOCK_OUT_MCU_I2S1) {
+    } else if (HAL_CMU_CLOCK_OUT_MCU_32K <= id && id <= HAL_CMU_CLOCK_OUT_MCU_SPI1) {
         sel = CMU_CLK_OUT_SEL_MCU;
         lock = int_lock();
         cmu->PERIPH_CLK = SET_BITFIELD(cmu->PERIPH_CLK, CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_MCU_32K);
@@ -2520,12 +1945,9 @@ int hal_cmu_clock_out_enable(enum HAL_CMU_CLOCK_OUT_ID_T id)
     } else if (HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA <= id && id <= HAL_CMU_CLOCK_OUT_CODEC_HCLK) {
         sel = CMU_CLK_OUT_SEL_CODEC;
         hal_codec_select_clock_out(id - HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA);
-    } else if (HAL_CMU_CLOCK_OUT_BT_NONE <= id && id <= HAL_CMU_CLOCK_OUT_BT_DACD8) {
+    } else if (HAL_CMU_CLOCK_OUT_BT_32K <= id && id <= HAL_CMU_CLOCK_OUT_BT_26M) {
         sel = CMU_CLK_OUT_SEL_BT;
-        btcmu->CLK_OUT = SET_BITFIELD(btcmu->CLK_OUT, BT_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_BT_NONE);
-    } else if (HAL_CMU_CLOCK_OUT_WF_32K <= id && id <= HAL_CMU_CLOCK_OUT_WF_BBDIGFIFO) {
-        sel = CMU_CLK_OUT_SEL_WF;
-        wlancmu->CLK_OUT = SET_BITFIELD(wlancmu->CLK_OUT, WLAN_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_WF_32K);
+        btcmu->CLK_OUT = SET_BITFIELD(btcmu->CLK_OUT, BT_CMU_CFG_CLK_OUT, id - HAL_CMU_CLOCK_OUT_BT_32K);
     }
 
     if (sel < CMU_CLK_OUT_SEL_QTY) {
@@ -2554,7 +1976,7 @@ int hal_cmu_i2s_mclk_enable(enum HAL_CMU_I2S_MCLK_ID_T id)
     uint32_t lock;
 
     lock = int_lock();
-    aoncmu->CODEC_DIV = SET_BITFIELD(aoncmu->CODEC_DIV, AON_CMU_SEL_I2S_MCLK, id) | AON_CMU_EN_I2S_MCLK;
+    aoncmu->PCM_I2S_CLK = SET_BITFIELD(aoncmu->PCM_I2S_CLK, AON_CMU_SEL_I2S_MCLK, id) | AON_CMU_EN_I2S_MCLK;
     int_unlock(lock);
 
     return 0;
@@ -2565,7 +1987,7 @@ void hal_cmu_i2s_mclk_disable(void)
     uint32_t lock;
 
     lock = int_lock();
-    aoncmu->CODEC_DIV &= ~AON_CMU_EN_I2S_MCLK;
+    aoncmu->PCM_I2S_CLK &= ~AON_CMU_EN_I2S_MCLK;
     int_unlock(lock);
 }
 
@@ -2586,42 +2008,28 @@ int hal_cmu_pwm_set_freq(enum HAL_PWM_ID_T id, uint32_t freq)
         clk_32k = 0;
         div = hal_cmu_get_crystal_freq() / freq;
         if (div < 2) {
-            return -1;
+            return 1;
         }
 
         div -= 2;
         if ((div & (AON_CMU_CFG_DIV_PWM0_MASK >> AON_CMU_CFG_DIV_PWM0_SHIFT)) != div) {
-            return -2;
+            return 1;
         }
     }
 
     lock = int_lock();
     if (id == HAL_PWM_ID_0) {
-        aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM0_MASK | AON_CMU_SEL_PWM0_OSC | AON_CMU_EN_CLK_PWM0_OSC)) |
-            AON_CMU_CFG_DIV_PWM0(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM0_OSC | AON_CMU_EN_CLK_PWM0_OSC));
+        aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM0_MASK | AON_CMU_SEL_OSC_PWM0 | AON_CMU_EN_OSC_PWM0)) |
+            AON_CMU_CFG_DIV_PWM0(div) | (clk_32k ? 0 : (AON_CMU_SEL_OSC_PWM0 | AON_CMU_EN_OSC_PWM0));
     } else if (id == HAL_PWM_ID_1) {
-        aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM1_MASK | AON_CMU_SEL_PWM1_OSC | AON_CMU_EN_CLK_PWM1_OSC)) |
-            AON_CMU_CFG_DIV_PWM1(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM1_OSC | AON_CMU_EN_CLK_PWM1_OSC));
+        aoncmu->PWM01_CLK = (aoncmu->PWM01_CLK & ~(AON_CMU_CFG_DIV_PWM1_MASK | AON_CMU_SEL_OSC_PWM1 | AON_CMU_EN_OSC_PWM1)) |
+            AON_CMU_CFG_DIV_PWM1(div) | (clk_32k ? 0 : (AON_CMU_SEL_OSC_PWM1 | AON_CMU_EN_OSC_PWM1));
     } else if (id == HAL_PWM_ID_2) {
-        aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM2_MASK | AON_CMU_SEL_PWM2_OSC | AON_CMU_EN_CLK_PWM2_OSC)) |
-            AON_CMU_CFG_DIV_PWM2(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM2_OSC | AON_CMU_EN_CLK_PWM2_OSC));
-    } else if (id == HAL_PWM_ID_3) {
-        aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM3_MASK | AON_CMU_SEL_PWM3_OSC | AON_CMU_EN_CLK_PWM3_OSC)) |
-            AON_CMU_CFG_DIV_PWM3(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM3_OSC | AON_CMU_EN_CLK_PWM3_OSC));
-    } else if (id == HAL_PWM1_ID_0) {
-        aoncmu->PWM45_CLK = (aoncmu->PWM45_CLK & ~(AON_CMU_CFG_DIV_PWM4_MASK | AON_CMU_SEL_PWM4_OSC | AON_CMU_EN_CLK_PWM4_OSC)) |
-            AON_CMU_CFG_DIV_PWM4(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM4_OSC | AON_CMU_EN_CLK_PWM4_OSC));
-    } else if (id == HAL_PWM1_ID_1) {
-        aoncmu->PWM45_CLK = (aoncmu->PWM45_CLK & ~(AON_CMU_CFG_DIV_PWM5_MASK | AON_CMU_SEL_PWM5_OSC | AON_CMU_EN_CLK_PWM5_OSC)) |
-            AON_CMU_CFG_DIV_PWM5(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM5_OSC | AON_CMU_EN_CLK_PWM5_OSC));
-    } else if (id == HAL_PWM1_ID_2) {
-        aoncmu->PWM67_CLK = (aoncmu->PWM67_CLK & ~(AON_CMU_CFG_DIV_PWM6_MASK | AON_CMU_SEL_PWM6_OSC | AON_CMU_EN_CLK_PWM6_OSC)) |
-            AON_CMU_CFG_DIV_PWM6(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM6_OSC | AON_CMU_EN_CLK_PWM6_OSC));
-    } else if (id == HAL_PWM1_ID_3) {
-        aoncmu->PWM67_CLK = (aoncmu->PWM67_CLK & ~(AON_CMU_CFG_DIV_PWM7_MASK | AON_CMU_SEL_PWM7_OSC | AON_CMU_EN_CLK_PWM7_OSC)) |
-            AON_CMU_CFG_DIV_PWM7(div) | (clk_32k ? 0 : (AON_CMU_SEL_PWM7_OSC | AON_CMU_EN_CLK_PWM7_OSC));
+        aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM2_MASK | AON_CMU_SEL_OSC_PWM2 | AON_CMU_EN_OSC_PWM2)) |
+            AON_CMU_CFG_DIV_PWM2(div) | (clk_32k ? 0 : (AON_CMU_SEL_OSC_PWM2 | AON_CMU_EN_OSC_PWM2));
     } else {
-        ASSERT(0,"PWM id error!");
+        aoncmu->PWM23_CLK = (aoncmu->PWM23_CLK & ~(AON_CMU_CFG_DIV_PWM3_MASK | AON_CMU_SEL_OSC_PWM3 | AON_CMU_EN_OSC_PWM3)) |
+            AON_CMU_CFG_DIV_PWM3(div) | (clk_32k ? 0 : (AON_CMU_SEL_OSC_PWM3 | AON_CMU_EN_OSC_PWM3));
     }
     int_unlock(lock);
     return 0;
@@ -2655,26 +2063,14 @@ void hal_cmu_jtag_clock_disable(void)
     aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_JTAG_DISABLE;
 }
 
-void hal_cmu_jtag_set_cp(void)
-{
-    cmu->PERIPH_CLK |= CMU_JTAG_SEL_CP;
-}
-
-void hal_cmu_jtag_set_a7(void)
-{
-    cmu->PERIPH_CLK |= CMU_JTAG_SEL_A7;
-}
-
 void hal_cmu_rom_clock_init(void)
 {
-    aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_AON_OSCX2) | AON_CMU_SEL_AON_OSC;
+    aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_CLK_OSCX2) |
+        AON_CMU_BYPASS_LOCK_PLLBB | AON_CMU_BYPASS_LOCK_PLLAUD | AON_CMU_SEL_CLK_OSC;
     // Enable PMU fast clock
-    //aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~AON_CMU_SEL_DCDC_PLL) | AON_CMU_SEL_DCDC_OSC | AON_CMU_BYPASS_DIV_DCDC | AON_CMU_EN_CLK_DCDC0;
-
-    hal_cmu_dma_req_init();
-
-    // Debug Select CMU REG F4
-    cmu->MCU_TIMER = SET_BITFIELD(cmu->MCU_TIMER, CMU_DEBUG_REG_SEL, CMU_DEBUG_REG_SEL_DEBUG);
+    aoncmu->CLK_OUT &= ~(AON_CMU_SEL_DCDC_PLL | AON_CMU_SEL_DCDC_OSCX2);
+    aoncmu->CLK_OUT |= AON_CMU_BYPASS_DIV_DCDC;
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_DCDC0_ENABLE;
 }
 
 void hal_cmu_init_chip_feature(uint16_t feature)
@@ -2686,238 +2082,155 @@ void BOOT_TEXT_FLASH_LOC hal_cmu_osc_x2_enable(void)
 {
     // Debug Select CMU REG F4
     cmu->MCU_TIMER = SET_BITFIELD(cmu->MCU_TIMER, CMU_DEBUG_REG_SEL, CMU_DEBUG_REG_SEL_DEBUG);
-    // Power on OSCX2
-    aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX2_ENABLE;
-    // Disable DIG OSCX2
-    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_OSCX2_DIG;
-    // Enable OSCX2
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX2_ENABLE | AON_CMU_EN_CLK_MCU_OSCX2_ENABLE;
+    // Enable OSCX2 for MCU peripheral
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_OSCX2_MCU_ENABLE;
 }
 
 void BOOT_TEXT_FLASH_LOC hal_cmu_osc_x4_enable(void)
 {
 #ifdef ANA_26M_X4_ENABLE
-    // Power on OSCX4
-    aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX4_ENABLE;
-    // Disable DIG OSCX4
-    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_OSCX4_DIG;
-    // Enable OSCX4
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX4_ENABLE;
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_X4_ANA_ENABLE;
+#endif
+#ifdef OSC_26M_X4_AUD2BB
+    aoncmu->CLK_SELECT |= AON_CMU_SEL_X4_SYS;
+    aoncmu->CLK_SELECT &= ~AON_CMU_SEL_X4_DIG;
 #endif
 }
 
-struct CMU_DMA_PER_2_REQ_T {
-    enum HAL_DMA_PERIPH_T periph;
-    enum CMU_DMA_REQ_T req;
-};
-const static BOOT_RODATA_FLASH_LOC struct CMU_DMA_PER_2_REQ_T periph_map[] = {
-    {HAL_DMA_PERIPH_NULL,   CMU_DMA_REQ_NULL},
-    {HAL_AUDMA_CODEC_RX,    CMU_DMA_REQ_CODEC_RX},
-    {HAL_AUDMA_CODEC_TX,    CMU_DMA_REQ_CODEC_TX},
-    {HAL_AUDMA_DSD_RX,      CMU_DMA_REQ_DSD_RX},
-    {HAL_AUDMA_DSD_TX,      CMU_DMA_REQ_DSD_TX},
-    {HAL_GPDMA_IR_RX,       CMU_DMA_REQ_IR_RX},
-    {HAL_GPDMA_IR_TX,       CMU_DMA_REQ_IR_TX},
-    {HAL_GPDMA_FLASH1,      CMU_DMA_REQ_FLS1},
-    {HAL_GPDMA_FLASH0,      CMU_DMA_REQ_FLS0},
-    {HAL_AUDMA_BTDUMP,      CMU_DMA_REQ_BTDUMP},
-    {HAL_GPDMA_SDMMC,       CMU_DMA_REQ_SDEMMC},
-    {HAL_GPDMA_I2C0_RX,     CMU_DMA_REQ_I2C0_RX},
-    {HAL_GPDMA_I2C0_TX,     CMU_DMA_REQ_I2C0_TX},
-    {HAL_GPDMA_I2C1_RX,     CMU_DMA_REQ_I2C1_RX},
-    {HAL_GPDMA_I2C1_TX,     CMU_DMA_REQ_I2C1_TX},
-    {HAL_GPDMA_I2C2_RX,     CMU_DMA_REQ_I2C2_RX},
-    {HAL_GPDMA_I2C2_TX,     CMU_DMA_REQ_I2C2_TX},
-    {HAL_GPDMA_SPI_RX,      CMU_DMA_REQ_SPILCD0_RX},
-    {HAL_GPDMA_SPI_TX,      CMU_DMA_REQ_SPILCD0_TX},
-    {HAL_GPDMA_SPILCD_RX,   CMU_DMA_REQ_SPILCD1_RX},
-    {HAL_GPDMA_SPILCD_TX,   CMU_DMA_REQ_SPILCD1_TX},
-    {HAL_GPDMA_ISPI_RX,     CMU_DMA_REQ_SPI_ITN_RX},
-    {HAL_GPDMA_ISPI_TX,     CMU_DMA_REQ_SPI_ITN_TX},
-    {HAL_GPDMA_UART0_RX,    CMU_DMA_REQ_UART0_RX},
-    {HAL_GPDMA_UART0_TX,    CMU_DMA_REQ_UART0_TX},
-    {HAL_GPDMA_UART1_RX,    CMU_DMA_REQ_UART1_RX},
-    {HAL_GPDMA_UART1_TX,    CMU_DMA_REQ_UART1_TX},
-    {HAL_GPDMA_UART2_RX,    CMU_DMA_REQ_UART2_RX},
-    {HAL_GPDMA_UART2_TX,    CMU_DMA_REQ_UART2_TX},
-    {HAL_GPDMA_UART3_RX,    CMU_DMA_REQ_UART3_RX},
-    {HAL_GPDMA_UART3_TX,    CMU_DMA_REQ_UART3_TX},
-    {HAL_AUDMA_BTPCM_RX,    CMU_DMA_REQ_PCM_RX},
-    {HAL_AUDMA_BTPCM_TX,    CMU_DMA_REQ_PCM_TX},
-    {HAL_AUDMA_I2S0_RX,     CMU_DMA_REQ_I2S0_RX},
-    {HAL_AUDMA_I2S0_TX,     CMU_DMA_REQ_I2S0_TX},
-    {HAL_AUDMA_I2S1_RX,     CMU_DMA_REQ_I2S1_RX},
-    {HAL_AUDMA_I2S1_TX,     CMU_DMA_REQ_I2S1_TX},
-    {HAL_AUDMA_SPDIF0_RX,   CMU_DMA_REQ_SPDIF0_RX},
-    {HAL_AUDMA_SPDIF0_TX,   CMU_DMA_REQ_SPDIF0_TX},
-};
-
-enum CMU_DMA_REQ_T BOOT_TEXT_FLASH_LOC hal_dma_periph_2_idx(enum HAL_DMA_PERIPH_T periph)
+void BOOT_TEXT_FLASH_LOC hal_cmu_module_init_state(void)
 {
-    uint32_t i;
-    for (i=0; i<ARRAY_SIZE(periph_map); ++i)
-        if (periph_map[i].periph == periph)
-            return periph_map[i].req;
-    return CMU_DMA_REQ_NULL;
-}
+    aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_CLK_OSCX2) |
+        AON_CMU_BYPASS_LOCK_PLLBB | AON_CMU_BYPASS_LOCK_PLLAUD | AON_CMU_SEL_CLK_OSC;
+    // Slow down PMU fast clock
+    aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~(AON_CMU_BYPASS_DIV_DCDC | AON_CMU_CFG_DIV_DCDC_MASK)) | AON_CMU_CFG_DIV_DCDC(2);
 
-void BOOT_TEXT_FLASH_LOC hal_cmu_dma_req_init(void)
-{
     // DMA channel config
     cmu->ADMA_CH0_4_REQ =
-        CMU_ADMA_CH0_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[0])) |
-        CMU_ADMA_CH1_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[1])) |
-        CMU_ADMA_CH2_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[2])) |
-        CMU_ADMA_CH3_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[3])) |
-        CMU_ADMA_CH4_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[4]));
+        // codec
+        CMU_ADMA_CH0_REQ_IDX(0) | CMU_ADMA_CH1_REQ_IDX(1) |
+#ifdef CODEC_DSD
+        // codec_dsd
+        CMU_ADMA_CH2_REQ_IDX(16) | CMU_ADMA_CH3_REQ_IDX(17) |
+#else
+        // btpcm
+        CMU_ADMA_CH2_REQ_IDX(2) | CMU_ADMA_CH3_REQ_IDX(3) |
+#endif
+        // i2s0
+        CMU_ADMA_CH4_REQ_IDX(4);
     cmu->ADMA_CH5_9_REQ =
-        CMU_ADMA_CH5_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[5])) |
-        CMU_ADMA_CH6_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[6])) |
-        CMU_ADMA_CH7_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[7])) |
-        CMU_ADMA_CH8_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[8])) |
-        CMU_ADMA_CH9_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[9]));
+        // i2s0
+        CMU_ADMA_CH5_REQ_IDX(5) |
+        // fir
+        CMU_ADMA_CH6_REQ_IDX(6) | CMU_ADMA_CH7_REQ_IDX(7) |
+        // spdif
+        CMU_ADMA_CH8_REQ_IDX(8) | CMU_ADMA_CH9_REQ_IDX(9);
     cmu->ADMA_CH10_14_REQ =
-        CMU_ADMA_CH10_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[10])) |
-        CMU_ADMA_CH11_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[11])) |
-        CMU_ADMA_CH12_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[12])) |
-        CMU_ADMA_CH13_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[13])) |
-        CMU_ADMA_CH14_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[14]));
+        // iir
+        CMU_ADMA_CH10_REQ_IDX(10) | CMU_ADMA_CH11_REQ_IDX(11) |
+        // btdump
+        CMU_ADMA_CH12_REQ_IDX(12) |
+        // mc
+        CMU_ADMA_CH13_REQ_IDX(13) |
+        // i2s1
+        CMU_ADMA_CH14_REQ_IDX(18);
     cmu->ADMA_CH15_REQ =
-        CMU_ADMA_CH15_REQ_IDX(hal_dma_periph_2_idx(bes2003_audma_fifo_periph[15]));
-
+        // i2s1
+        CMU_ADMA_CH15_REQ_IDX(19);
     cmu->GDMA_CH0_4_REQ =
-        CMU_GDMA_CH0_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[0])) |
-        CMU_GDMA_CH1_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[1])) |
-        CMU_GDMA_CH2_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[2])) |
-        CMU_GDMA_CH3_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[3])) |
-        CMU_GDMA_CH4_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[4]));
+        // flash
+        CMU_GDMA_CH0_REQ_IDX(20) |
+        // sdmmc
+        CMU_GDMA_CH1_REQ_IDX(21) |
+        // i2c0
+        CMU_GDMA_CH2_REQ_IDX(22) | CMU_GDMA_CH3_REQ_IDX(23) |
+        // spi
+        CMU_GDMA_CH4_REQ_IDX(24);
     cmu->GDMA_CH5_9_REQ =
-        CMU_GDMA_CH5_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[5])) |
-        CMU_GDMA_CH6_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[6])) |
-        CMU_GDMA_CH7_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[7])) |
-        CMU_GDMA_CH8_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[8])) |
-        CMU_GDMA_CH9_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[9]));
+        // spi
+        CMU_GDMA_CH5_REQ_IDX(25) |
+        // spilcd
+        CMU_GDMA_CH6_REQ_IDX(26) | CMU_GDMA_CH7_REQ_IDX(27) |
+        // uart0
+        CMU_GDMA_CH8_REQ_IDX(28) | CMU_GDMA_CH9_REQ_IDX(29);
     cmu->GDMA_CH10_14_REQ =
-        CMU_GDMA_CH10_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[10])) |
-        CMU_GDMA_CH11_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[11])) |
-        CMU_GDMA_CH12_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[12])) |
-        CMU_GDMA_CH13_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[13])) |
-        CMU_GDMA_CH14_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[14]));
+        // uart1
+        CMU_GDMA_CH10_REQ_IDX(30) | CMU_GDMA_CH11_REQ_IDX(31) |
+        // i2c1
+        CMU_GDMA_CH12_REQ_IDX(32) | CMU_GDMA_CH13_REQ_IDX(33) |
+        // uart2
+        CMU_GDMA_CH14_REQ_IDX(34);
     cmu->GDMA_CH15_REQ =
-        CMU_GDMA_CH15_REQ_IDX(hal_dma_periph_2_idx(bes2003_gpdma_fifo_periph[15]));
-}
-
-void BOOT_TEXT_FLASH_LOC hal_cmu_module_init_state(void)
-{
-    aoncmu->CLK_OUT = AON_CMU_EN_CLK_DCDC0 | AON_CMU_CFG_DIV_DCDC(1);
-    aoncmu->CODEC_DIV = (aoncmu->CODEC_DIV & ~AON_CMU_SEL_AON_OSCX2) | AON_CMU_SEL_AON_OSC;
-    // Slow down PMU fast clock
-    //aoncmu->CLK_OUT = (aoncmu->CLK_OUT & ~(AON_CMU_BYPASS_DIV_DCDC | AON_CMU_CFG_DIV_DCDC_MASK)) | AON_CMU_CFG_DIV_DCDC(2);
-
-    hal_cmu_sram_init();
-
-    hal_cmu_dma_req_init();
+        // uart2
+        CMU_GDMA_CH15_REQ_IDX(35);
 
 #ifndef SIMU
-    cmu->ORESET_SET = SYS_ORST_USB | SYS_ORST_USB32K | SYS_ORST_PSRAM1G | SYS_ORST_PSRAM200 | SYS_ORST_SDMMC |
-        SYS_ORST_WDT | SYS_ORST_TIMER2 | SYS_ORST_I2C0 | SYS_ORST_I2C1 | SYS_ORST_I2C2 | SYS_ORST_SPI | SYS_ORST_SLCD | SYS_ORST_SPI_PHY |
-#ifndef ARM_CMNS
-        SYS_ORST_UART0 |
-#endif
-        SYS_ORST_UART1 | SYS_ORST_UART2 | SYS_ORST_UART3 | SYS_ORST_PCM | SYS_ORST_I2S0 | SYS_ORST_I2S1 |
-        SYS_ORST_SPDIF0 | SYS_ORST_A7 | SYS_ORST_TSF | SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP | SYS_ORST_FLASH1;
-    cmu->PRESET_SET = SYS_PRST_WDT | SYS_PRST_TIMER2 | SYS_PRST_I2C0 | SYS_PRST_I2C1 | SYS_PRST_I2C2 | SYS_PRST_IR |
+    cmu->ORESET_SET = SYS_ORST_USB | SYS_ORST_SDMMC | SYS_ORST_WDT | SYS_ORST_TIMER2 |
+        SYS_ORST_I2C0 | SYS_ORST_I2C1 | SYS_ORST_SPI | SYS_ORST_SLCD | SYS_ORST_SPI_PHY |
+        SYS_ORST_UART0 | SYS_ORST_UART1 | SYS_ORST_UART2 | SYS_ORST_I2S0 | SYS_ORST_SPDIF0 | SYS_ORST_PCM |
+        SYS_ORST_USB32K | SYS_ORST_I2S1;
+    cmu->PRESET_SET = SYS_PRST_WDT | SYS_PRST_TIMER2 | SYS_PRST_I2C0 | SYS_PRST_I2C1 |
         SYS_PRST_SPI | SYS_PRST_SLCD | SYS_PRST_SPI_PHY |
-#ifndef ARM_CMNS
-        SYS_PRST_UART0 |
-#endif
-        SYS_PRST_UART1 | SYS_PRST_UART2 | SYS_PRST_UART3 |
-        SYS_PRST_PCM | SYS_PRST_I2S0 | SYS_PRST_I2S1 | SYS_PRST_SPDIF0 | SYS_PRST_TQWF | SYS_PRST_TQA7;
-    cmu->HRESET_SET = SYS_HRST_CORE1 | SYS_HRST_BCM | SYS_HRST_USBC | SYS_HRST_USBH | SYS_HRST_CODEC |
-        SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G | SYS_HRST_PSRAM200 | SYS_HRST_BT_DUMP | SYS_HRST_WF_DUMP | SYS_HRST_SDMMC |
-        SYS_HRST_CHECKSUM | SYS_HRST_CRC | SYS_HRST_FLASH1;
-    cmu->XRESET_SET = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PSRAM1G | SYS_XRST_PER |
-        SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
-        SYS_XRST_DISPLAYX | SYS_XRST_DISPLAYH | SYS_XRST_CSI | SYS_XRST_DSI | SYS_XRST_PSRAM1GMX | SYS_XRST_GPV_MAIN | SYS_XRST_GPV_PSRAM1G;
-    cmu->APRESET_SET = SYS_APRST_BOOTREG | SYS_APRST_WDT| SYS_APRST_TIMER0 | SYS_APRST_TIMER1 | SYS_APRST_TQ | SYS_APRST_DAP |
-        SYS_APRST_DISPLAY | SYS_APRST_CSI;
-    cmu->QRESET_SET = SYS_QRST_DSI_32K | SYS_QRST_DSI_PN | SYS_QRST_DSI_TV | SYS_QRST_DSI_PIX |
-        SYS_QRST_DSI_DSI | SYS_QRST_CSI_LANE | SYS_QRST_CSI_PIX | SYS_QRST_CSI_LANG | SYS_QRST_IR;
-
-    cmu->OCLK_DISABLE = SYS_OCLK_USB | SYS_OCLK_USB32K | SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_SDMMC |
-        SYS_OCLK_WDT | SYS_OCLK_TIMER2 | SYS_OCLK_I2C0 | SYS_OCLK_I2C1 | SYS_OCLK_I2C2 | SYS_OCLK_SPI | SYS_OCLK_SLCD | SYS_OCLK_SPI_PHY |
-#ifndef ARM_CMNS
-        SYS_OCLK_UART0 |
-#endif
-        SYS_OCLK_UART1 | SYS_OCLK_UART2 | SYS_OCLK_UART3 | SYS_OCLK_PCM | SYS_OCLK_I2S0 | SYS_OCLK_I2S1 |
-        SYS_OCLK_SPDIF0 | SYS_OCLK_A7 | SYS_OCLK_TSF | SYS_OCLK_WDT_AP | SYS_OCLK_TIMER0_AP | SYS_OCLK_TIMER1_AP | SYS_OCLK_FLASH1;
-    cmu->PCLK_DISABLE = SYS_PCLK_WDT | SYS_PCLK_TIMER2 | SYS_PCLK_I2C0 | SYS_PCLK_I2C1 | SYS_PCLK_I2C2 | SYS_PCLK_IR |
+        SYS_PRST_UART0 | SYS_PRST_UART1 | SYS_PRST_UART2 |
+        SYS_PRST_PCM | SYS_PRST_I2S0 | SYS_PRST_SPDIF0 | SYS_PRST_I2S1 | SYS_PRST_BCM;
+    cmu->HRESET_SET = SYS_HRST_SDMMC | SYS_HRST_USBC | SYS_HRST_CODEC | SYS_HRST_FFT |
+        SYS_HRST_USBH | SYS_HRST_SENSOR_HUB | SYS_HRST_BT_DUMP | SYS_HRST_CP | SYS_HRST_BCM | SYS_HRST_ICACHE0;
+
+    cmu->OCLK_DISABLE = SYS_OCLK_USB | SYS_OCLK_SDMMC | SYS_OCLK_WDT | SYS_OCLK_TIMER2 |
+        SYS_OCLK_I2C0 | SYS_OCLK_I2C1 | SYS_OCLK_SPI | SYS_OCLK_SLCD | SYS_OCLK_SPI_PHY |
+        SYS_OCLK_UART0 | SYS_OCLK_UART1 | SYS_OCLK_UART2 | SYS_OCLK_I2S0 | SYS_OCLK_SPDIF0 | SYS_OCLK_PCM |
+        SYS_OCLK_USB32K | SYS_OCLK_I2S1;
+    cmu->PCLK_DISABLE = SYS_PCLK_WDT | SYS_PCLK_TIMER2 | SYS_PCLK_I2C0 | SYS_PCLK_I2C1 |
         SYS_PCLK_SPI | SYS_PCLK_SLCD | SYS_PCLK_SPI_PHY |
-#ifndef ARM_CMNS
-        SYS_PCLK_UART0 |
-#endif
-        SYS_PCLK_UART1 | SYS_PCLK_UART2 | SYS_PCLK_UART3 |
-        SYS_PCLK_PCM | SYS_PCLK_I2S0 | SYS_PCLK_I2S1 | SYS_PCLK_SPDIF0 | SYS_PCLK_TQWF | SYS_PCLK_TQA7;
-    cmu->HCLK_DISABLE = SYS_HCLK_CORE1 | SYS_HCLK_BCM | SYS_HCLK_USBC | SYS_HCLK_USBH | SYS_HCLK_CODEC |
-        SYS_HCLK_AX2H_A7 | SYS_HCLK_PSRAM1G | SYS_HCLK_PSRAM200 | SYS_HCLK_BT_DUMP | SYS_HCLK_WF_DUMP | SYS_HCLK_SDMMC |
-        SYS_HCLK_CHECKSUM | SYS_HCLK_CRC | SYS_HCLK_FLASH1;
-    cmu->XCLK_DISABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PSRAM1G | SYS_XCLK_PER |
-        SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
-        SYS_XCLK_DISPLAYX | SYS_XCLK_DISPLAYH | SYS_XCLK_CSI | SYS_XCLK_DSI | SYS_XCLK_PSRAM1GMX | SYS_XCLK_GPV_MAIN | SYS_XCLK_GPV_PSRAM1G;;
-    cmu->APCLK_DISABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP |
-        SYS_APCLK_DISPLAY | SYS_APCLK_CSI;
-    cmu->QCLK_DISABLE = SYS_QCLK_DSI_32K | SYS_QCLK_DSI_PN | SYS_QCLK_DSI_TV | SYS_QCLK_DSI_PIX |
-        SYS_QCLK_DSI_DSI | SYS_QCLK_CSI_LANE | SYS_QCLK_CSI_PIX | SYS_QCLK_CSI_LANG | SYS_QCLK_IR;
-
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_DISABLE | AON_CMU_EN_CLK_CODECIIR_DISABLE | AON_CMU_EN_CLK_CODECRS0_DISABLE |
-        AON_CMU_EN_CLK_CODECRS1_DISABLE | AON_CMU_EN_CLK_CODECHCLK_DISABLE | AON_CMU_EN_CLK_VAD32K_DISABLE |
-        AON_CMU_EN_CLK_BT_DISABLE | AON_CMU_EN_CLK_WF_DISABLE;
-
-    aoncmu->RESET_SET = AON_CMU_ARESETN_SET(AON_ARST_PWM | AON_ARST_PWM1) |
-        AON_CMU_ORESETN_SET(AON_ORST_PWM0 | AON_ORST_PWM1 | AON_ORST_PWM2 | AON_ORST_PWM3 |
-            AON_ORST_PWM4 | AON_ORST_PWM5 | AON_ORST_PWM6 | AON_ORST_PWM7 | AON_ORST_BTAON);
-
-    aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_CODEC_SET |
-        AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET |
-        AON_CMU_SOFT_RSTN_WF_SET | AON_CMU_SOFT_RSTN_WFCPU_SET |
-        AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
+        SYS_PCLK_UART0 | SYS_PCLK_UART1 | SYS_PCLK_UART2 |
+        SYS_PCLK_PCM | SYS_PCLK_I2S0 | SYS_PCLK_SPDIF0 | SYS_PCLK_I2S1 | SYS_PCLK_BCM;
+    cmu->HCLK_DISABLE = SYS_HCLK_SDMMC | SYS_HCLK_USBC | SYS_HCLK_CODEC | SYS_HCLK_FFT |
+        SYS_HCLK_USBH | SYS_HCLK_SENSOR_HUB | SYS_HCLK_BT_DUMP | SYS_HCLK_CP | SYS_HCLK_BCM | SYS_HCLK_ICACHE0;
+
+    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_PLL_CODEC_DISABLE | AON_CMU_EN_CLK_CODEC_HCLK_DISABLE | AON_CMU_EN_CLK_CODEC_DISABLE |
+        AON_CMU_EN_CLK_CODEC_IIR_DISABLE | AON_CMU_EN_CLK_PLL_BT_DISABLE |
+        AON_CMU_EN_CLK_60M_BT_DISABLE | AON_CMU_EN_CLK_OSCX2_BT_DISABLE | AON_CMU_EN_CLK_OSC_BT_DISABLE |
+        AON_CMU_EN_CLK_32K_BT_DISABLE | AON_CMU_EN_CLK_PLL_PER_DISABLE;
+
+    aoncmu->RESET_SET = AON_CMU_ARESETN_SET(AON_ARST_PWM) |
+        AON_CMU_ORESETN_SET(AON_ORST_PWM0 | AON_ORST_PWM1 | AON_ORST_PWM2 | AON_ORST_PWM3) |
+        AON_CMU_SOFT_RSTN_CODEC_SET | AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
 
     aoncmu->MOD_CLK_DISABLE = AON_CMU_MANUAL_ACLK_DISABLE(AON_ACLK_PWM) |
-        AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_PWM0 | AON_OCLK_PWM1 | AON_OCLK_PWM2 | AON_OCLK_PWM3 | AON_OCLK_BTAON);
+        AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_PWM0 | AON_OCLK_PWM1 | AON_OCLK_PWM2 | AON_OCLK_PWM3);
 
     aoncmu->MOD_CLK_MODE &= ~AON_CMU_MODE_ACLK(AON_ACLK_CMU | AON_ACLK_GPIO_INT | AON_ACLK_WDT | AON_ACLK_PWM |
-        AON_ACLK_TIMER | AON_ACLK_IOMUX);
+        AON_ACLK_TIMER | AON_ACLK_PSC | AON_ACLK_IOMUX);
     cmu->PCLK_MODE &= ~(SYS_PCLK_CMU | SYS_PCLK_WDT | SYS_PCLK_TIMER0 | SYS_PCLK_TIMER1 | SYS_PCLK_TIMER2);
 
-    aoncmu->MIPI_CLK &= ~(AON_CMU_EN_CLK_PIX_DSI | AON_CMU_EN_CLK_PIX_CSI | AON_CMU_POL_CLK_DSI_IN |
-        AON_CMU_POL_CLK_CSI_IN);
-
     //cmu->HCLK_MODE = 0;
     //cmu->PCLK_MODE = SYS_PCLK_UART0 | SYS_PCLK_UART1 | SYS_PCLK_UART2;
     //cmu->OCLK_MODE = 0;
 #endif
+
+#ifdef CORE_SLEEP_POWER_DOWN
+    hal_cmu_set_wakeup_pc((uint32_t)hal_sleep_core_power_up);
+#endif
     hal_psc_init();
 }
 
 void BOOT_TEXT_FLASH_LOC hal_cmu_ema_init(void)
 {
-    // Never change EMA
+    // Never change EMA in best2300
 }
 
 void hal_cmu_lpu_wait_26m_ready(void)
 {
-    while ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCH26 | CMU_LPU_STATUS_26M)) ==
-            CMU_LPU_AUTO_SWITCH26);
+    while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_26M) == 0);
 }
 
 int hal_cmu_lpu_busy(void)
 {
-    if ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCH26 | CMU_LPU_STATUS_26M)) ==
-            CMU_LPU_AUTO_SWITCH26) {
+    if ((cmu->WAKEUP_CLK_CFG & CMU_LPU_AUTO_SWITCH26) &&
+        (cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_26M) == 0) {
         return 1;
     }
-    if ((cmu->WAKEUP_CLK_CFG & (CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_STATUS_PLL)) ==
-            CMU_LPU_AUTO_SWITCHPLL) {
+    if ((cmu->WAKEUP_CLK_CFG & CMU_LPU_AUTO_SWITCHPLL) &&
+        (cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_PLL) == 0) {
         return 1;
     }
     return 0;
@@ -2944,183 +2257,328 @@ int BOOT_TEXT_FLASH_LOC hal_cmu_lpu_init(enum HAL_CMU_LPU_CLK_CFG_T cfg)
     if (hal_cmu_lpu_busy()) {
         return -1;
     }
-    lpu_clk = cmu->WAKEUP_CLK_CFG;
-    lpu_clk &= ~(CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26);
 
     if (cfg == HAL_CMU_LPU_CLK_26M) {
-        lpu_clk |= CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCH26;
+        lpu_clk = CMU_LPU_AUTO_SWITCH26;
     } else if (cfg == HAL_CMU_LPU_CLK_PLL) {
-        lpu_clk |= CMU_LPU_EN_MCU | CMU_LPU_EN_A7 | CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26;
+        lpu_clk = CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26;
     } else {
+        lpu_clk = 0;
     }
 
     if (lpu_clk & CMU_LPU_AUTO_SWITCH26) {
         // Disable RAM wakeup early
         cmu->MCU_TIMER &= ~CMU_RAM_RETN_UP_EARLY;
         // MCU/ROM/RAM auto clock gating (which depends on RAM gating signal)
-        cmu->HCLK_MODE &= ~(SYS_HCLK_CORE0 | SYS_HCLK_ROM0 | SYS_HCLK_RAM0 | SYS_HCLK_RAM1 |
-            SYS_HCLK_RAM2 | SYS_HCLK_RAM3 | SYS_HCLK_RAM4 | SYS_HCLK_RAM5);
+        cmu->HCLK_MODE &= ~(SYS_HCLK_MCU | SYS_HCLK_ROM0 | SYS_HCLK_ROM1 | SYS_HCLK_ROM2 |
+            SYS_HCLK_RAM0 | SYS_HCLK_RAM1 | SYS_HCLK_RAM2 | SYS_HCLK_RAMRET | SYS_HCLK_RAM3 |
+            SYS_HCLK_RAM4 | SYS_HCLK_RAM5 | SYS_HCLK_RAM6);
         // AON_CMU enable auto switch 26M (AON_CMU must have selected 26M and disabled 52M/32K already)
-        aoncmu->CODEC_DIV |= AON_CMU_LPU_AUTO_SWITCH26;
+        aoncmu->CLK_SELECT |= AON_CMU_LPU_AUTO_SWITCH26;
     } else {
         // AON_CMU disable auto switch 26M
-        aoncmu->CODEC_DIV &= ~AON_CMU_LPU_AUTO_SWITCH26;
+        aoncmu->CLK_SELECT &= ~AON_CMU_LPU_AUTO_SWITCH26;
     }
 
-    lpu_clk |= CMU_TIMER_WT26(timer_26m);
+    cmu->WAKEUP_CLK_CFG = CMU_TIMER_WT26(timer_26m) | CMU_TIMER_WTPLL(0) | lpu_clk;
     if (timer_pll) {
-        lpu_clk |= CMU_TIMER_WTPLL(timer_pll);
         hal_sys_timer_delay(US_TO_TICKS(60));
-        cmu->WAKEUP_CLK_CFG = lpu_clk;
-    } else {
-        lpu_clk |= CMU_TIMER_WTPLL(0);
-        cmu->WAKEUP_CLK_CFG = lpu_clk;
+        cmu->WAKEUP_CLK_CFG = CMU_TIMER_WT26(timer_26m) | CMU_TIMER_WTPLL(timer_pll) | lpu_clk;
     }
+    return 0;
+}
 
-#ifndef ARM_CMNS
-    hal_sec_init(); //need metal_id
+#ifdef CORE_SLEEP_POWER_DOWN
+
+static int SRAM_TEXT_LOC hal_cmu_lpu_sleep_pd(void)
+{
+    uint32_t start;
+    uint32_t timeout;
+    uint32_t saved_hclk;
+    uint32_t saved_oclk;
+    uint32_t saved_top_clk;
+    uint32_t saved_clk_cfg;
+    uint32_t saved_periph_clk;
+    uint32_t saved_sys_div;
+    uint32_t saved_uart_clk;
+    uint32_t saved_codec_div;
+    uint32_t pll_locked;
+    uint32_t saved_cpu_regs[50];
+    register uint32_t sp asm("sp");
+    uint32_t stack_limit;
+
+#ifdef ROM_BUILD
+    extern uint32_t __rom_StackLimit[];
+    stack_limit = (uint32_t)__rom_StackLimit;
+#else
+    extern uint32_t __StackLimit[];
+    stack_limit = (uint32_t)__StackLimit;
 #endif
+    if (sp < stack_limit + 20 * 4) {
+        do {
+            asm volatile("nop; nop; nop; nop");
+        } while (1);
+    }
 
-    if (hal_get_chip_metal_id() >= HAL_CHIP_METAL_ID_4) {
-        cmu->CMU_REMAP = CMU_REMAP(0xF); //psram cache and flash cache
-    } else {
-        cmu->CMU_REMAP = CMU_REMAP(0xC); //psram cache
+    NVIC_PowerDownSleep(saved_cpu_regs, ARRAY_SIZE(saved_cpu_regs));
+
+    saved_hclk = cmu->HCLK_ENABLE;
+    saved_oclk = cmu->OCLK_ENABLE;
+    saved_periph_clk = cmu->PERIPH_CLK;
+    saved_sys_div = cmu->SYS_DIV;
+    saved_uart_clk = cmu->UART_CLK;
+    saved_codec_div = aoncmu->CODEC_DIV;
+
+    saved_top_clk = aoncmu->TOP_CLK_ENABLE;
+    saved_clk_cfg = cmu->SYS_CLK_ENABLE;
+
+    // Switch VAD clock to AON and disable codec HCLK
+    aoncmu->CODEC_DIV |= AON_CMU_SEL_CODEC_HCLK_AON;
+    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_HCLK_DISABLE;
+
+    // Disable memory/flash clock
+    cmu->OCLK_DISABLE = SYS_OCLK_FLASH;
+    cmu->HCLK_DISABLE = SYS_HCLK_FLASH;
+
+#ifndef ROM_BUILD
+    // Reset pll div if pll is enabled
+    if (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE) {
+        pmu_pll_div_reset_set(HAL_CMU_PLL_AUD);
+    }
+    if (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE) {
+        pmu_pll_div_reset_set(HAL_CMU_PLL_USB);
+    }
+#endif
+
+    // Switch system freq to 26M
+    cmu->SYS_CLK_ENABLE = CMU_SEL_OSC_SYS_ENABLE;
+    cmu->SYS_CLK_DISABLE = CMU_SEL_OSCX2_SYS_DISABLE | CMU_SEL_PLL_SYS_DISABLE;
+    cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_SYS_DISABLE;
+
+    // Shutdown PLLs
+    if (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE) {
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLAUD_DISABLE;
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLAUD_DISABLE;
+    }
+    if (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE) {
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLBB_DISABLE;
+    }
+    if (saved_top_clk & AON_CMU_PU_PLLUSB_ENABLE) {
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLUSB_DISABLE;
+    }
+
+    // Set power down wakeup bootmode
+    aoncmu->BOOTMODE = (aoncmu->BOOTMODE | HAL_SW_BOOTMODE_POWER_DOWN_WAKEUP) & HAL_SW_BOOTMODE_MASK;
+    // Set AON_CMU clock to 32K
+    aoncmu->CODEC_DIV &= ~(AON_CMU_SEL_CLK_OSC | AON_CMU_SEL_CLK_OSCX2);
+
+    hal_sleep_core_power_down();
+
+    while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_26M) == 0);
+
+    // Restore AON_CMU clock
+    aoncmu->CODEC_DIV = saved_codec_div;
+    // Clear power down wakeup bootmode
+    aoncmu->BOOTMODE = (aoncmu->BOOTMODE & ~HAL_SW_BOOTMODE_POWER_DOWN_WAKEUP) & HAL_SW_BOOTMODE_MASK;
+
+    // Disable memory/flash clock
+    cmu->OCLK_DISABLE = SYS_OCLK_FLASH;
+    cmu->HCLK_DISABLE = SYS_HCLK_FLASH;
+
+    // Restore PLLs
+    if (saved_top_clk & (AON_CMU_PU_PLLAUD_ENABLE | AON_CMU_PU_PLLUSB_ENABLE | AON_CMU_PU_PLLBB_ENABLE)) {
+        pll_locked = 0;
+        if (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE) {
+            aoncmu->TOP_CLK_ENABLE = AON_CMU_PU_PLLAUD_ENABLE;
+            pll_locked |= AON_CMU_LOCK_PLLAUD;
+        }
+        if (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE) {
+            aoncmu->TOP_CLK_ENABLE = AON_CMU_PU_PLLBB_ENABLE;
+            pll_locked |= AON_CMU_LOCK_PLLBB;
+        }
+        if (saved_top_clk & AON_CMU_PU_PLLUSB_ENABLE) {
+            aoncmu->TOP_CLK_ENABLE = AON_CMU_PU_PLLUSB_ENABLE;
+            pll_locked |= AON_CMU_LOCK_PLLUSB;
+        }
+#ifndef ROM_BUILD
+        hal_sys_timer_delay_us(10);
+        // Clear pll div reset if pll is enabled
+        if (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE) {
+            pmu_pll_div_reset_clear(HAL_CMU_PLL_AUD);
+        }
+        if (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE) {
+            pmu_pll_div_reset_clear(HAL_CMU_PLL_USB);
+        }
+#endif
+        start = hal_sys_timer_get();
+        timeout = HAL_CMU_PLL_LOCKED_TIMEOUT;
+        while (//(aoncmu->CODEC_DIV & pll_locked) != pll_locked &&
+                (hal_sys_timer_get() - start) < timeout);
+        if (saved_top_clk & AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE) {
+            aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE;
+        }
+        if (saved_top_clk & AON_CMU_EN_CLK_TOP_PLLBB_ENABLE) {
+            aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
+        }
+        if (saved_top_clk & AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE) {
+            aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
+        }
+    }
+
+    // Restore system freq
+    cmu->SYS_CLK_ENABLE = saved_clk_cfg &
+        (CMU_RSTN_DIV_FLS_ENABLE | CMU_RSTN_DIV_SYS_ENABLE);
+    cmu->SYS_CLK_ENABLE = saved_clk_cfg;
+    // The original system freq are at least 26M
+    //cmu->SYS_CLK_DISABLE = ~saved_clk_cfg;
+
+    cmu->PERIPH_CLK = saved_periph_clk;
+    cmu->SYS_DIV = saved_sys_div;
+    cmu->UART_CLK = saved_uart_clk;
+
+    // Switch VAD clock to MCU and enable codec HCLK if it is on before entering sleep
+    //aoncmu->CODEC_DIV &= ~AON_CMU_SEL_CODEC_HCLK_AON;
+    aoncmu->TOP_CLK_ENABLE = saved_top_clk & AON_CMU_EN_CLK_CODEC_HCLK_ENABLE;
+
+    int_lock();
+
+    NVIC_PowerDownWakeup(saved_cpu_regs, ARRAY_SIZE(saved_cpu_regs));
+
+    // TODO:
+    // 1) Restore hardware modules, e.g., timer, cache, flash, psram, dma, usb, uart, spi, i2c, sdmmc, codec
+    // 2) Recover system timer in rt_suspend() and rt_resume()
+    // 3) Dynamically select 32K sleep or power down sleep
+
+    if (saved_oclk & SYS_OCLK_FLASH) {
+        // Enable memory/flash clock
+        cmu->HCLK_ENABLE = saved_hclk;
+        cmu->OCLK_ENABLE = saved_oclk;
+        // Wait until memory/flash clock ready
+        hal_sys_timer_delay_us(2);
     }
 
     return 0;
 }
 
+#endif
+
 __STATIC_FORCEINLINE void cpu_sleep(uint32_t wakeup_cfg)
 {
     __DSB();
 
     if (wakeup_cfg & (CMU_LPU_AUTO_SWITCHPLL | CMU_LPU_AUTO_SWITCH26)) {
         // 1) Avoid race condition between LPU state machine entry and IRQ wakeup:
-        //    Wait 4 (at least 2) cycles of 32K clock, or 3248 cycles of 26M clock.
+        //    wait 4 (at least 2) cycles of 32K clock, or 3248 cycles of 26M clock
         // 2) Avoid race condition between CPU clock gating and RAM access when waiting:
-        //    No consecutive RAM access is allowed.
-        //    This is related to instruction width/alignment, pipeline state, branch prediction state, etc.
-        //    Unfortunately, it is too hard to control all of these, especially on M33.
-        __WFI();
+        //    No consecutive RAM access is allowed (all instructions must be 16-bit and must have no data access)
+        asm volatile (
+            "wfi;"
+            "movs.n r0, #0x3;"
+            "lsls r0, #8;"
+            "adds.n r0, #0x2c;"
+            "1:;"
+            "nop;"
+            "nop;"
+            "subs r0, 1;"
+            "bne.n 1b;"
+            :
+            :
+            : "r0", "cc" );
     } else {
         __WFI();
     }
 }
 
-int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
+static int SRAM_TEXT_LOC hal_cmu_lpu_sleep_normal(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
 {
     uint32_t start;
     uint32_t timeout;
-    uint32_t saved_pll_cfg;
+    uint32_t saved_hclk;
+    uint32_t saved_oclk;
+    uint32_t saved_top_clk;
     uint32_t saved_clk_cfg;
     uint32_t saved_codec_div;
-    uint32_t saved_top_clk;
     uint32_t wakeup_cfg;
-    uint32_t saved_hclk;
-    uint32_t saved_oclk;
+    bool pd_aud_pll;
+    bool pd_bb_pll;
+    bool wait_pll_locked;
 
+    pd_aud_pll = true;
+    pd_bb_pll = true;
+
+    saved_hclk = cmu->HCLK_ENABLE;
+    saved_oclk = cmu->OCLK_ENABLE;
     saved_codec_div = aoncmu->CODEC_DIV;
     saved_top_clk = aoncmu->TOP_CLK_ENABLE;
-    saved_pll_cfg = aoncmu->PLL_ENABLE;
     saved_clk_cfg = cmu->SYS_CLK_ENABLE;
-    saved_hclk = cmu->HCLK_ENABLE;
-    saved_oclk = cmu->OCLK_ENABLE;
 
-    // Switch VAD clock to AON and disable codec HCLK
-    aoncmu->CODEC_DIV |= AON_CMU_SEL_CODECHCLK_MCU;
     if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODECHCLK_DISABLE;
+        wakeup_cfg = cmu->WAKEUP_CLK_CFG;
     } else {
-        // Avoid auto-gating OSC and OSCX2
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX2_ENABLE | AON_CMU_EN_CLK_TOP_OSC_ENABLE;
+        wakeup_cfg = 0;
+        if (pll_user_map[HAL_CMU_PLL_AUD] & (1 << HAL_CMU_PLL_USER_AUD)) {
+            pd_aud_pll = false;
+        }
+        if (pll_user_map[HAL_CMU_PLL_USB] & (1 << HAL_CMU_PLL_USER_AUD)) {
+            pd_bb_pll = false;
+        }
     }
 
+    // Switch VAD clock to AON and disable codec HCLK
+    aoncmu->CODEC_DIV |= AON_CMU_SEL_CODEC_HCLK_AON;
     if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
-        wakeup_cfg = cmu->WAKEUP_CLK_CFG;
-    } else {
-        wakeup_cfg = 0;
+        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_CODEC_HCLK_DISABLE;
     }
 
-    // Disable memory/flash freq
-    cmu->OCLK_DISABLE = SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_FLASH;
-    cmu->HCLK_DISABLE = SYS_HCLK_PSRAM1G | SYS_HCLK_PSRAM200 | SYS_HCLK_FLASH;
+    // Disable memory/flash clock
+    cmu->OCLK_DISABLE = SYS_OCLK_FLASH;
+    cmu->HCLK_DISABLE = SYS_HCLK_FLASH;
 
 #ifndef ROM_BUILD
     // Reset pll div if pll is enabled
-    if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
-        pmu_pll_div_reset_set(HAL_CMU_PLL_USB);
+    if (pd_aud_pll && (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE)) {
+        pmu_pll_div_reset_set(HAL_CMU_PLL_AUD);
     }
-    if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
-        pmu_pll_div_reset_set(HAL_CMU_PLL_DDR);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
-        pmu_pll_div_reset_set(HAL_CMU_PLL_DSP);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
-        pmu_pll_div_reset_set(HAL_CMU_PLL_BB);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
-        pmu_pll_div_reset_set(HAL_CMU_PLL_BB_PSRAM);
+    if (pd_bb_pll && (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE)) {
+        pmu_pll_div_reset_set(HAL_CMU_PLL_USB);
     }
 #endif
 
     // Setup wakeup mask
-#ifdef __ARM_ARCH_ISA_ARM
-    cmu->WAKEUP_MASK0 = GICDistributor->ISENABLER[0];
-    cmu->WAKEUP_MASK1 = GICDistributor->ISENABLER[1];
-    cmu->WAKEUP_MASK2 = GICDistributor->ISENABLER[2];
-#else
     cmu->WAKEUP_MASK0 = NVIC->ISER[0];
     cmu->WAKEUP_MASK1 = NVIC->ISER[1];
-    cmu->WAKEUP_MASK2 = NVIC->ISER[2];
-#endif
-
-    // Switch system freq to 26M
-    cmu->SYS_CLK_ENABLE = CMU_SEL_MCU_SLOW_ENABLE;
-    cmu->SYS_CLK_DISABLE = CMU_SEL_MCU_OSC_4_DISABLE | CMU_SEL_MCU_OSC_2_DISABLE |
-        CMU_SEL_MCU_OSCX4_DISABLE | CMU_SEL_MCU_FAST_DISABLE | CMU_SEL_MCU_PLL_DISABLE;
-    cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_MCU_DISABLE;
-    // Shutdown PLLs
-    if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
-        aoncmu->PLL_DISABLE = AON_CMU_PU_PLLUSB_DISABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE;
-        aoncmu->PLL_DISABLE = AON_CMU_PU_PLLDDR_DISABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLA7_DISABLE;
-        aoncmu->PLL_DISABLE = AON_CMU_PU_PLLA7_DISABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
-        aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DIV_MCU_DISABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE;
-        aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DIV_PS_DISABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_ENABLE) {
-        aoncmu->PLL_DISABLE = AON_CMU_PU_PLLBB_DISABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
-        aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_OSCX4_DISABLE;
-        aoncmu->PLL_DISABLE = AON_CMU_PU_OSCX4_DISABLE;
-    }
 
     if (wakeup_cfg & CMU_LPU_AUTO_SWITCHPLL) {
         // Do nothing
         // Hardware will switch system freq to 32K and shutdown PLLs automatically
     } else {
+        // Switch system freq to 26M
+        cmu->SYS_CLK_ENABLE = CMU_SEL_OSC_SYS_ENABLE;
+        cmu->SYS_CLK_DISABLE = CMU_SEL_OSCX2_SYS_DISABLE | CMU_SEL_PLL_SYS_DISABLE;
+        cmu->SYS_CLK_DISABLE = CMU_RSTN_DIV_SYS_DISABLE;
+        // Shutdown PLLs
+        if (pd_aud_pll && (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE)) {
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLAUD_DISABLE;
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLAUD_DISABLE;
+        }
+        if (pd_bb_pll && (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE)) {
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLBB_DISABLE;
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLBB_DISABLE;
+        }
+        if (saved_top_clk & AON_CMU_PU_PLLUSB_ENABLE) {
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE;
+            aoncmu->TOP_CLK_DISABLE = AON_CMU_PU_PLLUSB_DISABLE;
+        }
         if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
             // Do nothing
             // Hardware will switch system freq to 32K automatically
         } else {
             // Manually switch AON_CMU clock to 32K
-            aoncmu->CODEC_DIV &= ~(AON_CMU_SEL_AON_OSC | AON_CMU_SEL_AON_OSCX2);
+            aoncmu->CODEC_DIV &= ~(AON_CMU_SEL_CLK_OSC | AON_CMU_SEL_CLK_OSCX2);
             // Switch system freq to 32K
-            cmu->SYS_CLK_DISABLE = CMU_SEL_MCU_SLOW_DISABLE;
+            cmu->SYS_CLK_DISABLE = CMU_SEL_OSC_SYS_DISABLE;
         }
     }
 
@@ -3134,13 +2592,11 @@ int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
             CMU_DEEPSLEEP_EN | CMU_MANUAL_RAM_RETN | CMU_DEEPSLEEP_START;
     }
 
-#ifndef __ARM_ARCH_ISA_ARM
     if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
         SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
     } else {
         SCB->SCR = 0;
     }
-#endif
 
     cpu_sleep(wakeup_cfg);
 
@@ -3149,7 +2605,18 @@ int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
         timeout = HAL_CMU_26M_READY_TIMEOUT + HAL_CMU_PLL_LOCKED_TIMEOUT + HAL_CMU_LPU_EXTRA_TIMEOUT;
         while ((cmu->WAKEUP_CLK_CFG & CMU_LPU_STATUS_PLL) == 0 &&
             (hal_sys_timer_get() - start) < timeout);
-        // Hardware will switch system to PLL divider and enable PLLs automatically
+        // !!! CAUTION !!!
+        // Hardware will switch system freq to PLL divider and enable PLLs automatically
+#ifndef ROM_BUILD
+        hal_sys_timer_delay_us(10);
+        // Clear pll div reset if pll is enabled
+        if (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE) {
+            pmu_pll_div_reset_clear(HAL_CMU_PLL_AUD);
+        }
+        if (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE) {
+            pmu_pll_div_reset_clear(HAL_CMU_PLL_USB);
+        }
+#endif
     } else {
         // Wait for 26M ready
         if (wakeup_cfg & CMU_LPU_AUTO_SWITCH26) {
@@ -3164,86 +2631,67 @@ int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
                 hal_sys_timer_delay(timeout);
             }
             // Switch system freq to 26M
-            cmu->SYS_CLK_ENABLE = CMU_SEL_MCU_SLOW_ENABLE;
+            cmu->SYS_CLK_ENABLE = CMU_SEL_OSC_SYS_ENABLE;
             // Restore AON_CMU clock
             aoncmu->CODEC_DIV = saved_codec_div;
         }
-    }
-
-    // System freq is 26M now and will be restored later
-    // Restore PLLs
-    if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
-        aoncmu->PLL_ENABLE = AON_CMU_PU_PLLUSB_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
-        aoncmu->PLL_ENABLE = AON_CMU_PU_PLLDDR_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
-        aoncmu->PLL_ENABLE = AON_CMU_PU_PLLA7_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
-        aoncmu->PLL_ENABLE = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_MCU_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
-        aoncmu->PLL_ENABLE = AON_CMU_PU_PLLBB_ENABLE | AON_CMU_PU_PLLBB_DIV_PS_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
-        aoncmu->PLL_ENABLE = AON_CMU_PU_OSCX4_ENABLE;
-    }
+        // System freq is 26M now and will be restored later
+        // Restore PLLs
+        if (saved_top_clk & (AON_CMU_PU_PLLAUD_ENABLE | AON_CMU_PU_PLLUSB_ENABLE | AON_CMU_PU_PLLBB_ENABLE)) {
+            wait_pll_locked = false;
+            if (pd_aud_pll && (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE)) {
+                aoncmu->TOP_CLK_ENABLE = AON_CMU_PU_PLLAUD_ENABLE;
+                wait_pll_locked = true;
+            }
+            if (pd_bb_pll && (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE)) {
+                aoncmu->TOP_CLK_ENABLE = AON_CMU_PU_PLLBB_ENABLE;
+                wait_pll_locked = true;
+            }
+            if (saved_top_clk & AON_CMU_PU_PLLUSB_ENABLE) {
+                aoncmu->TOP_CLK_ENABLE = AON_CMU_PU_PLLUSB_ENABLE;
+                wait_pll_locked = true;
+            }
+            if (wait_pll_locked) {
 #ifndef ROM_BUILD
-    hal_sys_timer_delay_us(20);
-    // Clear pll div reset if pll is enabled
-    if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
-        pmu_pll_div_reset_clear(HAL_CMU_PLL_USB);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
-        pmu_pll_div_reset_clear(HAL_CMU_PLL_DDR);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
-        pmu_pll_div_reset_clear(HAL_CMU_PLL_DSP);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
-        pmu_pll_div_reset_clear(HAL_CMU_PLL_BB);
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
-        pmu_pll_div_reset_clear(HAL_CMU_PLL_BB_PSRAM);
-    }
-    hal_sys_timer_delay_us(10);
-#endif
-    if (saved_pll_cfg & AON_CMU_PU_PLLUSB_ENABLE) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLDDR_ENABLE) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLA7_ENABLE) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLA7_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_MCU_ENABLE) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_PLLBB_DIV_PS_ENABLE) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE;
-    }
-    if (saved_pll_cfg & AON_CMU_PU_OSCX4_ENABLE) {
-        aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_OSCX4_ENABLE;
+                hal_sys_timer_delay_us(10);
+                // Clear pll div reset if pll is enabled
+                if (pd_aud_pll && (saved_top_clk & AON_CMU_PU_PLLAUD_ENABLE)) {
+                    pmu_pll_div_reset_clear(HAL_CMU_PLL_AUD);
+                }
+                if (pd_bb_pll && (saved_top_clk & AON_CMU_PU_PLLBB_ENABLE)) {
+                    pmu_pll_div_reset_clear(HAL_CMU_PLL_USB);
+                }
+#endif
+                start = hal_sys_timer_get();
+                timeout = HAL_CMU_PLL_LOCKED_TIMEOUT;
+                while ((hal_sys_timer_get() - start) < timeout);
+            }
+            if (pd_aud_pll && (saved_top_clk & AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE)) {
+                aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE;
+            }
+            if (pd_bb_pll && (saved_top_clk & AON_CMU_EN_CLK_TOP_PLLBB_ENABLE)) {
+                aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLBB_ENABLE;
+            }
+            if (saved_top_clk & AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE) {
+                aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE;
+            }
+        }
     }
+
     // Restore system freq
-    cmu->SYS_CLK_ENABLE = saved_clk_cfg & CMU_RSTN_DIV_MCU_ENABLE;
+    cmu->SYS_CLK_ENABLE = saved_clk_cfg &
+        (CMU_RSTN_DIV_FLS_ENABLE | CMU_RSTN_DIV_SYS_ENABLE);
     cmu->SYS_CLK_ENABLE = saved_clk_cfg;
     // The original system freq are at least 26M
     //cmu->SYS_CLK_DISABLE = ~saved_clk_cfg;
 
     // Switch VAD clock to MCU and enable codec HCLK if it is on before entering sleep
-    aoncmu->CODEC_DIV &= ~AON_CMU_SEL_CODECHCLK_MCU;
+    aoncmu->CODEC_DIV &= ~AON_CMU_SEL_CODEC_HCLK_AON;
     if (mode == HAL_CMU_LPU_SLEEP_MODE_CHIP) {
-        aoncmu->TOP_CLK_ENABLE = saved_top_clk & AON_CMU_EN_CLK_CODECHCLK_ENABLE;
-    } else {
-        // Restore the original top clock settings
-        aoncmu->TOP_CLK_DISABLE = ~saved_top_clk;
+        aoncmu->TOP_CLK_ENABLE = saved_top_clk & AON_CMU_EN_CLK_CODEC_HCLK_ENABLE;
     }
 
-    if (saved_oclk & (SYS_OCLK_PSRAM1G | SYS_OCLK_PSRAM200 | SYS_OCLK_FLASH)) {
+    if (saved_oclk & SYS_OCLK_FLASH) {
         // Enable memory/flash clock
         cmu->HCLK_ENABLE = saved_hclk;
         cmu->OCLK_ENABLE = saved_oclk;
@@ -3254,36 +2702,46 @@ int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
     return 0;
 }
 
+int SRAM_TEXT_LOC hal_cmu_lpu_sleep(enum HAL_CMU_LPU_SLEEP_MODE_T mode)
+{
+#ifdef CORE_SLEEP_POWER_DOWN
+    if (mode == HAL_CMU_LPU_SLEEP_MODE_POWER_DOWN) {
+        return hal_cmu_lpu_sleep_pd();
+    }
+#endif
+    return hal_cmu_lpu_sleep_normal(mode);
+}
+
 volatile uint32_t *hal_cmu_get_bootmode_addr(void)
 {
     return &aoncmu->BOOTMODE;
 }
 
+SRAM_TEXT_LOC
+volatile uint32_t *hal_cmu_get_memsc_addr(void)
+{
+    return &aoncmu->MEMSC[0];
+}
+
 void hal_cmu_bt_clock_enable(void)
 {
-    aoncmu->MOD_CLK_ENABLE = AON_CMU_MANUAL_OCLK_ENABLE(AON_OCLK_BTAON);
-    aocmu_reg_update_wait();
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_BT_ENABLE;
+    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_OSCX2_BT_ENABLE | AON_CMU_EN_CLK_OSC_BT_ENABLE | AON_CMU_EN_CLK_32K_BT_ENABLE;
     aocmu_reg_update_wait();
 }
 
 void hal_cmu_bt_clock_disable(void)
 {
-    aoncmu->MOD_CLK_DISABLE = AON_CMU_MANUAL_OCLK_DISABLE(AON_OCLK_BTAON);
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_BT_DISABLE;
+    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_OSCX2_BT_DISABLE | AON_CMU_EN_CLK_OSC_BT_DISABLE | AON_CMU_EN_CLK_32K_BT_DISABLE;
 }
 
 void hal_cmu_bt_reset_set(void)
 {
-    aoncmu->RESET_SET = AON_CMU_ORESETN_SET(AON_ORST_BTAON);
-    aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
+    aoncmu->RESET_SET = AON_CMU_SOFT_RSTN_BT_SET | AON_CMU_SOFT_RSTN_BTCPU_SET;
 }
 
 void hal_cmu_bt_reset_clear(void)
 {
-    aoncmu->RESET_CLR = AON_CMU_ORESETN_CLR(AON_ORST_BTAON);
-    aocmu_reg_update_wait();
-    aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_BT_CLR | AON_CMU_SOFT_RSTN_BTCPU_CLR;
+    aoncmu->RESET_CLR = AON_CMU_SOFT_RSTN_BT_CLR | AON_CMU_SOFT_RSTN_BTCPU_CLR;
     aocmu_reg_update_wait();
 }
 
@@ -3292,206 +2750,6 @@ void hal_cmu_bt_module_init(void)
     //btcmu->CLK_MODE = 0;
 }
 
-void hal_cmu_wifi_clock_enable(void)
-{
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_CLK_WF_ENABLE;
-    aocmu_reg_update_wait();
-}
-
-void hal_cmu_wifi_clock_disable(void)
-{
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_CLK_WF_DISABLE;
-}
-
-void hal_cmu_wifi_reset_set(void)
-{
-    aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_WF_SET | AON_CMU_SOFT_RSTN_WFCPU_SET;
-}
-
-void hal_cmu_wifi_reset_clear(void)
-{
-    aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_WF_CLR | AON_CMU_SOFT_RSTN_WFCPU_CLR;
-    aocmu_reg_update_wait();
-}
-
-void BOOT_TEXT_FLASH_LOC hal_cmu_wlan_set_sleep_allow(uint32_t auto_mode)
-{
-    if (auto_mode) { //controlled by wifi sleep signal
-        aoncmu->RESERVED_0E8 = aoncmu->RESERVED_0E8 & (~((1<<4)|(1<<6)));
-    } else { //force allow cmu sleep
-        aoncmu->RESERVED_0E8 = (aoncmu->RESERVED_0E8 & (~((1<<5)|(1<<7)))) | ((1<<4)|(1<<6));
-    }
-}
-
-static void GPV_init(void)
-{
-#ifdef GPV_MAIN_BASE
-    volatile uint32_t *gpv_ctrl_psram = (volatile uint32_t *)(GPV_MAIN_BASE+0x6000);
-    volatile uint32_t *gpv_ctrl_x2h = (volatile uint32_t *)(GPV_MAIN_BASE+0x7000);
-    gpv_ctrl_psram[17] |= 0x2; //0x50306044
-    gpv_ctrl_x2h[17] |= 0x2; //0x50307044
-#endif
-}
-
-void hal_cmu_dsp_clock_enable(void)
-{
-    enum HAL_CMU_PLL_T dsp;
-#ifdef DSP_ENABLE
-    hal_psc_a7_enable();
-#endif
-    // DSP AXI clock divider defaults to 4 (div = reg_val + 2)
-    cmu->DSP_DIV = SET_BITFIELD(cmu->DSP_DIV, CMU_CFG_DIV_XCLK, 2);
-    cmu->XCLK_ENABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PER |
-        SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
-        SYS_XCLK_GPV_MAIN;
-    cmu->APCLK_ENABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
-    cmu->HCLK_ENABLE = SYS_HCLK_AX2H_A7;
-
-    cmu->DSP_CFG0 |= CMU_CA7_DBGEN_MASK | CMU_CA7_SPIDEN_MASK | CMU_CA7_NIDEN_MASK | CMU_CA7_SPNIDEN_MASK;
-
-    cmu->PERIPH_CLK |= CMU_A7_ALLIRQ_MASK;
-    cmu->DSP_CFG0 |= CMU_A7TOM33_IRQS_MASK(8);
-
-#ifdef DSP_USE_BBPLL
-    dsp = HAL_CMU_PLL_BB;
-#elif defined(DSP_USE_USBPLL)
-    dsp = HAL_CMU_PLL_USB;
-#else
-    dsp = HAL_CMU_PLL_DSP;
-#endif
-    hal_cmu_dsp_select_pll(dsp);
-    hal_cmu_pll_enable(dsp, HAL_CMU_PLL_USER_DSP);
-
-    hal_cmu_dsp_set_freq(HAL_CMU_FREQ_780M);
-
-#ifdef DSP_ENABLE
-    hal_cmu_clock_enable(HAL_CMU_MOD_O_A7);
-    hal_cmu_clock_enable(HAL_CMU_MOD_O_WDT_AP);
-    hal_cmu_clock_enable(HAL_CMU_MOD_O_TIMER0_AP);
-    hal_cmu_clock_enable(HAL_CMU_MOD_O_TIMER1_AP);
-#ifndef ARM_CMNS
-    ///TODO: add cmse interface if trustzone is enabled
-    GPV_init();
-#endif
-#endif
-}
-
-void hal_cmu_dsp_clock_disable(void)
-{
-    enum HAL_CMU_PLL_T dsp;
-
-    hal_cmu_clock_disable(HAL_CMU_MOD_O_A7);
-
-#ifdef DSP_USE_BBPLL
-    dsp = HAL_CMU_PLL_BB;
-#elif defined(DSP_USE_USBPLL)
-    dsp = HAL_CMU_PLL_USB;
-#else
-    dsp = HAL_CMU_PLL_DSP;
-#endif
-    hal_cmu_pll_disable(dsp, HAL_CMU_PLL_USER_DSP);
-
-    cmu->XCLK_DISABLE = SYS_XCLK_DMA | SYS_XCLK_NIC | SYS_XCLK_IMEMLO | SYS_XCLK_IMEMHI | SYS_XCLK_PER |
-        SYS_XCLK_PDBG | SYS_XCLK_CORE0 | SYS_XCLK_CORE1 | SYS_XCLK_CORE2 | SYS_XCLK_CORE3 | SYS_XCLK_DBG | SYS_XCLK_SCU |
-        SYS_XCLK_GPV_MAIN;
-    cmu->APCLK_DISABLE = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
-    cmu->OCLK_DISABLE = SYS_OCLK_WDT_AP | SYS_OCLK_TIMER0_AP | SYS_OCLK_TIMER1_AP;
-    cmu->HCLK_DISABLE = SYS_HCLK_AX2H_A7;
-
-    hal_psc_a7_disable();
-}
-
-void hal_cmu_dsp_reset_set(void)
-{
-    aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET;
-    cmu->ORESET_SET = SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP;
-    cmu->XRESET_SET = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PER |
-        SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
-        SYS_XRST_GPV_MAIN;
-    cmu->APRESET_SET = SYS_APRST_BOOTREG | SYS_APRST_WDT | SYS_APRST_TIMER0 | SYS_APRST_TIMER1 | SYS_APRST_TQ | SYS_APRST_DAP;
-    cmu->HRESET_SET = SYS_HRST_AX2H_A7;
-}
-
-void hal_cmu_dsp_reset_clear(void)
-{
-    cmu->APRESET_CLR = SYS_APCLK_BOOTREG | SYS_APCLK_WDT| SYS_APCLK_TIMER0 | SYS_APCLK_TIMER1 | SYS_APCLK_TQ | SYS_APCLK_DAP;
-    cmu->XRESET_CLR = SYS_XRST_DMA | SYS_XRST_NIC | SYS_XRST_IMEMLO | SYS_XRST_IMEMHI | SYS_XRST_PER |
-        SYS_XRST_PDBG | SYS_XRST_CORE0 | SYS_XRST_CORE1 | SYS_XRST_CORE2 | SYS_XRST_CORE3 | SYS_XRST_DBG | SYS_XRST_SCU |
-        SYS_XRST_GPV_MAIN;
-    cmu->ORESET_CLR = SYS_ORST_WDT_AP | SYS_ORST_TIMER0_AP | SYS_ORST_TIMER1_AP;
-    cmu->HRESET_CLR = SYS_HRST_AX2H_A7;
-    aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7_CLR;
-    aocmu_reg_update_wait();
-}
-
-void hal_cmu_dsp_reset_hold(void)
-{
-    aoncmu->SOFT_RSTN_SET = AON_CMU_SOFT_RSTN_A7_SET | AON_CMU_SOFT_RSTN_A7CPU_SET;
-    cmu->HRESET_SET = SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G;
-    cmu->ORESET_SET = SYS_ORST_PSRAM1G;
-    cmu->ORESET_SET = SYS_ORST_WDT_AP | SYS_ORST_TIMER1_AP;
-}
-
-void hal_cmu_dsp_reset_release(void)
-{
-    cmu->ORESET_CLR = SYS_ORST_WDT_AP | SYS_ORST_TIMER1_AP;
-    cmu->ORESET_CLR = SYS_ORST_PSRAM1G;
-    cmu->HRESET_CLR = SYS_HRST_AX2H_A7 | SYS_HRST_PSRAM1G;
-    aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7_CLR;
-    aocmu_reg_update_wait();
-}
-
-void hal_cmu_dsp_init_boot_reg(uint32_t entry)
-{
-    int i;
-    volatile uint32_t *boot = (volatile uint32_t *)DSP_BOOT_REG;
-
-    // Unlock
-    boot[32] = 0xCAFE0001;
-    __DMB();
-
-    for (i = 0; i < 8; i++) {
-        // ldr pc, [pc, #24]
-        boot[0 + i] = 0xE59FF018;
-        // Init_Handler
-        boot[8 + i] = 0x00000040;
-    }
-    // b   40
-    boot[16] = 0xEAFFFFFE;
-
-    // Update reset handler
-    boot[8] = entry;
-
-    // Lock
-    __DMB();
-    boot[32] = 0xCAFE0000;
-    __DMB();
-}
-
-void hal_cmu_dsp_start_cpu(void)
-{
-    hal_cmu_dsp_set_freq(HAL_CMU_FREQ_156M);//div 5
-    aoncmu->SOFT_RSTN_CLR = AON_CMU_SOFT_RSTN_A7CPU_CLR;
-}
-
-void hal_cmu_dsp_stop_cpu(void)
-{
-    uint32_t lock;
-    lock = int_lock();
-#ifdef PSRAMUHS_ENABLE
-    hal_psramuhs_hold();
-#endif
-    hal_cmu_dsp_reset_hold();
-    //hal_cmu_dsp_clock_disable();
-
-#ifdef PSRAMUHS_ENABLE
-    //hal_cmu_dsp_clock_enable();
-    hal_cmu_dsp_reset_release();
-    hal_psramuhs_release();
-#endif
-    int_unlock(lock);
-}
-
 uint32_t hal_cmu_get_aon_chip_id(void)
 {
     return aoncmu->CHIP_ID;
@@ -3504,18 +2762,9 @@ uint32_t hal_cmu_get_aon_revision_id(void)
 
 void hal_cmu_cp_enable(uint32_t sp, uint32_t entry)
 {
-    struct CP_STARTUP_CFG_T * cp_cfg;
-    uint32_t cfg_addr;
-
-    // Use (sp - 128) as the default vector. The Address must aligned to 128-byte boundary.
-    cfg_addr = (sp - (1 << 7)) & ~((1 << 7) - 1);
-
-    cmu->CP_VTOR = cfg_addr;
-    cp_cfg = (struct CP_STARTUP_CFG_T *)cfg_addr;
-
     cp_cfg->stack = sp;
     cp_cfg->reset_hdlr = (uint32_t)system_cp_reset_handler;
-    cp_entry = entry;
+    cp_cfg->entry = entry;
 
     hal_cmu_clock_enable(HAL_CMU_MOD_H_CP);
     hal_cmu_reset_clear(HAL_CMU_MOD_H_CP);
@@ -3529,153 +2778,5 @@ void hal_cmu_cp_disable(void)
 
 uint32_t hal_cmu_cp_get_entry_addr(void)
 {
-    return cp_entry;
-}
-
-void hal_cmu_cp_boot(uint32_t entry)
-{
-    cmu->CP_VTOR = entry;
-
-    hal_cmu_clock_enable(HAL_CMU_MOD_H_CACHE1);
-    hal_cmu_reset_clear(HAL_CMU_MOD_H_CACHE1);
-
-    hal_cmu_clock_enable(HAL_CMU_MOD_H_CP);
-    hal_cmu_reset_clear(HAL_CMU_MOD_H_CP);
-}
-
-void hal_cmu_jtag_sel(enum HAL_CMU_JTAG_SEL_T sel)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    cmu->PERIPH_CLK &= ~CMU_JTAG_SEL_MASK;
-    switch (sel) {
-        case HAL_CMU_JTAG_SEL_CP:
-            cmu->PERIPH_CLK |= CMU_JTAG_SEL_CP;
-            break;
-        case HAL_CMU_JTAG_SEL_A7:
-            cmu->PERIPH_CLK |= CMU_JTAG_SEL_A7;
-            break;
-        default:
-            break;
-    }
-    int_unlock(lock);
-}
-
-void hal_cmu_dsp_setup(void)
-{
-    hal_sys_timer_open();
-
-    hal_sysfreq_req(HAL_SYSFREQ_USER_INIT, HAL_CMU_FREQ_390M);
-
-}
-
-void hal_cmu_flash0_dual_die()
-{
-    cmu->MCU_TIMER &= ~CMU_FLS1_IO_SEL;
-}
-
-void hal_cmu_flash1_enable()
-{
-    //aoncmu->FLASH_IOCFG |= AON_CMU_PU_FLASH1_IO;
-    aoncmu->FLASH_IOCFG = SET_BITFIELD(aoncmu->FLASH_IOCFG, AON_CMU_FLASH1_IODRV, 0x7) | AON_CMU_PU_FLASH1_IO;
-}
-
-void hal_cmu_set_flash0_x8_mode(uint32_t en)
-{
-    if (en)
-        cmu->MCU_TIMER |= CMU_FLS0_X8_SEL;
-    else
-        cmu->MCU_TIMER &= ~CMU_FLS0_X8_SEL;
-}
-
-void hal_cmu_set_flash0_size(enum HAL_FLASH0_SIZE_CFG cfg)
-{
-    *(volatile uint32_t *)(ICACHE_CTRL_BASE + 0x44) = cfg;
-}
-
-uint32_t hal_cmu_get_osc_ready_cycle_cnt(void)
-{
-    uint32_t cnt=10;
-
-
-
-    return cnt;
-}
-
-uint32_t hal_cmu_get_osc_switch_overhead(void)
-{
-        return 6;
-}
-
-void hal_cmu_bt_sys_set_freq(enum HAL_CMU_FREQ_T freq)
-{
-
-}
-
-void hal_cmu_bt_sys_clock_force_on(void)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    hal_psc_dslp_force_on_bt_enable();
-    aoncmu->TOP_CLK_ENABLE = AON_CMU_EN_BT_CLK_SYS_ENABLE;
-    int_unlock(lock);
-    aocmu_reg_update_wait();
-}
-
-void hal_cmu_bt_sys_clock_auto(void)
-{
-    uint32_t lock;
-
-    lock = int_lock();
-    aoncmu->TOP_CLK_DISABLE = AON_CMU_EN_BT_CLK_SYS_DISABLE;
-    hal_psc_dslp_force_on_bt_disable();
-    int_unlock(lock);
-}
-
-#ifdef REUSE_WIFI_CALI_RESULT
-extern void save_wifi_cali_result();
-#endif
-
-void hal_cmu_shutdown_hook(void)
-{
-    int_lock();
-    hal_cmu_codec_clock_disable();
-    hal_cmu_codec_rs_disable();
-
-    hal_cmu_dsp_reset_set();
-    hal_cmu_dsp_clock_disable();
-
-#ifdef REUSE_WIFI_CALI_RESULT
-    save_wifi_cali_result();
-#endif
-
-    hal_cmu_wifi_reset_set();
-    hal_cmu_wifi_clock_disable();
-    hal_cmu_cp_disable();
-    hal_cmu_bt_reset_set();
-    hal_cmu_bt_clock_disable();
-
-    // hal_norflash_deinit();
-
-    hal_cmu_mem_set_freq(HAL_CMU_FREQ_26M);
-    hal_cmu_sys_set_freq(HAL_CMU_FREQ_26M);
-
-    // psramuhsphy_sleep();
-    // hal_psram_phy_sleep();
-    // hal_cmu_pll_disable(HAL_CMU_PLL_BB, HAL_CMU_PLL_USER_ALL);
-    // hal_cmu_pll_disable(HAL_CMU_PLL_BB_PSRAM, HAL_CMU_PLL_USER_ALL);
-    // hal_cmu_pll_disable(HAL_CMU_PLL_DDR, HAL_CMU_PLL_USER_ALL);
-    // hal_cmu_pll_disable(HAL_CMU_PLL_DSP, HAL_CMU_PLL_USER_ALL);
-    // hal_cmu_pll_disable(HAL_CMU_PLL_USB, HAL_CMU_PLL_USER_ALL);
-}
-
-void hal_cmu_sys_reboot(void)
-{
-#if defined(FLASH_SUSPEND) && defined(FLASH_API_GUARD_THREAD)
-    norflash_api_flush_all();
-#endif
-    hal_cmu_shutdown_hook();
-    hal_cmu_reset_set(HAL_CMU_MOD_GLOBAL);
+    return cp_cfg->entry;
 }

platform/hal/best2300p/hal_cmu_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/hal_cmu_best2300p.h bes/platform/hal/best2300p/hal_cmu_best2300p.h
index aafdb5fb036..3ac2ef6ad59 100644
--- a/platform/hal/best2300p/hal_cmu_best2300p.h
+++ b/platform/hal/best2300p/hal_cmu_best2300p.h
@@ -19,131 +19,120 @@
 extern "C" {
 #endif
 
-#define HAL_CMU_VALID_CRYSTAL_FREQ          { 24000000, 40000000, }
+#define HAL_CMU_VALID_CRYSTAL_FREQ          { 26000000, 24000000, 40000000, 48000000, }
 
 enum HAL_CMU_MOD_ID_T {
     // HCLK/HRST
     HAL_CMU_MOD_H_MCU,          // 0
-    HAL_CMU_MOD_H_CACHE0,       // 1
-    HAL_CMU_MOD_H_CP,           // 2
-    HAL_CMU_MOD_H_CACHE1,       // 3
-    HAL_CMU_MOD_H_ADMA,         // 4
-    HAL_CMU_MOD_H_GDMA,         // 5
-    HAL_CMU_MOD_H_SEC_ENG,      // 6
-    HAL_CMU_MOD_H_USBC,         // 7
-    HAL_CMU_MOD_H_USBH,         // 8
-    HAL_CMU_MOD_H_I2C_SLAVE,    // 9
-    HAL_CMU_MOD_H_AX2H_A7,      // 10
-    HAL_CMU_MOD_H_AH2H_WF,      // 11
-    HAL_CMU_MOD_H_AH2H_BT,      // 12
-    HAL_CMU_MOD_H_CODEC,        // 13
-    HAL_CMU_MOD_H_AHB1,         // 14
-    HAL_CMU_MOD_H_AHB0,         // 15
-    HAL_CMU_MOD_H_PSRAM1G,      // 16
-    HAL_CMU_MOD_H_PSRAM200,     // 17
-    HAL_CMU_MOD_H_FLASH,        // 18
-    HAL_CMU_MOD_H_RAM5,         // 19
-    HAL_CMU_MOD_H_RAM4,         // 20
-    HAL_CMU_MOD_H_RAM3,         // 21
-    HAL_CMU_MOD_H_RAM2,         // 22
-    HAL_CMU_MOD_H_RAM1,         // 23
-    HAL_CMU_MOD_H_RAM0,         // 24
-    HAL_CMU_MOD_H_ROM0,         // 25
-    HAL_CMU_MOD_H_BT_DUMP,      // 26
-    HAL_CMU_MOD_H_WF_DUMP,      // 27
-    HAL_CMU_MOD_H_SDMMC,        // 28
-    HAL_CMU_MOD_H_CHECKSUM,     // 29
-    HAL_CMU_MOD_H_CRC,          // 30
-    HAL_CMU_MOD_H_FLASH1,       // 31
+    HAL_CMU_MOD_H_ROM0,         // 1
+    HAL_CMU_MOD_H_ROM1,         // 2
+    HAL_CMU_MOD_H_ROM2,         // 3
+    HAL_CMU_MOD_H_RAM0,         // 4
+    HAL_CMU_MOD_H_RAM1,         // 5
+    HAL_CMU_MOD_H_RAM2,         // 6
+    HAL_CMU_MOD_H_RAMRET,       // 7
+    HAL_CMU_MOD_H_AHB0,         // 8
+    HAL_CMU_MOD_H_AHB1,         // 9
+    HAL_CMU_MOD_H_AH2H_BT,      // 10
+    HAL_CMU_MOD_H_ADMA,         // 11
+    HAL_CMU_MOD_H_GDMA,         // 12
+    HAL_CMU_MOD_H_CACHE,        // 13
+    HAL_CMU_MOD_H_FLASH,        // 14
+    HAL_CMU_MOD_H_SDMMC,        // 15
+    HAL_CMU_MOD_H_USBC,         // 16
+    HAL_CMU_MOD_H_CODEC,        // 17
+    HAL_CMU_MOD_H_FFT,          // 18
+    HAL_CMU_MOD_H_I2C_SLAVE,    // 19
+    HAL_CMU_MOD_H_USBH,         // 20
+    HAL_CMU_MOD_H_SENSOR_ENG,   // 21
+    HAL_CMU_MOD_H_BT_DUMP,      // 22
+    HAL_CMU_MOD_H_CP,           // 23
+    HAL_CMU_MOD_H_RAM3,         // 24
+    HAL_CMU_MOD_H_RAM4,         // 25
+    HAL_CMU_MOD_H_RAM5,         // 26
+    HAL_CMU_MOD_H_RAM6,         // 27
+    HAL_CMU_MOD_H_SEC_ENG,      // 28
+    HAL_CMU_MOD_H_ICACHE0,      // 29
+    HAL_CMU_MOD_H_ICACHE1,      // 30
     // PCLK/PRST
-    HAL_CMU_MOD_P_CMU,          // 0
-    HAL_CMU_MOD_P_WDT,          // 1
-    HAL_CMU_MOD_P_TIMER0,       // 2
-    HAL_CMU_MOD_P_TIMER1,       // 3
-    HAL_CMU_MOD_P_TIMER2,       // 4
-    HAL_CMU_MOD_P_I2C0,         // 5
-    HAL_CMU_MOD_P_I2C1,         // 6
-    HAL_CMU_MOD_P_SPI,          // 7
-    HAL_CMU_MOD_P_SLCD,         // 8
-    HAL_CMU_MOD_P_SPI_ITN,      // 9
-    HAL_CMU_MOD_P_SPI_PHY,      // 10
-    HAL_CMU_MOD_P_UART0,        // 11
-    HAL_CMU_MOD_P_UART1,        // 12
-    HAL_CMU_MOD_P_UART2,        // 13
-    HAL_CMU_MOD_P_PCM,          // 14
-    HAL_CMU_MOD_P_I2S0,         // 15
-    HAL_CMU_MOD_P_SPDIF0,       // 16
-    HAL_CMU_MOD_P_SEC_ENG,      // 20
-    HAL_CMU_MOD_P_I2S1,         // 25
+    HAL_CMU_MOD_P_CMU,          // 31
+    HAL_CMU_MOD_P_WDT,          // 32
+    HAL_CMU_MOD_P_TIMER0,       // 33
+    HAL_CMU_MOD_P_TIMER1,       // 34
+    HAL_CMU_MOD_P_TIMER2,       // 35
+    HAL_CMU_MOD_P_I2C0,         // 36
+    HAL_CMU_MOD_P_I2C1,         // 37
+    HAL_CMU_MOD_P_SPI,          // 38
+    HAL_CMU_MOD_P_SLCD,         // 39
+    HAL_CMU_MOD_P_SPI_ITN,      // 40
+    HAL_CMU_MOD_P_SPI_PHY,      // 41
+    HAL_CMU_MOD_P_UART0,        // 42
+    HAL_CMU_MOD_P_UART1,        // 43
+    HAL_CMU_MOD_P_UART2,        // 44
+    HAL_CMU_MOD_P_PCM,          // 45
+    HAL_CMU_MOD_P_I2S0,         // 46
+    HAL_CMU_MOD_P_SPDIF0,       // 47
+    HAL_CMU_MOD_P_I2S1,         // 48
+    HAL_CMU_MOD_P_SEC_ENG,      // 49
     // OCLK/ORST
-    HAL_CMU_MOD_O_SLEEP,        // 0
-    HAL_CMU_MOD_O_USB,          // 1
-    HAL_CMU_MOD_O_USB32K,       // 2
-    HAL_CMU_MOD_O_PSRAM1G,      // 3
-    HAL_CMU_MOD_O_PSRAM200,     // 4
-    HAL_CMU_MOD_O_FLASH,        // 5
-    HAL_CMU_MOD_O_SDMMC,        // 6
-    HAL_CMU_MOD_O_WDT,          // 7
-    HAL_CMU_MOD_O_TIMER0,       // 8
-    HAL_CMU_MOD_O_TIMER1,       // 9
-    HAL_CMU_MOD_O_TIMER2,       // 10
-    HAL_CMU_MOD_O_I2C0,         // 11
-    HAL_CMU_MOD_O_I2C1,         // 12
-    HAL_CMU_MOD_O_SPI,          // 13
-    HAL_CMU_MOD_O_SLCD,         // 14
-    HAL_CMU_MOD_O_SPI_ITN,      // 15
-    HAL_CMU_MOD_O_SPI_PHY,      // 16
-    HAL_CMU_MOD_O_UART0,        // 17
-    HAL_CMU_MOD_O_UART1,        // 18
-    HAL_CMU_MOD_O_UART2,        // 19
-    HAL_CMU_MOD_O_PCM,          // 20
-    HAL_CMU_MOD_O_I2S0,         // 21
-    HAL_CMU_MOD_O_SPDIF0,       // 22
-    HAL_CMU_MOD_O_I2S1,         // 23
-    HAL_CMU_MOD_O_A7,           // 24
-    HAL_CMU_MOD_O_TSF,          // 25
-    HAL_CMU_MOD_O_WDT_AP,       // 26
-    HAL_CMU_MOD_O_TIMER0_AP,    // 27
-    HAL_CMU_MOD_O_TIMER1_AP,    // 28
-    HAL_CMU_MOD_O_FLASH1,       // 29
-    HAL_CMU_MOD_O_I2C2,         // 30
-    HAL_CMU_MOD_O_UART3,        // 31
+    HAL_CMU_MOD_O_SLEEP,        // 50
+    HAL_CMU_MOD_O_FLASH,        // 51
+    HAL_CMU_MOD_O_USB,          // 52
+    HAL_CMU_MOD_O_SDMMC,        // 53
+    HAL_CMU_MOD_O_WDT,          // 54
+    HAL_CMU_MOD_O_TIMER0,       // 55
+    HAL_CMU_MOD_O_TIMER1,       // 56
+    HAL_CMU_MOD_O_TIMER2,       // 57
+    HAL_CMU_MOD_O_I2C0,         // 58
+    HAL_CMU_MOD_O_I2C1,         // 59
+    HAL_CMU_MOD_O_SPI,          // 60
+    HAL_CMU_MOD_O_SLCD,         // 61
+    HAL_CMU_MOD_O_SPI_ITN,      // 62
+    HAL_CMU_MOD_O_SPI_PHY,      // 63
+    HAL_CMU_MOD_O_UART0,        // 64
+    HAL_CMU_MOD_O_UART1,        // 65
+    HAL_CMU_MOD_O_UART2,        // 66
+    HAL_CMU_MOD_O_I2S0,         // 67
+    HAL_CMU_MOD_O_SPDIF0,       // 68
+    HAL_CMU_MOD_O_PCM,          // 69
+    HAL_CMU_MOD_O_USB32K,       // 70
+    HAL_CMU_MOD_O_I2S1,         // 71
 
     // AON ACLK/ARST
-    HAL_CMU_AON_A_CMU,          // 0
-    HAL_CMU_AON_A_GPIO,         // 1
-    HAL_CMU_AON_A_GPIO_INT,     // 2
-    HAL_CMU_AON_A_WDT,          // 3
-    HAL_CMU_AON_A_PWM,          // 4
-    HAL_CMU_AON_A_TIMER,        // 5
-    HAL_CMU_AON_A_IOMUX,        // 6
-    HAL_CMU_AON_A_APBC,         // 8
-    HAL_CMU_AON_A_H2H_MCU,      // 9
-    HAL_CMU_AON_A_PSC,          // 10
+    HAL_CMU_AON_A_CMU,          // 72
+    HAL_CMU_AON_A_GPIO,         // 73
+    HAL_CMU_AON_A_GPIO_INT,     // 74
+    HAL_CMU_AON_A_WDT,          // 75
+    HAL_CMU_AON_A_PWM,          // 76
+    HAL_CMU_AON_A_TIMER,        // 77
+    HAL_CMU_AON_A_PSC,          // 78
+    HAL_CMU_AON_A_IOMUX,        // 79
+    HAL_CMU_AON_A_APBC,         // 80
+    HAL_CMU_AON_A_H2H_MCU,      // 81
     // AON OCLK/ORST
-    HAL_CMU_AON_O_WDT,          // 13
-    HAL_CMU_AON_O_TIMER,        // 14
-    HAL_CMU_AON_O_GPIO,         // 15
-    HAL_CMU_AON_O_PWM0,         // 16
-    HAL_CMU_AON_O_PWM1,         // 17
-    HAL_CMU_AON_O_PWM2,         // 18
-    HAL_CMU_AON_O_PWM3,         // 19
-    HAL_CMU_AON_O_IOMUX,        // 20
-    HAL_CMU_AON_O_SLP32K,       // 21
-    HAL_CMU_AON_O_SLP26M,       // 22
-    HAL_CMU_AON_O_SPIDPD,       // 23
-    HAL_CMU_AON_O_WLAN32K,      // 24
-    HAL_CMU_AON_O_WLAN26M,      // 25
-    HAL_CMU_AON_O_BTAON,        // 26
+    HAL_CMU_AON_O_WDT,          // 82
+    HAL_CMU_AON_O_TIMER,        // 83
+    HAL_CMU_AON_O_GPIO,         // 84
+    HAL_CMU_AON_O_PWM0,         // 85
+    HAL_CMU_AON_O_PWM1,         // 86
+    HAL_CMU_AON_O_PWM2,         // 87
+    HAL_CMU_AON_O_PWM3,         // 88
+    HAL_CMU_AON_O_IOMUX,        // 89
+    HAL_CMU_AON_O_SLP32K,       // 90
+    HAL_CMU_AON_O_SLP26M,       // 91
+    HAL_CMU_AON_RESERVED0,      // 92
+    HAL_CMU_AON_RESERVED1,      // 93
+    HAL_CMU_AON_RESERVED2,      // 94
+    HAL_CMU_AON_RESERVED3,      // 95
     // AON SUBSYS
-    HAL_CMU_AON_MCU,            // 2
-    HAL_CMU_AON_CODEC,          // 3
-    HAL_CMU_AON_WF,             // 4
-    HAL_CMU_AON_BT,             // 5
-    HAL_CMU_AON_MCUCPU,         // 6
-    HAL_CMU_AON_WFCPU,          // 7
-    HAL_CMU_AON_BTCPU,          // 8
-    HAL_CMU_AON_GLOBAL,         // 9
+    HAL_CMU_AON_MCU,            // 96
+    HAL_CMU_AON_CODEC,          // 97
+    HAL_CMU_AON_RESERVED4,      // 98
+    HAL_CMU_AON_BT,             // 99
+    HAL_CMU_AON_MCUCPU,         // 100
+    HAL_CMU_AON_RESERVED5,      // 101
+    HAL_CMU_AON_BTCPU,          // 102
+    HAL_CMU_AON_GLOBAL,         // 103
 
     HAL_CMU_MOD_QTY,
 
@@ -156,43 +145,48 @@ enum HAL_CMU_MOD_ID_T {
     HAL_CMU_MOD_O_PWM1 = HAL_CMU_AON_O_PWM1,
     HAL_CMU_MOD_O_PWM2 = HAL_CMU_AON_O_PWM2,
     HAL_CMU_MOD_O_PWM3 = HAL_CMU_AON_O_PWM3,
-    HAL_CMU_H_DCACHE = HAL_CMU_MOD_H_CACHE0,
-    HAL_CMU_H_ICACHE = HAL_CMU_MOD_H_CACHE1,
 
+    HAL_CMU_H_ICACHECP = HAL_CMU_MOD_H_ICACHE0,
+    HAL_CMU_H_DCACHECP = HAL_CMU_MOD_QTY,
+
+    // TO BE REMOVED
+    HAL_CMU_MOD_P_CODEC = HAL_CMU_MOD_QTY,
+    HAL_CMU_MOD_O_CODEC_DA = HAL_CMU_MOD_QTY,
+    HAL_CMU_MOD_O_CODEC_AD = HAL_CMU_MOD_QTY,
 };
 
 enum HAL_CMU_CLOCK_OUT_ID_T {
     HAL_CMU_CLOCK_OUT_AON_32K           = 0x00,
-    HAL_CMU_CLOCK_OUT_AON_OSC           = 0x01,
-    HAL_CMU_CLOCK_OUT_AON_OSCX2         = 0x02,
-    HAL_CMU_CLOCK_OUT_AON_DIG_OSCX2     = 0x03,
-    HAL_CMU_CLOCK_OUT_AON_DIG_OSCX4     = 0x04,
+    HAL_CMU_CLOCK_OUT_AON_26M           = 0x01,
+    HAL_CMU_CLOCK_OUT_AON_52M           = 0x02,
+    HAL_CMU_CLOCK_OUT_AON_DIG_52M       = 0x03,
+    HAL_CMU_CLOCK_OUT_AON_DIG_104M      = 0x04,
     HAL_CMU_CLOCK_OUT_AON_PER           = 0x05,
     HAL_CMU_CLOCK_OUT_AON_USB           = 0x06,
-    HAL_CMU_CLOCK_OUT_AON_DCDC0         = 0x07,
+    HAL_CMU_CLOCK_OUT_AON_DCDC          = 0x07,
     HAL_CMU_CLOCK_OUT_AON_CHCLK         = 0x08,
     HAL_CMU_CLOCK_OUT_AON_SPDIF0        = 0x09,
     HAL_CMU_CLOCK_OUT_AON_MCU           = 0x0A,
     HAL_CMU_CLOCK_OUT_AON_FLASH         = 0x0B,
-    HAL_CMU_CLOCK_OUT_AON_SYS           = 0x17,
-
-    HAL_CMU_CLOCK_OUT_BT_NONE           = 0x40,
-    HAL_CMU_CLOCK_OUT_BT_32K            = 0x41,
-    HAL_CMU_CLOCK_OUT_BT_SYS            = 0x42,
-    HAL_CMU_CLOCK_OUT_BT_OSCX2          = 0x43,
-    HAL_CMU_CLOCK_OUT_BT_OSC_2          = 0x44,
-    HAL_CMU_CLOCK_OUT_BT_ADC            = 0x45,
-    HAL_CMU_CLOCK_OUT_BT_ADCD3          = 0x46,
-    HAL_CMU_CLOCK_OUT_BT_DAC            = 0x47,
-    HAL_CMU_CLOCK_OUT_BT_DACD2          = 0x48,
-    HAL_CMU_CLOCK_OUT_BT_DACD4          = 0x49,
+    HAL_CMU_CLOCK_OUT_AON_SYS           = 0x0C,
+
+    HAL_CMU_CLOCK_OUT_BT_32K            = 0x40,
+    HAL_CMU_CLOCK_OUT_BT_SYS            = 0x41,
+    HAL_CMU_CLOCK_OUT_BT_52M            = 0x42,
+    HAL_CMU_CLOCK_OUT_BT_26MI           = 0x43,
+    HAL_CMU_CLOCK_OUT_BT_13M            = 0x44,
+    HAL_CMU_CLOCK_OUT_BT_12M            = 0x45,
+    HAL_CMU_CLOCK_OUT_BT_ADC            = 0x46,
+    HAL_CMU_CLOCK_OUT_BT_ADC2           = 0x47,
+    HAL_CMU_CLOCK_OUT_BT_24M            = 0x48,
+    HAL_CMU_CLOCK_OUT_BT_26M            = 0x49,
 
     HAL_CMU_CLOCK_OUT_MCU_32K           = 0x60,
     HAL_CMU_CLOCK_OUT_MCU_SYS           = 0x61,
     HAL_CMU_CLOCK_OUT_MCU_FLASH         = 0x62,
     HAL_CMU_CLOCK_OUT_MCU_USB           = 0x63,
     HAL_CMU_CLOCK_OUT_MCU_PCLK          = 0x64,
-    HAL_CMU_CLOCK_OUT_MCU_I2S0          = 0x65,
+    HAL_CMU_CLOCK_OUT_MCU_I2S           = 0x65,
     HAL_CMU_CLOCK_OUT_MCU_PCM           = 0x66,
     HAL_CMU_CLOCK_OUT_MCU_SPDIF0        = 0x67,
     HAL_CMU_CLOCK_OUT_MCU_SDMMC         = 0x68,
@@ -203,9 +197,8 @@ enum HAL_CMU_CLOCK_OUT_ID_T {
     HAL_CMU_CLOCK_OUT_CODEC_ADC_ANA     = 0x80,
     HAL_CMU_CLOCK_OUT_CODEC_CODEC       = 0x81,
     HAL_CMU_CLOCK_OUT_CODEC_IIR         = 0x82,
-    HAL_CMU_CLOCK_OUT_CODEC_RS_DAC      = 0x83,
-    HAL_CMU_CLOCK_OUT_CODEC_RS_ADC      = 0x84,
-    HAL_CMU_CLOCK_OUT_CODEC_HCLK        = 0x85,
+    HAL_CMU_CLOCK_OUT_CODEC_RS          = 0x83,
+    HAL_CMU_CLOCK_OUT_CODEC_HCLK        = 0x84,
 };
 
 enum HAL_CMU_I2S_MCLK_ID_T {
@@ -227,17 +220,31 @@ enum HAL_I2S_ID_T {
 };
 #define HAL_I2S_ID_T                        HAL_I2S_ID_T
 
+enum HAL_CMU_ANC_CLK_USER_T {
+    HAL_CMU_ANC_CLK_USER_ANC,
 
+    HAL_CMU_ANC_CLK_USER_QTY
 };
 
+enum HAL_CMU_LOW_SYS_FREQ_T {
+    HAL_CMU_LOW_SYS_FREQ_NONE,
+    HAL_CMU_LOW_SYS_FREQ_13M,
+    HAL_CMU_LOW_SYS_FREQ_6P5M,
+    HAL_CMU_LOW_SYS_FREQ_4P33M,
+    HAL_CMU_LOW_SYS_FREQ_3P25M,
 };
 
+void hal_cmu_low_sys_clock_set(enum HAL_CMU_LOW_SYS_FREQ_T freq);
 
 int hal_cmu_fast_timer_offline(void);
 
+void hal_cmu_anc_enable(enum HAL_CMU_ANC_CLK_USER_T user);
 
+void hal_cmu_anc_disable(enum HAL_CMU_ANC_CLK_USER_T user);
 
+int hal_cmu_anc_get_status(enum HAL_CMU_ANC_CLK_USER_T user);
 
+void hal_cmu_codec_vad_clock_enable(uint32_t enabled);
 
 uint32_t hal_cmu_get_aon_chip_id(void);

platform/hal/best2300p/hal_dmacfg_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/hal_dmacfg_best2300p.h bes/platform/hal/best2300p/hal_dmacfg_best2300p.h
index 08ff5d483fd..3d2a4f69968 100644
--- a/platform/hal/best2300p/hal_dmacfg_best2300p.h
+++ b/platform/hal/best2300p/hal_dmacfg_best2300p.h
@@ -24,118 +24,90 @@
 #define AUDMA_CHAN_START                        (0)
 #define GPDMA_CHAN_START                        (0)
 
-static const uint32_t gpdma_fifo_addr[AUDMA_PERIPH_NUM] = {
+static const uint32_t audma_fifo_addr[AUDMA_PERIPH_NUM] = {
     CODEC_BASE + 0x01C,     // CODEC RX
     CODEC_BASE + 0x01C,     // CODEC TX
+#ifdef CODEC_DSD
     CODEC_BASE + 0x034,     // DSD RX
     CODEC_BASE + 0x034,     // DSD TX
-    CODEC_BASE + 0x058,     // CODEC TX2
-#ifdef AF_DEVICE_I2S
-    I2S1_BASE + 0x200,      // I2S0 RX
-    I2S1_BASE + 0x240,      // I2S0 TX
-    I2S0_BASE + 0x200,      // I2S0 RX
-    I2S0_BASE + 0x240,      // I2S0 TX
 #else
-    I2C1_BASE + 0x010,      // I2C1 RX
-    I2C1_BASE + 0x010,      // I2C1 TX
-    SPI_BASE + 0x008,       // SPI RX
-    SPI_BASE + 0x008,       // SPI TX
-#endif
-    SDMMC_BASE + 0x200,     // SDMMC
     BTPCM_BASE + 0x1C0,     // BTPCM RX
     BTPCM_BASE + 0x1C8,     // BTPCM TX
-    UART2_BASE + 0x000,     // UART2 RX
-    UART2_BASE + 0x000,     // UART2 TX
-    UART1_BASE + 0x000,     // UART1 RX
-    UART1_BASE + 0x000,     // UART1 TX
+#endif
+    I2S0_BASE + 0x200,      // I2S0 RX
+    I2S0_BASE + 0x240,      // I2S0 TX
+    0,                      // FIR RX
+    0,                      // FIR TX
+    SPDIF0_BASE + 0x1C0,    // SPDIF0 RX
+    SPDIF0_BASE + 0x1C8,    // SPDIF0 TX
+    CODEC_BASE + 0x03C,     // IIR RX
+    CODEC_BASE + 0x03C,     // IIR TX
+    BTDUMP_BASE + 0x34,     // BTDUMP
+    CODEC_BASE + 0x038,     // MC RX
+    I2S1_BASE + 0x200,      // I2S1 RX
+    I2S1_BASE + 0x240,      // I2S1 TX
 };
 
-static const enum HAL_DMA_PERIPH_T gpdma_fifo_periph[AUDMA_PERIPH_NUM] = {
+static const enum HAL_DMA_PERIPH_T audma_fifo_periph[AUDMA_PERIPH_NUM] = {
     HAL_AUDMA_CODEC_RX,
     HAL_AUDMA_CODEC_TX,
+#ifdef CODEC_DSD
     HAL_AUDMA_DSD_RX,
     HAL_AUDMA_DSD_TX,
-    HAL_DMA_PERIPH_NULL,
-#ifdef AF_DEVICE_I2S
+#else
+    HAL_AUDMA_BTPCM_RX,
+    HAL_AUDMA_BTPCM_TX,
+#endif
     HAL_AUDMA_I2S0_RX,
     HAL_AUDMA_I2S0_TX,
+    HAL_AUDMA_FIR_RX,
+    HAL_AUDMA_FIR_TX,
+    HAL_AUDMA_SPDIF0_RX,
+    HAL_AUDMA_SPDIF0_TX,
+    HAL_AUDMA_IIR_RX,
+    HAL_AUDMA_IIR_TX,
+    HAL_AUDMA_BTDUMP,
+    HAL_AUDMA_MC_RX,
     HAL_AUDMA_I2S1_RX,
     HAL_AUDMA_I2S1_TX,
-#else
-    HAL_GPDMA_I2C1_RX,
-    HAL_GPDMA_I2C1_TX,
-    HAL_GPDMA_SPI_RX,
-    HAL_GPDMA_SPI_TX,
-#endif
-    HAL_GPDMA_SDMMC,
-    HAL_AUDMA_BTPCM_RX,
-    HAL_AUDMA_BTPCM_TX,
-    HAL_GPDMA_UART2_RX,
-    HAL_GPDMA_UART2_TX,
-    HAL_GPDMA_UART1_RX,
-    HAL_GPDMA_UART1_TX,
 };
 
-static const uint32_t audma_fifo_addr[GPDMA_PERIPH_NUM] = {
-    CODEC_BASE + 0x01C,     // CODEC RX
-    CODEC_BASE + 0x01C,     // CODEC TX
-    IRDA_BASE + 0x000,      // IR RX
-    IRDA_BASE + 0x004,      // IR TX
-    UART0_BASE + 0x000,     // UART0 RX
-    UART0_BASE + 0x000,     // UART0 TX
-    UART2_BASE + 0x000,     // UART2 RX
-    UART2_BASE + 0x000,     // UART2 TX
-#ifndef SPILCD_DMA_ENABLE
-    BTDUMP_BASE + 0x34,     // BTDUMP
-    0,                      // NULL
-#else
+static const uint32_t gpdma_fifo_addr[GPDMA_PERIPH_NUM] = {
+    FLASH_CTRL_BASE + 0x008, // FLASH CTRL
+    SDMMC_BASE + 0x200,     // SDMMC
+    I2C0_BASE + 0x010,      // I2C0 RX
+    I2C0_BASE + 0x010,      // I2C0 TX
+    SPI_BASE + 0x008,       // SPI RX
+    SPI_BASE + 0x008,       // SPI TX
     SPILCD_BASE + 0x008,    // SPILCD RX
     SPILCD_BASE + 0x008,    // SPILCD TX
-#endif
-#ifdef AF_DEVICE_I2S
-    I2S0_BASE + 0x200,      // I2S0 RX
-    I2S0_BASE + 0x240,      // I2S0 TX
-    I2S1_BASE + 0x200,      // I2S1 RX
-    I2S1_BASE + 0x240,      // I2S1 TX
-#else
-    BTPCM_BASE + 0x1C0,     // BTPCM RX
-    BTPCM_BASE + 0x1C8,     // BTPCM TX
+    UART0_BASE + 0x000,     // UART0 RX
+    UART0_BASE + 0x000,     // UART0 TX
     UART1_BASE + 0x000,     // UART1 RX
     UART1_BASE + 0x000,     // UART1 TX
-#endif
-    FLASH_CTRL_BASE + 0x008,// FLASH0
-    FLASH1_CTRL_BASE + 0x008,// FLASH0
+    I2C1_BASE + 0x010,      // I2C1 RX
+    I2C1_BASE + 0x010,      // I2C1 TX
+    UART2_BASE + 0x000,     // UART2 RX
+    UART2_BASE + 0x000,     // UART2 TX
 };
 
-static const enum HAL_DMA_PERIPH_T audma_fifo_periph[GPDMA_PERIPH_NUM] = {
-    HAL_AUDMA_CODEC_RX,
-    HAL_AUDMA_CODEC_TX,
-    HAL_GPDMA_IR_RX,
-    HAL_GPDMA_IR_TX,
-    HAL_GPDMA_UART0_RX,
-    HAL_GPDMA_UART0_TX,
-    HAL_GPDMA_UART2_RX,
-    HAL_GPDMA_UART2_TX,
-#ifndef SPILCD_DMA_ENABLE
-    HAL_AUDMA_BTDUMP,
-    HAL_DMA_PERIPH_NULL,
-#else
+static const enum HAL_DMA_PERIPH_T gpdma_fifo_periph[GPDMA_PERIPH_NUM] = {
+    HAL_GPDMA_FLASH_TX,
+    HAL_GPDMA_SDMMC,
+    HAL_GPDMA_I2C0_RX,
+    HAL_GPDMA_I2C0_TX,
+    HAL_GPDMA_SPI_RX,
+    HAL_GPDMA_SPI_TX,
     HAL_GPDMA_SPILCD_RX,
     HAL_GPDMA_SPILCD_TX,
-#endif
-#ifdef AF_DEVICE_I2S
-    HAL_AUDMA_I2S0_RX,      // I2S0 RX
-    HAL_AUDMA_I2S0_TX,      // I2S0 TX
-    HAL_AUDMA_I2S1_RX,
-    HAL_AUDMA_I2S1_TX,
-#else
-    HAL_AUDMA_BTPCM_RX,
-    HAL_AUDMA_BTPCM_TX,
+    HAL_GPDMA_UART0_RX,
+    HAL_GPDMA_UART0_TX,
     HAL_GPDMA_UART1_RX,
     HAL_GPDMA_UART1_TX,
-#endif
-    HAL_GPDMA_FLASH0,
-    HAL_GPDMA_FLASH1,
+    HAL_GPDMA_I2C1_RX,
+    HAL_GPDMA_I2C1_TX,
+    HAL_GPDMA_UART2_RX,
+    HAL_GPDMA_UART2_TX,
 };
 
 #endif

platform/hal/best2300p/hal_iomux_best2300p.c

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/hal_iomux_best2300p.c bes/platform/hal/best2300p/hal_iomux_best2300p.c
index c0961dcc167..097f3da6b96 100644
--- a/platform/hal/best2300p/hal_iomux_best2300p.c
+++ b/platform/hal/best2300p/hal_iomux_best2300p.c
@@ -28,6 +28,11 @@
 #define I2S0_VOLTAGE_SEL                    HAL_IOMUX_PIN_VOLTAGE_VIO
 #endif
 
+#ifdef I2S1_VOLTAGE_VMEM
+#define I2S1_VOLTAGE_SEL                    HAL_IOMUX_PIN_VOLTAGE_MEM
+#else
+#define I2S1_VOLTAGE_SEL                    HAL_IOMUX_PIN_VOLTAGE_VIO
+#endif
 
 #ifdef SPDIF0_VOLTAGE_VMEM
 #define SPDIF0_VOLTAGE_SEL                  HAL_IOMUX_PIN_VOLTAGE_MEM
@@ -71,19 +76,28 @@
 #define CLKOUT_VOLTAGE_SEL                  HAL_IOMUX_PIN_VOLTAGE_VIO
 #endif
 
+#ifndef I2S0_IOMUX_INDEX
+#define I2S0_IOMUX_INDEX                    0
+#endif
 
+#ifndef I2S1_IOMUX_INDEX
+#define I2S1_IOMUX_INDEX                    0
+#endif
 
 #ifndef I2S_MCLK_IOMUX_INDEX
-#define I2S_MCLK_IOMUX_INDEX                04
+#define I2S_MCLK_IOMUX_INDEX                0
 #endif
 
+#ifndef SPDIF0_IOMUX_INDEX
+#define SPDIF0_IOMUX_INDEX                  0
+#endif
 
-#ifndef SPDIF0_I_IOMUX_INDEX
-#define SPDIF0_I_IOMUX_INDEX                02
+#ifndef DIG_MIC2_CK_IOMUX_INDEX
+#define DIG_MIC2_CK_IOMUX_INDEX             0
 #endif
 
-#ifndef SPDIF0_O_IOMUX_INDEX
-#define SPDIF0_O_IOMUX_INDEX                03
+#ifndef DIG_MIC3_CK_IOMUX_INDEX
+#define DIG_MIC3_CK_IOMUX_INDEX             0
 #endif
 
 #ifndef DIG_MIC_CK_IOMUX_PIN
@@ -103,7 +117,7 @@
 #endif
 
 #ifndef SPI_IOMUX_INDEX
-#define SPI_IOMUX_INDEX                    04
+#define SPI_IOMUX_INDEX                     0
 #endif
 
 #ifndef SPILCD_IOMUX_INDEX
@@ -111,157 +125,121 @@
 #endif
 
 #ifndef I2C0_IOMUX_INDEX
-#define I2C0_IOMUX_INDEX                    4
+#define I2C0_IOMUX_INDEX                    0
 #endif
 
 #ifndef I2C1_IOMUX_INDEX
-#define I2C1_IOMUX_INDEX                    22
+#define I2C1_IOMUX_INDEX                    0
 #endif
 
 #ifndef CLKOUT_IOMUX_INDEX
-#define CLKOUT_IOMUX_INDEX                  20
+#define CLKOUT_IOMUX_INDEX                  0
 #endif
 
-#define IOMUX_FUNC_VAL_GPIO                 15
+#define IOMUX_FUNC_VAL_GPIO                 0
 
-#define IOMUX_ALT_FUNC_NUM                  11
+#define IOMUX_ALT_FUNC_NUM                  6
 
-// Other func values: 2 -> uart rtx/ctx, 12 -> btdm, 13 -> wf_fem, 14 -> tport, 15 -> gpio
-static const uint8_t index_to_func_val[IOMUX_ALT_FUNC_NUM] = {
-    0,  1,  3,  4,
-    5,  6,  7,  8,
-    9,  10, 11
-};
+// Other func values: 0 -> gpio, 6 -> rf_ana, 7 -> jtag/btdm, 9 -> clk_req, 10 -> ana_test
+static const uint8_t index_to_func_val[IOMUX_ALT_FUNC_NUM] = { 1, 2, 3, 4, 5, 8, };
 
 static const enum HAL_IOMUX_FUNCTION_T pin_func_map[HAL_IOMUX_PIN_NUM][IOMUX_ALT_FUNC_NUM] = {
     // P0_0
-    { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
-      HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_I2S0_SDI0, },
+    { HAL_IOMUX_FUNC_I2S0_SDI0, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_PCM_DI, HAL_IOMUX_FUNC_SPILCD_DI0,
+      HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_SPILCD_DCN, },
     // P0_1
-    { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
-      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDO0, },
+    { HAL_IOMUX_FUNC_I2S0_SDO, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_PCM_DO, HAL_IOMUX_FUNC_SPILCD_DIO,
+      HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_NONE, },
     // P0_2
-    { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
-      HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_BL_EN,
-      HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_WS, },
+    { HAL_IOMUX_FUNC_I2S0_WS, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_PCM_FSYNC, HAL_IOMUX_FUNC_SPILCD_CS0,
+      HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_NONE, },
     // P0_3
-    { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
-      HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_BL_PWM,
-      HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SCK, },
+    { HAL_IOMUX_FUNC_I2S0_SCK, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_PCM_CLK, HAL_IOMUX_FUNC_SPILCD_CLK,
+      HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_NONE, },
     // P0_4
-    { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPI_DI0,
-      HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPI_DCN,
-      HAL_IOMUX_FUNC_SDMMC_DATA7, HAL_IOMUX_FUNC_PDM1_CK, HAL_IOMUX_FUNC_I2S0_SDO3, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA7, HAL_IOMUX_FUNC_SPI_DI0, HAL_IOMUX_FUNC_I2S0_MCLK, HAL_IOMUX_FUNC_CLK_OUT,
+      HAL_IOMUX_FUNC_PDM1_CK, HAL_IOMUX_FUNC_SPI_DCN, },
     // P0_5
-    { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPI_CLK,
-      HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_DISPLAY_TE,
-      HAL_IOMUX_FUNC_SDMMC_DATA6, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDO2, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA6, HAL_IOMUX_FUNC_SPI_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_CS1,
+      HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_NONE, },
     // P0_6
-    { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPI_CS0,
-      HAL_IOMUX_FUNC_SPILCD_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_CS, HAL_IOMUX_FUNC_WF_WAKE_HOST, HAL_IOMUX_FUNC_IR_RX,
-      HAL_IOMUX_FUNC_SDMMC_DATA5, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_SDO1, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA5, HAL_IOMUX_FUNC_SPI_CS0, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_CS2,
+      HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_NONE, },
     // P0_7
-    { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPI_DIO,
-      HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DIO, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_IR_TX,
-      HAL_IOMUX_FUNC_SDMMC_DATA4, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SDO0, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA4, HAL_IOMUX_FUNC_SPI_DIO, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_CS3,
+      HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_NONE, },
     // P1_0
-    { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CLK,
-      HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_DO1_DCN, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_WF_SDIO_CLK,
-      HAL_IOMUX_FUNC_SDMMC_DATA2, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S0_SDI3, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA2, HAL_IOMUX_FUNC_I2S1_SCK, HAL_IOMUX_FUNC_SPILCD_CLK, HAL_IOMUX_FUNC_SPI_CS1,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P1_1
-    { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_CS0,
-      HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_DO2, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_WF_SDIO_CMD,
-      HAL_IOMUX_FUNC_SDMMC_DATA3, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S0_SDI2, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA3, HAL_IOMUX_FUNC_I2S1_WS, HAL_IOMUX_FUNC_SPILCD_CS0, HAL_IOMUX_FUNC_SPI_CS2,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P1_2
-    { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CS1,
-      HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO3, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_WF_SDIO_DATA0,
-      HAL_IOMUX_FUNC_SDMMC_CMD, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_I2S0_SDI1, },
+    { HAL_IOMUX_FUNC_SDMMC_CMD, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_SPI_CS3,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P1_3
-    { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_DCN,
-      HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_SDIO_DATA1,
-      HAL_IOMUX_FUNC_SDMMC_CLK, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_I2S0_SDI0, },
+    { HAL_IOMUX_FUNC_SDMMC_CLK, HAL_IOMUX_FUNC_I2S0_MCLK, HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_CLK_OUT,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P1_4
-    { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
-      HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_DISPLAY_SPI_DI, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_WF_SDIO_DATA2,
-      HAL_IOMUX_FUNC_SDMMC_DATA0, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_DISPLAY_TE, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA0, HAL_IOMUX_FUNC_I2S1_SDI0, HAL_IOMUX_FUNC_SPILCD_DI0, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P1_5
-    { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
-      HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_SDIO_DATA3,
-      HAL_IOMUX_FUNC_SDMMC_DATA1, HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_DISPLAY_TE, },
+    { HAL_IOMUX_FUNC_SDMMC_DATA1, HAL_IOMUX_FUNC_I2S1_SDO, HAL_IOMUX_FUNC_SPILCD_DIO, HAL_IOMUX_FUNC_I2S0_MCLK,
+      HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_NONE, },
     // P1_6
-    { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART0_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_WF_WAKE_HOST,
-      HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
+    { HAL_IOMUX_FUNC_UART0_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P1_7
-    { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART0_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
+    { HAL_IOMUX_FUNC_UART0_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P2_0
-    { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
-      HAL_IOMUX_FUNC_SPILCD_DCN, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_RX,
-      HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S1_SDI0, },
+    { HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_BT_UART_RX, HAL_IOMUX_FUNC_SPDIF0_DI,
+      HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_I2S0_MCLK, },
     // P2_1
-    { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
-      HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_TX,
-      HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S1_SDO0, },
+    { HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_BT_UART_TX, HAL_IOMUX_FUNC_SPDIF0_DO,
+      HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_CLK_OUT, },
     // P2_2
-    { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
-      HAL_IOMUX_FUNC_DISPLAY_BL_EN, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_WF_UART_CTS,
-      HAL_IOMUX_FUNC_BT_UART_CTS, HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_I2S1_WS, },
+    { HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_UART1_CTS, HAL_IOMUX_FUNC_BT_UART_CTS,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S0_MCLK, },
     // P2_3
-    { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
-      HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_DISPLAY_BL_PWM, HAL_IOMUX_FUNC_PCM_DI, HAL_IOMUX_FUNC_WF_UART_RTS,
-      HAL_IOMUX_FUNC_BT_UART_RTS, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_I2S1_SCK, },
+    { HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_UART1_RTS, HAL_IOMUX_FUNC_BT_UART_RTS,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_CLK_OUT, },
     // P2_4
-    { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPI_DI0,
-      HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_PCM_DO, HAL_IOMUX_FUNC_SPDIF0_DI,
-      HAL_IOMUX_FUNC_WF_SDIO_CLK, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S1_SDO3, },
+    { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_CLK_REQ_OUT, HAL_IOMUX_FUNC_SPI_DI3, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P2_5
-    { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPI_DIO,
-      HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_PCM_FSYNC, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_WF_SDIO_CMD, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_I2S1_SDO2, },
+    { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_CLK_REQ_IN, HAL_IOMUX_FUNC_SPI_CS3, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P2_6
-    { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPI_CS0,
-      HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_PCM_CLK, HAL_IOMUX_FUNC_IR_RX,
-      HAL_IOMUX_FUNC_WF_SDIO_DATA0, HAL_IOMUX_FUNC_SPDIF0_DI, HAL_IOMUX_FUNC_I2S1_SDO1, },
+    { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_SPILCD_DI1, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPDIF0_DI,
+      HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_NONE, },
     // P2_7
-    { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPI_CLK,
-      HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_I2S_MCLK, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_IR_TX,
-      HAL_IOMUX_FUNC_WF_SDIO_DATA1, HAL_IOMUX_FUNC_SPDIF0_DO, HAL_IOMUX_FUNC_I2S1_SDO0, },
+    { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPDIF0_DO,
+      HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_NONE, },
     // P3_0
-    { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M1_SCL, HAL_IOMUX_FUNC_SPI_DI0,
-      HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_SPI_DCN, HAL_IOMUX_FUNC_WF_UART_RX, HAL_IOMUX_FUNC_SPILCD_CS1,
-      HAL_IOMUX_FUNC_WF_SDIO_DATA2, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S1_SDI3, },
+    { HAL_IOMUX_FUNC_SPILCD_DI2, HAL_IOMUX_FUNC_I2S1_SCK, HAL_IOMUX_FUNC_SPILCD_CS1, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_NONE, },
     // P3_1
-    { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M1_SDA, HAL_IOMUX_FUNC_SPI_DIO,
-      HAL_IOMUX_FUNC_WF_SDIO_DATA0, HAL_IOMUX_FUNC_DISPLAY_SPI_DI, HAL_IOMUX_FUNC_WF_UART_TX, HAL_IOMUX_FUNC_IR_RX,
-      HAL_IOMUX_FUNC_WF_SDIO_DATA3, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S1_SDI2, },
+    { HAL_IOMUX_FUNC_SPILCD_CS2, HAL_IOMUX_FUNC_I2S1_WS, HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_NONE, },
     // P3_2
-    { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_UART1_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPI_CS0,
-      HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO3, HAL_IOMUX_FUNC_WF_UART_CTS, HAL_IOMUX_FUNC_IR_TX,
-      HAL_IOMUX_FUNC_WF_WAKE_HOST, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S1_SDI1, },
+    { HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_I2S1_SDI0, HAL_IOMUX_FUNC_SPILCD_CS3, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_NONE, },
     // P3_3
-    { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_UART1_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPI_CLK,
-      HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_DISPLAY_SPI_DO2, HAL_IOMUX_FUNC_WF_UART_RTS, HAL_IOMUX_FUNC_SPILCD_DCN,
-      HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM2_CK, HAL_IOMUX_FUNC_I2S1_SDI0, },
+    { HAL_IOMUX_FUNC_SPILCD_DI3, HAL_IOMUX_FUNC_I2S1_SDO, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE,
+      HAL_IOMUX_FUNC_PDM2_CK, HAL_IOMUX_FUNC_NONE, },
     // P3_4
-    { HAL_IOMUX_FUNC_PWM4, HAL_IOMUX_FUNC_UART3_RX, HAL_IOMUX_FUNC_I2C_M0_SCL, HAL_IOMUX_FUNC_SPILCD_DI0,
-      HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_DISPLAY_SPI_DO1_DCN, HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPILCD_DCN,
-      HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM0_CK, HAL_IOMUX_FUNC_I2S0_SDI3, },
+    { HAL_IOMUX_FUNC_PWM0, HAL_IOMUX_FUNC_SPI_DI1, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_DI0,
+      HAL_IOMUX_FUNC_CLK_OUT, HAL_IOMUX_FUNC_SPILCD_DCN, },
     // P3_5
-    { HAL_IOMUX_FUNC_PWM5, HAL_IOMUX_FUNC_UART3_TX, HAL_IOMUX_FUNC_I2C_M0_SDA, HAL_IOMUX_FUNC_SPILCD_DIO,
-      HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_DISPLAY_SPI_DIO, HAL_IOMUX_FUNC_CLK_32K_IN, HAL_IOMUX_FUNC_NONE,
-      HAL_IOMUX_FUNC_DISPLAY_TE, HAL_IOMUX_FUNC_PDM0_D, HAL_IOMUX_FUNC_I2S0_SDI2, },
+    { HAL_IOMUX_FUNC_PWM1, HAL_IOMUX_FUNC_SPI_CS1, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_DIO,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P3_6
-    { HAL_IOMUX_FUNC_PWM6, HAL_IOMUX_FUNC_UART2_RX, HAL_IOMUX_FUNC_I2C_M2_SCL, HAL_IOMUX_FUNC_SPILCD_CS0,
-      HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_DISPLAY_SPI_CS, HAL_IOMUX_FUNC_CLK_REQ_OUT, HAL_IOMUX_FUNC_SPDIF0_DI,
-      HAL_IOMUX_FUNC_IR_RX, HAL_IOMUX_FUNC_PDM1_D, HAL_IOMUX_FUNC_I2S0_SDI1, },
+    { HAL_IOMUX_FUNC_PWM2, HAL_IOMUX_FUNC_SPI_DI2, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_CS0,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
     // P3_7
-    { HAL_IOMUX_FUNC_PWM7, HAL_IOMUX_FUNC_UART2_TX, HAL_IOMUX_FUNC_I2C_M2_SDA, HAL_IOMUX_FUNC_SPILCD_CLK,
-      HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_DISPLAY_SPI_CLK, HAL_IOMUX_FUNC_CLK_REQ_IN, HAL_IOMUX_FUNC_SPDIF0_DO,
-      HAL_IOMUX_FUNC_IR_TX, HAL_IOMUX_FUNC_PDM2_D, HAL_IOMUX_FUNC_I2S0_SDI0, },
+    { HAL_IOMUX_FUNC_PWM3, HAL_IOMUX_FUNC_SPI_CS2, HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_SPILCD_CLK,
+      HAL_IOMUX_FUNC_NONE, HAL_IOMUX_FUNC_NONE, },
 };
 
 static struct IOMUX_T * const iomux = (struct IOMUX_T *)IOMUX_BASE;
@@ -278,6 +256,9 @@ static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d0_pin = DIG_MIC_D0_IOMUX_PIN;
 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d1_pin = DIG_MIC_D1_IOMUX_PIN;
 static OPT_TYPE enum HAL_IOMUX_PIN_T digmic_d2_pin = DIG_MIC_D2_IOMUX_PIN;
 
+static enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T BOOT_DATA_LOC uart0_volt = HAL_IOMUX_PIN_VOLTAGE_VIO;
+// UART1 is tied to vmem domain
+
 void hal_iomux_set_default_config(void)
 {
     uint32_t i;
@@ -335,6 +316,28 @@ uint32_t hal_iomux_init(const struct HAL_IOMUX_PIN_FUNCTION_MAP *map, uint32_t c
     return 0;
 }
 
+#ifdef ANC_PROD_TEST
+void hal_iomux_set_dig_mic_clock_pin(enum HAL_IOMUX_PIN_T pin)
+{
+    digmic_ck_pin = pin;
+}
+void hal_iomux_set_dig_mic_data0_pin(enum HAL_IOMUX_PIN_T pin)
+{
+    digmic_d0_pin = pin;
+}
+
+void hal_iomux_set_dig_mic_data1_pin(enum HAL_IOMUX_PIN_T pin)
+{
+    digmic_d1_pin = pin;
+}
+
+void hal_iomux_set_dig_mic_data2_pin(enum HAL_IOMUX_PIN_T pin)
+{
+    digmic_d2_pin = pin;
+}
+#endif
+
+
 uint32_t hal_iomux_set_function(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_FUNCTION_T func, enum HAL_IOMUX_OP_TYPE_T type)
 {
     int i;
@@ -350,7 +353,7 @@ uint32_t hal_iomux_set_function(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_FUNCTIO
     }
 
     if (pin == HAL_IOMUX_PIN_P1_6 || pin == HAL_IOMUX_PIN_P1_7) {
-        if (func ==  HAL_IOMUX_FUNC_I2C_M0_SCL || func == HAL_IOMUX_FUNC_I2C_M0_SDA) {
+        if (func ==  HAL_IOMUX_FUNC_I2C_SCL || func == HAL_IOMUX_FUNC_I2C_SDA) {
             // Enable analog I2C slave
             iomux->REG_050 &= ~IOMUX_GPIO_I2C_MODE;
             // Set mcu GPIO func
@@ -433,7 +436,7 @@ uint32_t hal_iomux_set_io_pull_select(enum HAL_IOMUX_PIN_T pin, enum HAL_IOMUX_P
         return 1;
     }
 
-    if (pin < HAL_IOMUX_PIN_NUM) {
+    if (pin < HAL_IOMUX_PIN_LED1) {
         iomux->REG_02C &= ~(1 << pin);
         iomux->REG_030 &= ~(1 << pin);
         if (pull_sel == HAL_IOMUX_PIN_PULLUP_ENABLE) {
@@ -454,6 +457,7 @@ void hal_iomux_set_sdmmc_dt_n_out_group(int enable)
 
 void hal_iomux_set_uart0_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
 {
+    uart0_volt = volt;
 }
 
 void hal_iomux_set_uart1_voltage(enum HAL_IOMUX_PIN_VOLTAGE_DOMAINS_T volt)
@@ -478,6 +482,12 @@ bool hal_iomux_uart0_connected(void)
     iomux->REG_008 = SET_BITFIELD(iomux->REG_008, IOMUX_GPIO_P16_SEL, IOMUX_FUNC_VAL_GPIO);
 
     mask = (1 << HAL_IOMUX_PIN_P1_6);
+    // Set voltage domain
+    if (uart0_volt == HAL_IOMUX_PIN_VOLTAGE_VIO) {
+        iomux->REG_070 |= (1 << (IOMUX_GPIO_P1_PWS_SHIFT + 1));
+    } else {
+        iomux->REG_070 &= ~(1 << (IOMUX_GPIO_P1_PWS_SHIFT + 1));
+    }
     // Clear pullup
     iomux->REG_02C &= ~mask;
     // Setup pulldown
@@ -547,6 +557,12 @@ void hal_iomux_set_uart0(void)
         IOMUX_GPIO_P16_SEL(1) | IOMUX_GPIO_P17_SEL(1);
 
     mask = (1 << HAL_IOMUX_PIN_P1_6) | (1 << HAL_IOMUX_PIN_P1_7);
+    // Set voltage domain
+    if (uart0_volt == HAL_IOMUX_PIN_VOLTAGE_VIO) {
+        iomux->REG_070 |= (1 << (IOMUX_GPIO_P1_PWS_SHIFT + 1));
+    } else {
+        iomux->REG_070 &= ~(1 << (IOMUX_GPIO_P1_PWS_SHIFT + 1));
+    }
     // Setup pullup
     iomux->REG_02C |= (1 << HAL_IOMUX_PIN_P1_6);
     iomux->REG_02C &= ~(1 << HAL_IOMUX_PIN_P1_7);
@@ -556,20 +572,18 @@ void hal_iomux_set_uart0(void)
 
 void hal_iomux_set_uart1(void)
 {
-    uint32_t mask_pd_c, mask_pu, mask_pu_c;
+    uint32_t mask;
 
     // Set uart1 func
     iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK | IOMUX_GPIO_P21_SEL_MASK)) |
         IOMUX_GPIO_P20_SEL(1) | IOMUX_GPIO_P21_SEL(1);
 
-    mask_pd_c = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
-    mask_pu = (1 << HAL_IOMUX_PIN_P2_0);
-    mask_pu_c = (1 << HAL_IOMUX_PIN_P2_1);
+    mask = (1 << HAL_IOMUX_PIN_P2_0) | (1 << HAL_IOMUX_PIN_P2_1);
     // Setup pullup
-    iomux->REG_02C |= mask_pu;
-    iomux->REG_02C &= ~(mask_pu_c);
+    iomux->REG_02C |= (1 << HAL_IOMUX_PIN_P2_0);
+    iomux->REG_02C &= ~(1 << HAL_IOMUX_PIN_P2_1);
     // Clear pulldown
-    iomux->REG_030 &= ~mask_pd_c;
+    iomux->REG_030 &= ~mask;
 }
 
 void hal_iomux_set_uart2(void)
@@ -584,11 +598,17 @@ void hal_iomux_set_analog_i2c(void)
     iomux->REG_050 |= IOMUX_I2C0_M_SEL_GPIO;
     // Set mcu GPIO func
     iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P16_SEL_MASK | IOMUX_GPIO_P17_SEL_MASK)) |
-        IOMUX_GPIO_P16_SEL(0xF) | IOMUX_GPIO_P17_SEL(0xF);
+        IOMUX_GPIO_P16_SEL(0) | IOMUX_GPIO_P17_SEL(0);
     // Enable analog I2C slave
     iomux->REG_050 &= ~IOMUX_GPIO_I2C_MODE;
 
     mask = (1 << HAL_IOMUX_PIN_P1_6) | (1 << HAL_IOMUX_PIN_P1_7);
+    // Set voltage domain
+    if (uart0_volt == HAL_IOMUX_PIN_VOLTAGE_VIO) {
+        iomux->REG_070 |= (1 << (IOMUX_GPIO_P1_PWS_SHIFT + 1));
+    } else {
+        iomux->REG_070 &= ~(1 << (IOMUX_GPIO_P1_PWS_SHIFT + 1));
+    }
     // Setup pullup
     iomux->REG_02C |= mask;
     // Clear pulldown
@@ -601,27 +621,27 @@ void hal_iomux_set_jtag(void)
     uint32_t val;
 
     // SWCLK/TCK, SWDIO/TMS
-    mask = IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P00_SEL_MASK;
-    val = IOMUX_GPIO_P01_SEL(7) | IOMUX_GPIO_P00_SEL(7);
+    mask = IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P02_SEL_MASK;
+    val = IOMUX_GPIO_P01_SEL(7) | IOMUX_GPIO_P02_SEL(7);
 
     // TDI, TDO
 #ifdef JTAG_TDI_TDO_PIN
-    mask |= IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK;
-    val |= IOMUX_GPIO_P02_SEL(7) | IOMUX_GPIO_P03_SEL(7);
+    mask |= IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK;
+    val |= IOMUX_GPIO_P00_SEL(7) | IOMUX_GPIO_P03_SEL(7);
 #endif
     iomux->REG_004 = (iomux->REG_004 & ~mask) | val;
 
     // RESET
 #if defined(JTAG_RESET_PIN) || defined(JTAG_TDI_TDO_PIN)
-    iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P05_SEL_MASK)) | IOMUX_GPIO_P05_SEL(7);
+    iomux->REG_00C = (iomux->REG_00C & ~(IOMUX_GPIO_P20_SEL_MASK)) | IOMUX_GPIO_P20_SEL(7);
 #endif
 
-    mask = (1 << HAL_IOMUX_PIN_P0_1) | (1 << HAL_IOMUX_PIN_P0_0);
+    mask = (1 << HAL_IOMUX_PIN_P0_1) | (1 << HAL_IOMUX_PIN_P0_2);
 #ifdef JTAG_TDI_TDO_PIN
-    mask |= (1 << HAL_IOMUX_PIN_P0_2) | (1 << HAL_IOMUX_PIN_P0_3);
+    mask |= (1 << HAL_IOMUX_PIN_P0_0) | (1 << HAL_IOMUX_PIN_P0_3);
 #endif
 #if defined(JTAG_RESET_PIN) || defined(JTAG_TDI_TDO_PIN)
-    mask |= (1 << HAL_IOMUX_PIN_P0_5);
+    mask |= (1 << HAL_IOMUX_PIN_P2_0);
 #endif
     // Clear pullup
     iomux->REG_02C &= ~mask;
@@ -658,10 +678,10 @@ void hal_iomux_ispi_access_init(void)
 void hal_iomux_set_i2s0(void)
 {
     static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2s[] = {
+        {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_I2S0_SDO,  I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
         {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_I2S0_WS,   I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
         {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_I2S0_SCK,  I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_I2S0_SDI0, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_I2S0_SDO0,  I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
     };
 
     hal_iomux_init(pinmux_i2s, ARRAY_SIZE(pinmux_i2s));
@@ -670,65 +690,34 @@ void hal_iomux_set_i2s0(void)
 void hal_iomux_set_i2s1(void)
 {
     static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2s[] = {
-        {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S1_WS,   I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_I2S1_SCK,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#if (I2S1_I_IOMUX_INDEX == 20)
-        {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (I2S1_I_IOMUX_INDEX == 33)
-        {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#if (I2S1_IOMUX_INDEX == 30)
+        {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_I2S1_SDO,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_I2S1_WS,   I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_I2S1_SCK,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #else
-#error "Unsupported I2S1_I_IOMUX_INDEX"
-#endif
-#if (I2S1_I1_IOMUX_INDEX == 32)
-        {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_I2S1_SDI1, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-#if (I2S1_I2_IOMUX_INDEX == 31)
-        {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_I2S1_SDI2, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-#if (I2S1_I3_IOMUX_INDEX == 30)
-        {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_I2S1_SDI3, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-
-#if (I2S1_O_IOMUX_INDEX == 21)
-        {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_I2S1_SDO0,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (I2S1_O_IOMUX_INDEX == 27)
-        {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2S1_SDO0,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#else
-#error "Unsupported I2S1_O_IOMUX_INDEX"
-#endif
-#if (I2S1_O1_IOMUX_INDEX == 26)
-        {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_I2S1_SDO1,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-#if (I2S1_O2_IOMUX_INDEX == 25)
-        {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_I2S1_SDO2,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-#if (I2S1_O3_IOMUX_INDEX == 24)
-        {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_I2S1_SDO3,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
+        {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_I2S1_SDI0, I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2S1_SDO,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_I2S1_WS,   I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_I2S1_SCK,  I2S1_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
     };
-
+#endif
     hal_iomux_init(pinmux_i2s, ARRAY_SIZE(pinmux_i2s));
 }
 
 void hal_iomux_set_i2s_mclk(void)
 {
     static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux[] = {
-#if (I2S_MCLK_IOMUX_INDEX == 04)
-        {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (I2S_MCLK_IOMUX_INDEX == 13)
-        {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#if (I2S_MCLK_IOMUX_INDEX == 13)
+        {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_I2S0_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #elif (I2S_MCLK_IOMUX_INDEX == 15)
-        {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_I2S0_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #elif (I2S_MCLK_IOMUX_INDEX == 20)
-        {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2S0_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #elif (I2S_MCLK_IOMUX_INDEX == 22)
-        {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (I2S_MCLK_IOMUX_INDEX == 27)
-        {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (I2S_MCLK_IOMUX_INDEX == 34)
-        {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_I2S_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_I2S0_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #else
-#error "Unsupported I2S_MCLK_IOMUX_INDEX"
+        {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_I2S0_MCLK, I2S0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
     };
 
@@ -738,41 +727,24 @@ void hal_iomux_set_i2s_mclk(void)
 void hal_iomux_set_spdif0(void)
 {
     static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spdif[] = {
-#if (SPDIF0_I_IOMUX_INDEX == 02)
-        {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
-#elif (SPDIF0_I_IOMUX_INDEX == 10)
-        {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
-#elif (SPDIF0_I_IOMUX_INDEX == 20)
+#if (SPDIF0_IOMUX_INDEX == 20)
         {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
-#elif (SPDIF0_I_IOMUX_INDEX == 26)
-        {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
-#elif (SPDIF0_I_IOMUX_INDEX == 37)
-        {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
-#elif (SPDIF0_I_IOMUX_INDEX == 24)
-        {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
-#else
-#error "Unsupported SPDIF0_I_IOMUX_INDEX"
-#endif
-
-#if (SPDIF0_O_IOMUX_INDEX == 03)
-        {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPDIF0_O_IOMUX_INDEX == 11)
-        {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPDIF0_O_IOMUX_INDEX == 21)
         {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPDIF0_O_IOMUX_INDEX == 27)
+#elif (SPDIF0_IOMUX_INDEX == 26)
+        {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
         {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPDIF0_O_IOMUX_INDEX == 37)
-        {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPDIF0_O_IOMUX_INDEX == 07)
-        {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #else
-#error "Unsupported SPDIF0_O_IOMUX_INDEX"
+        {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPDIF0_DI, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
+        {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPDIF0_DO, SPDIF0_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
     };
+
     hal_iomux_init(pinmux_spdif, ARRAY_SIZE(pinmux_spdif));
 }
 
+void hal_iomux_set_spdif1(void)
+{
+}
 
 void hal_iomux_set_dig_mic(uint32_t map)
 {
@@ -798,29 +770,22 @@ void hal_iomux_set_dig_mic(uint32_t map)
     } else if (digmic_ck_pin == HAL_IOMUX_PIN_P3_3) {
         pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P3_3;
         pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM2_CK;
-    } else if (digmic_ck_pin == HAL_IOMUX_PIN_P3_4) {
-        pinmux_digitalmic_clk[0].pin = HAL_IOMUX_PIN_P3_4;
-        pinmux_digitalmic_clk[0].function = HAL_IOMUX_FUNC_PDM0_CK;
     }
 
     if (digmic_d0_pin == HAL_IOMUX_PIN_P0_1) {
         pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_1;
-    } else if (digmic_d0_pin == HAL_IOMUX_PIN_P0_5) {
-        pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_5;
+    } else if (digmic_d0_pin == HAL_IOMUX_PIN_P0_6) {
+        pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P0_6;
     } else if (digmic_d0_pin == HAL_IOMUX_PIN_P3_0) {
         pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P3_0;
-    } else if (digmic_d0_pin == HAL_IOMUX_PIN_P3_5) {
-        pinmux_digitalmic0[0].pin = HAL_IOMUX_PIN_P3_5;
     }
 
     if (digmic_d1_pin == HAL_IOMUX_PIN_P0_2) {
         pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_2;
-    } else if (digmic_d1_pin == HAL_IOMUX_PIN_P0_6) {
-        pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_6;
+    } else if (digmic_d1_pin == HAL_IOMUX_PIN_P0_5) {
+        pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P0_5;
     } else if (digmic_d1_pin == HAL_IOMUX_PIN_P3_1) {
         pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P3_1;
-    } else if (digmic_d1_pin == HAL_IOMUX_PIN_P3_6) {
-        pinmux_digitalmic1[0].pin = HAL_IOMUX_PIN_P3_6;
     }
 
     if (digmic_d2_pin == HAL_IOMUX_PIN_P0_3) {
@@ -829,8 +794,6 @@ void hal_iomux_set_dig_mic(uint32_t map)
         pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P0_7;
     } else if (digmic_d2_pin == HAL_IOMUX_PIN_P3_2) {
         pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P3_2;
-    } else if (digmic_d2_pin == HAL_IOMUX_PIN_P3_7) {
-        pinmux_digitalmic2[0].pin = HAL_IOMUX_PIN_P3_7;
     }
 
     if ((map & 0xF) == 0) {
@@ -850,163 +813,140 @@ void hal_iomux_set_dig_mic(uint32_t map)
 
 void hal_iomux_set_spi(void)
 {
-    static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spi[] = {
-#if (SPI_IOMUX_INDEX == 04)
-#ifdef SPI_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
+    static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spi_3wire[3] = {
         {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
         {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPI_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
         {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-
-#elif (SPI_IOMUX_INDEX == 24)
-#ifdef SPI_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-        {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPI_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-
-#elif (SPI_IOMUX_INDEX == 30)
-#ifdef SPI_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-        {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPI_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPI_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPI_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPI_IOMUX_CS1_INDEX
+#if (SPI_IOMUX_CS1_INDEX == 35)
+        {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPI_CS1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #else
-#error "Unsupported SPI_IOMUX_INDEX"
-#endif
-
-#if (SPI_IOMUX_CS1_INDEX == 10)
         {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPI_CS1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPI_IOMUX_CS1_INDEX == 35)
-        {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPI_CS1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-#if (SPI_IOMUX_CS2_INDEX == 11)
-        {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPI_CS2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPI_IOMUX_CS2_INDEX == 37)
+#endif
+#ifdef SPI_IOMUX_CS2_INDEX
+#if (SPI_IOMUX_CS2_INDEX == 37)
         {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPI_CS2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#else
+        {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPI_CS2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-#if (SPI_IOMUX_CS3_INDEX == 12)
-        {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPI_CS3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPI_IOMUX_CS3_INDEX == 25)
+#endif
+#ifdef SPI_IOMUX_CS3_INDEX
+#if (SPI_IOMUX_CS3_INDEX == 25)
         {HAL_IOMUX_PIN_P2_5, HAL_IOMUX_FUNC_SPI_CS3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#else
+        {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPI_CS3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-
-#ifdef SPI_IOMUX_4WIRE
-#if (SPI_IOMUX_DI1_INDEX == 13)
-        {HAL_IOMUX_PIN_P1_3, HAL_IOMUX_FUNC_SPI_DI1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPI_IOMUX_DI1_INDEX == 34)
-        {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPI_DI1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-#if (SPI_IOMUX_DI2_INDEX == 14)
-        {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPI_DI2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPI_IOMUX_DI2_INDEX == 36)
-        {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPI_DI2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+    };
+#ifdef SPI_IOMUX_4WIRE
+    static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spi_4wire[1] = {
+        {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPI_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPI_IOMUX_DI1_INDEX
+        {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPI_DI1, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-#if (SPI_IOMUX_DI3_INDEX == 15)
-        {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPI_DI3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPI_IOMUX_DI3_INDEX == 24)
-        {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPI_IOMUX_DI2_INDEX
+        {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPI_DI2, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
+#ifdef SPI_IOMUX_DI3_INDEX
+        {HAL_IOMUX_PIN_P2_4, HAL_IOMUX_FUNC_SPI_DI3, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
     };
+#endif
 
-    hal_iomux_init(pinmux_spi, ARRAY_SIZE(pinmux_spi));
-}
-
-void hal_iomux_set_spilcd_slave(void)
-{
-    iomux->REG_050 |= IOMUX_SPILCD1_MASTER_N;
+    hal_iomux_init(pinmux_spi_3wire, ARRAY_SIZE(pinmux_spi_3wire));
+#ifdef SPI_IOMUX_4WIRE
+    hal_iomux_init(pinmux_spi_4wire, ARRAY_SIZE(pinmux_spi_4wire));
+#endif
 }
 
 void hal_iomux_set_spilcd(void)
 {
-    static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spilcd[] = {
-#if (SPILCD_IOMUX_INDEX == 00)
-#ifdef SPILCD_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-        {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-
-#elif (SPILCD_IOMUX_INDEX == 10)
-#ifdef SPILCD_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+    static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spilcd_3wire[] = {
+#if (SPILCD_IOMUX_INDEX == 10)
+        {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPILCD_CLK, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPILCD_CS0, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#elif (SPILCD_IOMUX_INDEX == 35)
+        {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPILCD_CLK, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPILCD_CS0, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#else
+        {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_CS0, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P0_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-        {HAL_IOMUX_PIN_P1_0, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_SPILCD_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-
-#elif (SPILCD_IOMUX_INDEX == 20)
-#ifdef SPILCD_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPILCD_IOMUX_CS1_INDEX
+#if (SPILCD_IOMUX_CS1_INDEX == 12)
+        {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPILCD_CS1, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#elif (SPILCD_IOMUX_CS1_INDEX == 27)
+        {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPILCD_CS1, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#elif (SPILCD_IOMUX_CS1_INDEX == 30)
+        {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPILCD_CS1, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#else
+        {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPILCD_CS1, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-        {HAL_IOMUX_PIN_P2_3, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P2_2, HAL_IOMUX_FUNC_SPILCD_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-
-#elif (SPILCD_IOMUX_INDEX == 34)
-#ifdef SPILCD_IOMUX_4WIRE
-        {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-        {HAL_IOMUX_PIN_P3_7, HAL_IOMUX_FUNC_SPILCD_CLK, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P3_6, HAL_IOMUX_FUNC_SPILCD_CS0,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-        {HAL_IOMUX_PIN_P3_5, HAL_IOMUX_FUNC_SPILCD_DIO, SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPILCD_IOMUX_CS2_INDEX
+#if (SPILCD_IOMUX_CS2_INDEX == 31)
+        {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPILCD_CS2, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #else
-#error "Unsupported SPILCD_IOMUX_INDEX"
+        {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPILCD_CS2, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-
-#if (SPILCD_IOMUX_CS1_INDEX == 05)
-        {HAL_IOMUX_PIN_P0_5, HAL_IOMUX_FUNC_SPILCD_CS1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPILCD_IOMUX_CS1_INDEX == 12)
-        {HAL_IOMUX_PIN_P1_2, HAL_IOMUX_FUNC_SPILCD_CS1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPILCD_IOMUX_CS1_INDEX == 27)
-        {HAL_IOMUX_PIN_P2_7, HAL_IOMUX_FUNC_SPILCD_CS1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-#if (SPILCD_IOMUX_CS2_INDEX == 06)
-        {HAL_IOMUX_PIN_P0_6, HAL_IOMUX_FUNC_SPILCD_CS2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPILCD_IOMUX_CS2_INDEX == 31)
-        {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPILCD_CS2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#endif
-#if (SPILCD_IOMUX_CS3_INDEX == 07)
-        {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPILCD_CS3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPILCD_IOMUX_CS3_INDEX
+#if (SPILCD_IOMUX_CS3_INDEX == 31)
+        {HAL_IOMUX_PIN_P3_1, HAL_IOMUX_FUNC_SPILCD_CS3, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #elif (SPILCD_IOMUX_CS3_INDEX == 32)
-        {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPILCD_CS3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+        {HAL_IOMUX_PIN_P3_2, HAL_IOMUX_FUNC_SPILCD_CS3, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#else
+        {HAL_IOMUX_PIN_P0_7, HAL_IOMUX_FUNC_SPILCD_CS3, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-
+#endif
+    };
 #ifdef SPILCD_IOMUX_4WIRE
-#if (SPILCD_IOMUX_DI1_INDEX == 02)
-        {HAL_IOMUX_PIN_P0_2, HAL_IOMUX_FUNC_SPILCD_DI1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPILCD_IOMUX_DI1_INDEX == 26)
-        {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPILCD_DI1,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+    static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_spilcd_4wire[] = {
+#ifdef SPILCD_IOMUX_DI0_INDEX
+#if (SPILCD_IOMUX_DI0_INDEX == 14)
+        {HAL_IOMUX_PIN_P1_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#elif (SPILCD_IOMUX_DI0_INDEX == 34)
+        {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_SPILCD_DI0, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#else
+        {HAL_IOMUX_PIN_P0_0, HAL_IOMUX_FUNC_SPILCD_DI0, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#endif
 #endif
-#if (SPILCD_IOMUX_DI2_INDEX == 03)
-        {HAL_IOMUX_PIN_P0_3, HAL_IOMUX_FUNC_SPILCD_DI2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPILCD_IOMUX_DI2_INDEX == 30)
-        {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPILCD_DI2,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPILCD_IOMUX_DI1_INDEX
+        {HAL_IOMUX_PIN_P2_6, HAL_IOMUX_FUNC_SPILCD_DI1, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
-#if (SPILCD_IOMUX_DI3_INDEX == 04)
-        {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_SPILCD_DI3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
-#elif (SPILCD_IOMUX_DI3_INDEX == 33)
-        {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPILCD_DI3,  SPI_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
+#ifdef SPILCD_IOMUX_DI2_INDEX
+        {HAL_IOMUX_PIN_P3_0, HAL_IOMUX_FUNC_SPILCD_DI2, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
+#ifdef SPILCD_IOMUX_DI3_INDEX
+        {HAL_IOMUX_PIN_P3_3, HAL_IOMUX_FUNC_SPILCD_DI3, SPILCD_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
     };
+#endif
 
-    hal_iomux_init(pinmux_spilcd, ARRAY_SIZE(pinmux_spilcd));
+    hal_iomux_init(pinmux_spilcd_3wire, ARRAY_SIZE(pinmux_spilcd_3wire));
+#ifdef SPILCD_IOMUX_4WIRE
+    hal_iomux_init(pinmux_spilcd_4wire, ARRAY_SIZE(pinmux_spilcd_4wire));
+#endif
 }
 
 void hal_iomux_set_i2c0(void)
 {
+#if (I2C0_IOMUX_INDEX == 16)
+    hal_iomux_set_analog_i2c();
+    // IOMUX_GPIO_I2C_MODE should be kept in disabled state
+    iomux->REG_050 &= ~IOMUX_I2C0_M_SEL_GPIO;
+#else
     static const struct HAL_IOMUX_PIN_FUNCTION_MAP pinmux_i2c[] = {
         {HAL_IOMUX_PIN_P2_0, HAL_IOMUX_FUNC_I2C_M0_SCL, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
         {HAL_IOMUX_PIN_P2_1, HAL_IOMUX_FUNC_I2C_M0_SDA, I2C0_VOLTAGE_SEL, HAL_IOMUX_PIN_PULLUP_ENABLE},
     };
+
     hal_iomux_init(pinmux_i2c, ARRAY_SIZE(pinmux_i2c));
-    iomux->REG_050 |= IOMUX_I2C0_M_SEL_GPIO;
+#endif
 }
 
 void hal_iomux_set_i2c1(void)
@@ -1041,7 +981,7 @@ void hal_iomux_set_clock_out(void)
 #elif (CLKOUT_IOMUX_INDEX == 34)
         {HAL_IOMUX_PIN_P3_4, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #else
-#error "Unsupported CLKOUT_IOMUX_INDEX"
+        {HAL_IOMUX_PIN_P0_4, HAL_IOMUX_FUNC_CLK_OUT, CLKOUT_VOLTAGE_SEL, HAL_IOMUX_PIN_NOPULL},
 #endif
     };
 
@@ -1061,9 +1001,15 @@ void hal_iomux_set_bt_tport(void)
     // P0_0 ~ P0_3,
     iomux->REG_004 = (iomux->REG_004 & ~(IOMUX_GPIO_P00_SEL_MASK | IOMUX_GPIO_P01_SEL_MASK | IOMUX_GPIO_P02_SEL_MASK | IOMUX_GPIO_P03_SEL_MASK)) |
     IOMUX_GPIO_P00_SEL(0xA) | IOMUX_GPIO_P01_SEL(0xA) | IOMUX_GPIO_P02_SEL(0xA) |IOMUX_GPIO_P03_SEL(0xA);
+#ifdef TPORTS_KEY_COEXIST
+    //P1_1 ~ P1_2,
+    iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P11_SEL_MASK | IOMUX_GPIO_P12_SEL_MASK)) |
+    IOMUX_GPIO_P11_SEL(0xA) | IOMUX_GPIO_P12_SEL(0xA);
+#else
     //P1_0 ~ P1_3,
     iomux->REG_008 = (iomux->REG_008 & ~(IOMUX_GPIO_P10_SEL_MASK | IOMUX_GPIO_P11_SEL_MASK | IOMUX_GPIO_P12_SEL_MASK | IOMUX_GPIO_P13_SEL_MASK )) |
     IOMUX_GPIO_P10_SEL(0xA) | IOMUX_GPIO_P11_SEL(0xA) | IOMUX_GPIO_P12_SEL(0xA) | IOMUX_GPIO_P13_SEL(0xA);
+#endif
     // ANA TEST DIR
     iomux->REG_014 = 0x0f0f;
     // ANA TEST SEL
@@ -1102,9 +1048,7 @@ int WEAK hal_pwrkey_set_irq(enum HAL_PWRKEY_IRQ_T type)
 
 bool WEAK hal_pwrkey_pressed(void)
 {
-    uint32_t v = iomux->REG_040;
-    return !!(v & IOMUX_POWER_ON_FEEDOUT);
-
+    return 0;
 }
 
 bool hal_pwrkey_startup_pressed(void)
@@ -1115,9 +1059,38 @@ bool hal_pwrkey_startup_pressed(void)
 enum HAL_PWRKEY_IRQ_T WEAK hal_pwrkey_get_irq_state(void)
 {
     enum HAL_PWRKEY_IRQ_T state = HAL_PWRKEY_IRQ_NONE;
+
     return state;
 }
 
+const struct HAL_IOMUX_PIN_FUNCTION_MAP iomux_tport[] = {
+/*    {HAL_IOMUX_PIN_P1_1, HAL_IOMUX_FUNC_AS_GPIO, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_PULLUP_ENABLE},*/
+    {HAL_IOMUX_PIN_P1_5, HAL_IOMUX_FUNC_AS_GPIO, HAL_IOMUX_PIN_VOLTAGE_VIO, HAL_IOMUX_PIN_PULLUP_ENABLE},
+};
+
+int hal_iomux_tportopen(void)
+{
+    int i;
+
+    for (i=0;i<sizeof(iomux_tport)/sizeof(struct HAL_IOMUX_PIN_FUNCTION_MAP);i++){
+        hal_iomux_init((struct HAL_IOMUX_PIN_FUNCTION_MAP *)&iomux_tport[i], 1);
+        hal_gpio_pin_set_dir((enum HAL_GPIO_PIN_T)iomux_tport[i].pin, HAL_GPIO_DIR_OUT, 0);
+    }
+    return 0;
+}
+
+int hal_iomux_tportset(int port)
+{
+    hal_gpio_pin_set((enum HAL_GPIO_PIN_T)iomux_tport[port].pin);
+    return 0;
+}
+
+int hal_iomux_tportclr(int port)
+{
+    hal_gpio_pin_clr((enum HAL_GPIO_PIN_T)iomux_tport[port].pin);
+    return 0;
+}
+
 void hal_iomux_set_codec_gpio_trigger(enum HAL_IOMUX_PIN_T pin, bool polarity)
 {
     iomux->REG_064 = SET_BITFIELD(iomux->REG_064, IOMUX_CFG_CODEC_TRIG_SEL, pin);

platform/hal/best2300p/hal_iomux_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/hal_iomux_best2300p.h bes/platform/hal/best2300p/hal_iomux_best2300p.h
index c1f1c68b621..52d5a8f8a08 100644
--- a/platform/hal/best2300p/hal_iomux_best2300p.h
+++ b/platform/hal/best2300p/hal_iomux_best2300p.h
@@ -130,29 +130,18 @@ enum HAL_IOMUX_FUNCTION_T {
     HAL_IOMUX_FUNC_I2C_M0_SCL,
     HAL_IOMUX_FUNC_I2C_M0_SDA,
     HAL_IOMUX_FUNC_I2C_M1_SCL,
-    HAL_IOMUX_FUNC_I2C_M2_SCL,
-    HAL_IOMUX_FUNC_I2C_M2_SDA,
     HAL_IOMUX_FUNC_I2C_M1_SDA,
-    HAL_IOMUX_FUNC_I2S_MCLK,
+    HAL_IOMUX_FUNC_I2C_SCL,
+    HAL_IOMUX_FUNC_I2C_SDA,
+    HAL_IOMUX_FUNC_I2S0_MCLK,
     HAL_IOMUX_FUNC_I2S0_SCK,
     HAL_IOMUX_FUNC_I2S0_SDI0,
-    HAL_IOMUX_FUNC_I2S0_SDI1,
-    HAL_IOMUX_FUNC_I2S0_SDI2,
-    HAL_IOMUX_FUNC_I2S0_SDI3,
-    HAL_IOMUX_FUNC_I2S0_SDO0,
-    HAL_IOMUX_FUNC_I2S0_SDO1,
-    HAL_IOMUX_FUNC_I2S0_SDO2,
-    HAL_IOMUX_FUNC_I2S0_SDO3,
+    HAL_IOMUX_FUNC_I2S0_SDO,
     HAL_IOMUX_FUNC_I2S0_WS,
+    HAL_IOMUX_FUNC_I2S1_MCLK,
     HAL_IOMUX_FUNC_I2S1_SCK,
     HAL_IOMUX_FUNC_I2S1_SDI0,
-    HAL_IOMUX_FUNC_I2S1_SDI1,
-    HAL_IOMUX_FUNC_I2S1_SDI2,
-    HAL_IOMUX_FUNC_I2S1_SDI3,
-    HAL_IOMUX_FUNC_I2S1_SDO0,
-    HAL_IOMUX_FUNC_I2S1_SDO1,
-    HAL_IOMUX_FUNC_I2S1_SDO2,
-    HAL_IOMUX_FUNC_I2S1_SDO3,
+    HAL_IOMUX_FUNC_I2S1_SDO,
     HAL_IOMUX_FUNC_I2S1_WS,
     HAL_IOMUX_FUNC_PCM_CLK,
     HAL_IOMUX_FUNC_PCM_DI,
@@ -231,8 +220,11 @@ void hal_iomux_set_mcu_clock_out(void);
 
 void hal_iomux_set_bt_clock_out(void);
 
+int hal_iomux_tportopen(void);
 
+int hal_iomux_tportclr(int port);
 
+int hal_iomux_tportset(int port);
 
 #ifdef __cplusplus
 }

Author

OneDeuxTriSeiGo commented Mar 19, 2024

platform/hal/best2300p/hal_psc_best2300p.c

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/hal_psc_best2300p.c bes/platform/hal/best2300p/hal_psc_best2300p.c
index 3ff9c39821a..216f189cbe0 100644
--- a/platform/hal/best2300p/hal_psc_best2300p.c
+++ b/platform/hal/best2300p/hal_psc_best2300p.c
@@ -25,12 +25,22 @@ static struct AONPSC_T * const psc = (struct AONPSC_T *)AON_PSC_BASE;
 
 void BOOT_TEXT_FLASH_LOC hal_psc_init(void)
 {
-    // Setup MCU wakeup mask
-    psc->REG_080 = 0;
-    psc->REG_084 = 0;
+    // Setup wakeup mask
+    psc->REG_080 = 0xFFFFFFFF;
+    psc->REG_084 = 0xFFFFFFFF;
 }
 
+void SRAM_TEXT_LOC hal_psc_core_auto_power_down(void)
+{
+    psc->REG_018 = PSC_WRITE_ENABLE | 0;
+    psc->REG_000 = PSC_WRITE_ENABLE | PSC_AON_MCU_PG_AUTO_EN;
+    psc->REG_010 = PSC_WRITE_ENABLE | PSC_AON_MCU_POWERDN_START;
+}
 
+void SRAM_TEXT_LOC hal_psc_mcu_auto_power_up(void)
+{
+    psc->REG_014 = PSC_WRITE_ENABLE | PSC_AON_MCU_POWERUP_START;
+}
 
 void BOOT_TEXT_FLASH_LOC hal_psc_codec_enable(void)
 {
@@ -90,10 +100,18 @@ void BOOT_TEXT_FLASH_LOC hal_psc_bt_enable(void)
         PSC_AON_BT_ISO_EN_DR |
         PSC_AON_BT_CLK_STOP_DR;
 
+#ifdef JTAG_BT
+    psc->REG_064 |= PSC_AON_CODEC_RESERVED(1 << 3);
+    psc->REG_064 &= ~PSC_AON_CODEC_RESERVED(1 << 2);
+#endif
 }
 
 void BOOT_TEXT_FLASH_LOC hal_psc_bt_disable(void)
 {
+#ifdef JTAG_BT
+    psc->REG_064 &= ~PSC_AON_CODEC_RESERVED(1 << 3);
+    psc->REG_064 |= PSC_AON_CODEC_RESERVED(1 << 2);
+#endif
 
     psc->REG_038 = PSC_WRITE_ENABLE |
         PSC_AON_BT_PSW_EN_DR | PSC_AON_BT_PSW_EN_REG |

platform/hal/best2300p/Makefile

No Declared License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/Makefile bes/platform/hal/best2300p/Makefile
index 498ac0276ea..68478398fd4 100644
--- a/platform/hal/best2300p/Makefile
+++ b/platform/hal/best2300p/Makefile
@@ -27,8 +27,31 @@ ifeq ($(USB_USE_USBPLL),1)
 CMU_CFG_FLAGS += -DUSB_USE_USBPLL
 endif
 
+ifeq ($(USB_CLK_SRC_24M_X2),1)
+CMU_CFG_FLAGS += -DUSB_CLK_SRC_24M_X2
+else
+ifeq ($(USB_CLK_SRC_48M),1)
+CMU_CFG_FLAGS += -DUSB_CLK_SRC_48M
+else
+ifeq ($(USB_CLK_SRC_26M_X4),1)
+CMU_CFG_FLAGS += -DUSB_CLK_SRC_26M_X4
+else
+ifeq ($(USB_CLK_SRC_26M_X2),1)
+CMU_CFG_FLAGS += -DUSB_CLK_SRC_26M_X2
+endif
+endif
+endif
+endif
 
+ifeq ($(RESAMPLE_CODEC_CLK_ANA),1)
+CMU_CFG_FLAGS += -DRESAMPLE_CODEC_CLK_ANA
+endif
 
+ifeq ($(LOW_SYS_FREQ),1)
+ifneq ($(FLASH_LOW_SPEED),1)
+$(error FLASH_LOW_SPEED should be enabled along with LOW_SYS_FREQ)
+endif
+endif
 
 ifeq ($(DAC_CLASSG_ENABLE),1)
 CODEC_CFG_FLAGS += -DDAC_CLASSG_ENABLE
@@ -40,6 +63,7 @@ endif
 
 ifeq ($(JTAG_BT),1)
 PSC_CFG_FLAGS += -DJTAG_BT
+JTAG_TDI_TDO_PIN ?= 1
 endif
 
 ifeq ($(JTAG_TDI_TDO_PIN),1)

platform/hal/best2300p/plat_addr_map_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/plat_addr_map_best2300p.h bes/platform/hal/best2300p/plat_addr_map_best2300p.h
index ef4ca25946d..95c277b27c1 100644
--- a/platform/hal/best2300p/plat_addr_map_best2300p.h
+++ b/platform/hal/best2300p/plat_addr_map_best2300p.h
@@ -19,172 +19,81 @@
 extern "C" {
 #endif
 
-#define ROM_BASE                                0x00020000
-#define ROMD_BASE                               0x24020000
+#define ROM_BASE                                0x00000000
 
 #ifndef ROM_SIZE
-#ifdef FPGA
-#define ROM_SIZE                                0x00020000
-#else
-#define ROM_SIZE                                0x00010000
+#define ROM_SIZE                                0x0000C000
 #endif
+
+#define RAMRET_BASE                             0x200D8000
+#define RAMXRET_BASE                            0x002D8000
+
+#ifndef RAMRET_SIZE
+#define RAMRET_SIZE                             0x00020000
 #endif
 
 #define RAM0_BASE                               0x20000000
 #define RAMX0_BASE                              0x00200000
-#define RAM1_BASE                               0x20040000
-#define RAMX1_BASE                              0x00240000
-#define RAM2_BASE                               0x20080000
-#define RAMX2_BASE                              0x00280000
-#define RAM3_BASE                               0x20100000
-#define RAMX3_BASE                              0x00300000
-#define RAM4_BASE                               0x20180000
-#define RAMX4_BASE                              0x00380000
-#define RAM5_BASE                               0x201C0000
-#define RAMX5_BASE                              0x003C0000
+#define RAM1_BASE                               0x20020000
+#define RAMX1_BASE                              0x00220000
+#define RAM2_BASE                               0x20040000
+#define RAMX2_BASE                              0x00240000
+#define RAM3_BASE                               0x20060000
+#define RAMX3_BASE                              0x00260000
+#define RAM4_BASE                               0x20080000
+#define RAMX4_BASE                              0x00280000
+#define RAM5_BASE                               0x200A0000
+#define RAMX5_BASE                              0x002A0000
+#define RAM6_BASE                               0x200C0000
+#define RAMX6_BASE                              0x002C0000
 #define RAM_BASE                                RAM0_BASE
 #define RAMX_BASE                               RAMX0_BASE
 
-#define RAM5_SIZE                               0x00040000
-
-/* total ramv size is 0x30000 */
-#define RAMV_BASE                               0x20200000
-#ifndef RAMV_SIZE
-#define RAMV_SIZE                               0x00000000
-#endif
-
-#ifdef __BT_RAMRUN__
-#define BT_RAMRUN_BASE                           RAM3_BASE
-#define BT_RAMRUNX_BASE                          RAMX3_BASE
-#endif
-
-#ifndef CP_FLASH_SIZE
-#define CP_FLASH_SIZE 0
-#endif
-
 #ifdef CHIP_HAS_CP
-#if (CP_FLASH_SIZE > 0)
-#define CP_FLASH_BASE                           (FLASH_BASE + FLASH_SIZE - CP_FLASH_SIZE)
-#define CP_FLASHX_BASE                          (FLASHX_BASE + FLASH_SIZE - CP_FLASH_SIZE)
-#endif
-
-#ifdef LARGE_RAM
-/*MCU use RAM0/1/2/3, CPX use RAM4, and CP use RAM5*/
-#define RAMCP_TOP                               (RAM5_BASE + RAM5_SIZE)
+#define RAMCP_TOP                               (RAMRET_BASE + RAMRET_SIZE - 0x20)
 
 #ifndef RAMCP_SIZE
-#define RAMCP_SIZE                              RAM5_SIZE
+#define RAMCP_SIZE                              (RAMRET_SIZE - 0x20)
 #endif
-
-#ifndef RAMCP_BASE
 #define RAMCP_BASE                              (RAMCP_TOP - RAMCP_SIZE)
-#endif
 
 #ifndef RAMCPX_SIZE
-#define RAMCPX_SIZE                             (RAM5_BASE - RAM4_BASE)
+#define RAMCPX_SIZE                             (RAMXRET_BASE - RAMX6_BASE)
 #endif
-
 #ifndef RAMCPX_BASE
 #define RAMCPX_BASE                             (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE)
 #endif
-
-#else /*LARGE_RAM*/
-/*MCU use RAM0, CP and CPX use RAM1*/
-#define RAMCP_TOP                               RAM2_BASE
-
-#ifndef RAMCP_SIZE
-#define RAMCP_SIZE                              0x20000
-#endif
-
-#ifndef RAMCP_BASE
-#define RAMCP_BASE                              (RAMCP_TOP - RAMCP_SIZE)
-#endif
-
-#ifndef RAMCPX_SIZE
-#define RAMCPX_SIZE                             (RAMX2_BASE - RAMX1_BASE - RAMCP_SIZE)
-#endif
-
-#ifndef RAMCPX_BASE
-#define RAMCPX_BASE                             (RAM_TO_RAMX(RAMCP_BASE) - RAMCPX_SIZE)
-#endif
-
-#endif /*LARGE_RAM*/
 #endif
 
-#define RAM_TOTAL_SIZE                          (RAM5_BASE + RAM5_SIZE - RAM0_BASE) // 0x00200000
-
-#if defined(ARM_CMSE) || defined(ARM_CMNS)
-#undef RAM_BASE
-#undef RAMX_BASE
-
-/*MPC: SRAM block size: 0x8000, FLASH block size 0x40000*/
-#ifndef RAM_S_SIZE
-#define RAM_S_SIZE                              0x00020000
-#endif
-#define RAM_NSC_SIZE                            0
-#ifndef FLASH_S_SIZE
-#define FLASH_S_SIZE                            0x00040000
-#endif
-
-#define RAM_NS_BASE                             (RAM0_BASE + RAM_S_SIZE)
-#define RAMX_NS_BASE                            (RAMX0_BASE + RAM_S_SIZE)
-
-#if defined(ARM_CMNS)
-#define RAM_BASE                                RAM_NS_BASE
-#define RAMX_BASE                               RAMX_NS_BASE
-#else
-#if ((RAM_S_SIZE) & (0x8000-1))
-#error "RAM_S_SIZE should be 0x8000 aligned"
-#endif
-#if (FLASH_S_SIZE & (0x40000-1))
-#error "FLASH_S_SIZE should be 0x40000 aligned"
-#endif
-#define RAM_BASE                                RAM0_BASE
-#define RAMX_BASE                               RAMX0_BASE
-#define RAM_SIZE                                RAM_S_SIZE
-#ifndef NS_APP_START_OFFSET
-#define NS_APP_START_OFFSET                     (FLASH_S_SIZE)
-#endif
-#ifndef FLASH_REGION_SIZE
-#define FLASH_REGION_SIZE                       FLASH_S_SIZE
-#endif
-#endif
-#endif /* defined(ARM_CMSE) || defined(ARM_CMNS) */
-
-#ifndef RAM_MCU_SIZE
-/* secure and non-secure ram size */
-#ifdef LARGE_RAM
+#ifndef RAM_SIZE
 #ifdef CHIP_HAS_CP
-#define RAM_MCU_SIZE                            (RAMCPX_BASE - RAMX_BASE)
+#define RAM_SIZE                                (RAMCPX_BASE - RAMX_BASE) // 0X000C0000
 #else
-#define RAM_MCU_SIZE                            (RAM5_BASE + RAM5_SIZE - RAM_BASE)
-#endif
-#else
-#ifdef CHIP_HAS_CP
-#define RAM_MCU_SIZE                            (RAMCPX_BASE - RAMX_BASE)
+#ifdef LARGE_RAM
+#define RAM_SIZE                                (RAMRET_BASE + RAMRET_SIZE - RAM_BASE) // 0x000F8000
 #else
-#define RAM_MCU_SIZE                            (RAM2_BASE - RAM_BASE) // 0x00080000
-#endif
-#endif
-#endif /*RAM_MCU_SIZE*/
-
-#if defined(ARM_CMSE)
-#ifndef RAM_NS_SIZE
-#define RAM_NS_SIZE                             (RAM_BASE + RAM_MCU_SIZE - RAM_NS_BASE)
-#endif /*RAM_NS_SIZE*/
+#define RAM_SIZE                                (RAMRET_BASE - RAM_BASE) // 0x000D8000
 #endif
+#endif /* !CHIP_HAS_CP */
+#endif /* !RAM_SIZE */
 
-#ifndef RAM_SIZE
-#define RAM_SIZE                                RAM_MCU_SIZE
+#if defined(ROM_BUILD) && defined(CORE_SLEEP_POWER_DOWN)
+#undef RAM_BASE
+#undef RAMX_BASE
+#undef RAM_SIZE
+#define RAM_BASE                                RAMRET_BASE
+#define RAMX_BASE                               RAMXRET_BASE
+#define RAM_SIZE                                RAMRET_SIZE
 #endif
 
-#define FLASH_BASE                              0x2C000000
-#define FLASH_NC_BASE                           0x28000000
+#define FLASH_BASE                              0x3C000000
+#define FLASH_NC_BASE                           0x38000000
 #define FLASHX_BASE                             0x0C000000
 #define FLASHX_NC_BASE                          0x08000000
 
-#define DCACHE_CTRL_BASE                        0x27FFA000
-#define ICACHE_CTRL_BASE                        0x27FFC000
+#define ICACHE_CTRL_BASE                        0x07FFE000
+#define ICACHECP_CTRL_BASE                      0x07FFA000
+/* No data cache */
 
 #define CMU_BASE                                0x40000000
 #define MCU_WDT_BASE                            0x40001000
@@ -203,42 +112,42 @@ extern "C" {
 #define BTPCM_BASE                              0x4000E000
 #define I2S0_BASE                               0x4000F000
 #define SPDIF0_BASE                             0x40010000
-#define I2S1_BASE                               0x40017000
+#define I2S1_BASE                               0x40011000
 #define SEC_ENG_BASE                            0x40020000
 
 #define AON_CMU_BASE                            0x40080000
 #define AON_GPIO_BASE                           0x40081000
 #define AON_WDT_BASE                            0x40082000
-#define AON_PWM0_BASE                           0x40083000
+#define AON_PWM_BASE                            0x40083000
 #define AON_TIMER_BASE                          0x40084000
-#define AON_PSC_BASE                            0x40088000
+#define AON_PSC_BASE                            0x40085000
 #define AON_IOMUX_BASE                          0x40086000
 
-#define CHECKSUM_BASE                           0x40100000
-#define CRC_BASE                                0x40108000
 #define SDMMC_BASE                              0x40110000
-#define BES2003_AUDMA_BASE                      0x40120000
-#define BES2003_GPDMA_BASE                      0x40130000
+#define AUDMA_BASE                              0x40120000
+#define GPDMA_BASE                              0x40130000
 #define FLASH_CTRL_BASE                         0x40140000
-#define BTDUMP_BASE                             0x401E0000
+#define BTDUMP_BASE                             0x40150000
 #define I2C_SLAVE_BASE                          0x40160000
+#define SENSOR_ENG_BASE                         0x40170000
 #define USB_BASE                                0x40180000
 #define SEDMA_BASE                              0x401D0000
 
-#define CODEC_BASE                              0x40380000
+#define CODEC_BASE                              0x40300000
 
 #define BT_SUBSYS_BASE                          0xA0000000
 #define BT_RAM_BASE                             0xC0000000
 #define BT_RAM_SIZE                             0x00008000
+#define BT_EXCH_MEM_BASE                        0xD0210000
+#define BT_EXCH_MEM_SIZE                        0x00008000
 #define BT_UART_BASE                            0xD0300000
 #define BT_CMU_BASE                             0xD0330000
 
 #define IOMUX_BASE                              AON_IOMUX_BASE
 #define GPIO_BASE                               AON_GPIO_BASE
-#define PWM_BASE                                AON_PWM0_BASE
-
-#ifdef CHIP_BEST2003_DSP
-#define TIMER0_BASE                             DSP_TIMER0_BASE
+#define PWM_BASE                                AON_PWM_BASE
+#ifdef CORE_SLEEP_POWER_DOWN
+#define TIMER0_BASE                             AON_TIMER_BASE
 #else
 #define TIMER0_BASE                             MCU_TIMER0_BASE
 #endif
@@ -247,14 +156,15 @@ extern "C" {
 
 /* For linker scripts */
 
-#define VECTOR_SECTION_SIZE                     360
+#define VECTOR_SECTION_SIZE                     320
 #define REBOOT_PARAM_SECTION_SIZE               64
 #define ROM_BUILD_INFO_SECTION_SIZE             40
 #define ROM_EXPORT_FN_SECTION_SIZE              128
+#define BT_INTESYS_MEM_OFFSET                   0x00000000
 
 /* For boot struct version */
 #ifndef SECURE_BOOT_VER
-#define SECURE_BOOT_VER                         4
+#define SECURE_BOOT_VER                         2
 #endif
 
 #ifdef __cplusplus

platform/hal/best2300p/reg_aoncmu_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/reg_aoncmu_best2300p.h bes/platform/hal/best2300p/reg_aoncmu_best2300p.h
index 5018183c962..ba7e71e4f31 100644
--- a/platform/hal/best2300p/reg_aoncmu_best2300p.h
+++ b/platform/hal/best2300p/reg_aoncmu_best2300p.h
@@ -30,7 +30,7 @@ struct AONCMU_T {
     __IO uint32_t MEMSC[4];         // 0x24
     __I  uint32_t MEMSC_STATUS;     // 0x34
     __IO uint32_t BOOTMODE;         // 0x38
-    __IO uint32_t FLS_PSR_CLK;      // 0x3C
+    __IO uint32_t RESERVED_03C;     // 0x3C
     __IO uint32_t MOD_CLK_ENABLE;   // 0x40
     __IO uint32_t MOD_CLK_DISABLE;  // 0x44
     __IO uint32_t MOD_CLK_MODE;     // 0x48
@@ -38,7 +38,7 @@ struct AONCMU_T {
     __IO uint32_t TIMER_CLK;        // 0x50
     __IO uint32_t PWM01_CLK;        // 0x54
     __IO uint32_t PWM23_CLK;        // 0x58
-    __IO uint32_t LNA_CFG;          // 0x5C
+    __IO uint32_t RAM_CFG;          // 0x5C
     __IO uint32_t RESERVED_060;     // 0x60
     __IO uint32_t PCM_I2S_CLK;      // 0x64
     __IO uint32_t SPDIF_CLK;        // 0x68
@@ -49,7 +49,7 @@ struct AONCMU_T {
     __IO uint32_t SE_WLOCK;         // 0x7C
     __IO uint32_t SE_RLOCK;         // 0x80
     __IO uint32_t PD_STAB_TIMER;    // 0x84
-    __IO uint32_t TIMER_WDT;        // 0x88
+         uint32_t RESERVED_088[0x1A]; // 0x88
     __IO uint32_t WAKEUP_PC;        // 0xF0
     __IO uint32_t DEBUG_RES[2];     // 0xF4
     __IO uint32_t CHIP_FEATURE;     // 0xFC
@@ -64,65 +64,75 @@ struct AONCMU_T {
 #define AON_CMU_REVISION_ID_SHIFT               (16)
 
 // reg_04
-#define AON_CMU_EN_CLK_TOP_OSC_ENABLE           (1 << 0)
-#define AON_CMU_EN_CLK_TOP_OSCX2_ENABLE         (1 << 1)
-#define AON_CMU_EN_CLK_TOP_OSCX4_ENABLE         (1 << 2)
-#define AON_CMU_EN_CLK_TOP_PLLBB_ENABLE         (1 << 3)
-#define AON_CMU_EN_CLK_TOP_PLLA7_ENABLE         (1 << 4)
-#define AON_CMU_EN_CLK_TOP_PLLDDR_ENABLE        (1 << 5)
+#define AON_CMU_EN_CLK_TOP_PLLBB_ENABLE         (1 << 0)
+#define AON_CMU_EN_CLK_TOP_PLLAUD_ENABLE        (1 << 1)
+#define AON_CMU_EN_CLK_TOP_OSCX2_ENABLE         (1 << 2)
+#define AON_CMU_EN_CLK_TOP_OSC_ENABLE           (1 << 3)
+#define AON_CMU_EN_CLK_TOP_JTAG_ENABLE          (1 << 4)
+#define AON_CMU_EN_CLK_TOP_PLLBB2_ENABLE        (1 << 5)
 #define AON_CMU_EN_CLK_TOP_PLLUSB_ENABLE        (1 << 6)
-#define AON_CMU_EN_CLK_TOP_PLLBB_PS_ENABLE      (1 << 7)
-#define AON_CMU_EN_CLK_TOP_PLLBB_WF_ENABLE      (1 << 8)
-#define AON_CMU_EN_CLK_TOP_PHY_PS_ENABLE        (1 << 9)
-#define AON_CMU_EN_CLK_TOP_JTAG_ENABLE          (1 << 10)
-#define AON_CMU_EN_CLK_USB_PLL_ENABLE           (1 << 11)
-#define AON_CMU_EN_CLK_BT_ENABLE                (1 << 12)
-#define AON_CMU_EN_CLK_WF_ENABLE                (1 << 13)
-#define AON_CMU_EN_CLK_CODEC_ENABLE             (1 << 14)
-#define AON_CMU_EN_CLK_CODECIIR_ENABLE          (1 << 15)
-#define AON_CMU_EN_CLK_CODECRS0_ENABLE          (1 << 16)
-#define AON_CMU_EN_CLK_CODECRS1_ENABLE          (1 << 17)
-#define AON_CMU_EN_CLK_CODECHCLK_ENABLE         (1 << 18)
-#define AON_CMU_EN_CLK_VAD32K_ENABLE            (1 << 19)
-#define AON_CMU_EN_CLK_MCU_32K_ENABLE           (1 << 20)
-#define AON_CMU_EN_CLK_MCU_OSC_ENABLE           (1 << 21)
-#define AON_CMU_EN_CLK_MCU_OSCX2_ENABLE         (1 << 22)
-#define AON_CMU_EN_X2_DIG_ENABLE                (1 << 23)
-#define AON_CMU_EN_X4_DIG_ENABLE                (1 << 24)
-#define AON_CMU_EN_BT_CLK_SYS_ENABLE            (1 << 25)
-#define AON_CMU_EN_CLK_PSRAMX2_ENABLE           (1 << 26)
+#define AON_CMU_EN_CLK_PLL_CODEC_ENABLE         (1 << 7)
+#define AON_CMU_EN_CLK_CODEC_HCLK_ENABLE        (1 << 8)
+#define AON_CMU_EN_CLK_CODEC_RS_ENABLE          (1 << 9)
+#define AON_CMU_EN_CLK_CODEC_ENABLE             (1 << 10)
+#define AON_CMU_EN_CLK_CODEC_IIR_ENABLE         (1 << 11)
+#define AON_CMU_EN_CLK_OSCX2_MCU_ENABLE         (1 << 12)
+#define AON_CMU_EN_CLK_OSC_MCU_ENABLE           (1 << 13)
+#define AON_CMU_EN_CLK_32K_MCU_ENABLE           (1 << 14)
+#define AON_CMU_EN_CLK_PLL_BT_ENABLE            (1 << 15)
+#define AON_CMU_EN_CLK_60M_BT_ENABLE            (1 << 16)
+#define AON_CMU_EN_CLK_OSCX2_BT_ENABLE          (1 << 17)
+#define AON_CMU_EN_CLK_OSC_BT_ENABLE            (1 << 18)
+#define AON_CMU_EN_CLK_32K_BT_ENABLE            (1 << 19)
+#define AON_CMU_EN_CLK_PLL_PER_ENABLE           (1 << 20)
+#define AON_CMU_EN_CLK_DCDC0_ENABLE             (1 << 21)
+#define AON_CMU_EN_CLK_DCDC1_ENABLE             (1 << 22)
+#define AON_CMU_EN_CLK_DCDC2_ENABLE             (1 << 23)
+#define AON_CMU_EN_X2_DIG_ENABLE                (1 << 24)
+#define AON_CMU_EN_X4_DIG_ENABLE                (1 << 25)
+#define AON_CMU_PU_PLLBB_ENABLE                 (1 << 26)
+#define AON_CMU_PU_PLLUSB_ENABLE                (1 << 27)
+#define AON_CMU_PU_PLLAUD_ENABLE                (1 << 28)
+#define AON_CMU_PU_OSC_ENABLE                   (1 << 29)
+#define AON_CMU_EN_X4_ANA_ENABLE                (1 << 30)
+#define AON_CMU_EN_CLK_32K_CODEC_ENABLE         (1 << 31)
 
 // reg_08
-#define AON_CMU_EN_CLK_TOP_OSC_DISABLE          (1 << 0)
-#define AON_CMU_EN_CLK_TOP_OSCX2_DISABLE        (1 << 1)
-#define AON_CMU_EN_CLK_TOP_OSCX4_DISABLE        (1 << 2)
-#define AON_CMU_EN_CLK_TOP_PLLBB_DISABLE        (1 << 3)
-#define AON_CMU_EN_CLK_TOP_PLLA7_DISABLE        (1 << 4)
-#define AON_CMU_EN_CLK_TOP_PLLDDR_DISABLE       (1 << 5)
+#define AON_CMU_EN_CLK_TOP_PLLBB_DISABLE        (1 << 0)
+#define AON_CMU_EN_CLK_TOP_PLLAUD_DISABLE       (1 << 1)
+#define AON_CMU_EN_CLK_TOP_OSCX2_DISABLE        (1 << 2)
+#define AON_CMU_EN_CLK_TOP_OSC_DISABLE          (1 << 3)
+#define AON_CMU_EN_CLK_TOP_JTAG_DISABLE         (1 << 4)
+#define AON_CMU_EN_CLK_TOP_PLLBB2_DISABLE       (1 << 5)
 #define AON_CMU_EN_CLK_TOP_PLLUSB_DISABLE       (1 << 6)
-#define AON_CMU_EN_CLK_TOP_PLLBB_PS_DISABLE     (1 << 7)
-#define AON_CMU_EN_CLK_TOP_PLLBB_WF_DISABLE     (1 << 8)
-#define AON_CMU_EN_CLK_TOP_PHY_PS_DISABLE       (1 << 9)
-#define AON_CMU_EN_CLK_TOP_JTAG_DISABLE         (1 << 10)
-#define AON_CMU_EN_CLK_USB_PLL_DISABLE          (1 << 11)
-#define AON_CMU_EN_CLK_BT_DISABLE               (1 << 12)
-#define AON_CMU_EN_CLK_WF_DISABLE               (1 << 13)
-#define AON_CMU_EN_CLK_CODEC_DISABLE            (1 << 14)
-#define AON_CMU_EN_CLK_CODECIIR_DISABLE         (1 << 15)
-#define AON_CMU_EN_CLK_CODECRS0_DISABLE         (1 << 16)
-#define AON_CMU_EN_CLK_CODECRS1_DISABLE         (1 << 17)
-#define AON_CMU_EN_CLK_CODECHCLK_DISABLE        (1 << 18)
-#define AON_CMU_EN_CLK_VAD32K_DISABLE           (1 << 19)
-#define AON_CMU_EN_CLK_MCU_32K_DISABLE          (1 << 20)
-#define AON_CMU_EN_CLK_MCU_OSC_DISABLE          (1 << 21)
-#define AON_CMU_EN_CLK_MCU_OSCX2_DISABLE        (1 << 22)
-#define AON_CMU_EN_X2_DIG_DISABLE               (1 << 23)
-#define AON_CMU_EN_X4_DIG_DISABLE               (1 << 24)
-#define AON_CMU_EN_BT_CLK_SYS_DISABLE           (1 << 25)
-#define AON_CMU_EN_CLK_PSRAMX2_DISABLE          (1 << 26)
-
-#define AON_ARST_NUM                            13
-#define AON_ORST_NUM                            18
+#define AON_CMU_EN_CLK_PLL_CODEC_DISABLE        (1 << 7)
+#define AON_CMU_EN_CLK_CODEC_HCLK_DISABLE       (1 << 8)
+#define AON_CMU_EN_CLK_CODEC_RS_DISABLE         (1 << 9)
+#define AON_CMU_EN_CLK_CODEC_DISABLE            (1 << 10)
+#define AON_CMU_EN_CLK_CODEC_IIR_DISABLE        (1 << 11)
+#define AON_CMU_EN_CLK_OSCX2_MCU_DISABLE        (1 << 12)
+#define AON_CMU_EN_CLK_OSC_MCU_DISABLE          (1 << 13)
+#define AON_CMU_EN_CLK_32K_MCU_DISABLE          (1 << 14)
+#define AON_CMU_EN_CLK_PLL_BT_DISABLE           (1 << 15)
+#define AON_CMU_EN_CLK_60M_BT_DISABLE           (1 << 16)
+#define AON_CMU_EN_CLK_OSCX2_BT_DISABLE         (1 << 17)
+#define AON_CMU_EN_CLK_OSC_BT_DISABLE           (1 << 18)
+#define AON_CMU_EN_CLK_32K_BT_DISABLE           (1 << 19)
+#define AON_CMU_EN_CLK_PLL_PER_DISABLE          (1 << 20)
+#define AON_CMU_EN_CLK_DCDC0_DISABLE            (1 << 21)
+#define AON_CMU_EN_CLK_DCDC1_DISABLE            (1 << 22)
+#define AON_CMU_EN_CLK_DCDC2_DISABLE            (1 << 23)
+#define AON_CMU_EN_X2_DIG_DISABLE               (1 << 24)
+#define AON_CMU_EN_X4_DIG_DISABLE               (1 << 25)
+#define AON_CMU_PU_PLLBB_DISABLE                (1 << 26)
+#define AON_CMU_PU_PLLUSB_DISABLE               (1 << 27)
+#define AON_CMU_PU_PLLAUD_DISABLE               (1 << 28)
+#define AON_CMU_PU_OSC_DISABLE                  (1 << 29)
+#define AON_CMU_EN_X4_ANA_DISABLE               (1 << 30)
+#define AON_CMU_EN_CLK_32K_CODEC_DISABLE        (1 << 31)
+
+#define AON_ARST_NUM                            10
+#define AON_ORST_NUM                            10
 #define AON_ACLK_NUM                            AON_ARST_NUM
 #define AON_OCLK_NUM                            AON_ORST_NUM
 
@@ -133,6 +143,14 @@ struct AONCMU_T {
 #define AON_CMU_ORESETN_PULSE(n)                (((n) & 0xFFFFFFFF) << AON_ARST_NUM)
 #define AON_CMU_ORESETN_PULSE_MASK              (0xFFFFFFFF << AON_ARST_NUM)
 #define AON_CMU_ORESETN_PULSE_SHIFT             (AON_ARST_NUM)
+#define AON_CMU_SOFT_RSTN_MCU_PULSE             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1-1))
+#define AON_CMU_SOFT_RSTN_CODEC_PULSE           (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1-1))
+#define AON_CMU_SOFT_RSTN_WF_PULSE              (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_BT_PULSE              (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_MCUCPU_PULSE          (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_WFCPU_PULSE           (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_BTCPU_PULSE           (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1+1-1))
+#define AON_CMU_GLOBAL_RESETN_PULSE             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1+1+1-1))
 
 // reg_10
 #define AON_CMU_ARESETN_SET(n)                  (((n) & 0xFFFFFFFF) << 0)
@@ -141,6 +159,14 @@ struct AONCMU_T {
 #define AON_CMU_ORESETN_SET(n)                  (((n) & 0xFFFFFFFF) << AON_ARST_NUM)
 #define AON_CMU_ORESETN_SET_MASK                (0xFFFFFFFF << AON_ARST_NUM)
 #define AON_CMU_ORESETN_SET_SHIFT               (AON_ARST_NUM)
+#define AON_CMU_SOFT_RSTN_MCU_SET               (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1-1))
+#define AON_CMU_SOFT_RSTN_CODEC_SET             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1-1))
+#define AON_CMU_SOFT_RSTN_WF_SET                (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_BT_SET                (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_MCUCPU_SET            (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_WFCPU_SET             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_BTCPU_SET             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1+1-1))
+#define AON_CMU_GLOBAL_RESETN_SET               (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1+1+1-1))
 
 // reg_14
 #define AON_CMU_ARESETN_CLR(n)                  (((n) & 0xFFFFFFFF) << 0)
@@ -149,57 +175,70 @@ struct AONCMU_T {
 #define AON_CMU_ORESETN_CLR(n)                  (((n) & 0xFFFFFFFF) << AON_ARST_NUM)
 #define AON_CMU_ORESETN_CLR_MASK                (0xFFFFFFFF << AON_ARST_NUM)
 #define AON_CMU_ORESETN_CLR_SHIFT               (AON_ARST_NUM)
+#define AON_CMU_SOFT_RSTN_MCU_CLR               (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1-1))
+#define AON_CMU_SOFT_RSTN_CODEC_CLR             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1-1))
+#define AON_CMU_SOFT_RSTN_WF_CLR                (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_BT_CLR                (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_MCUCPU_CLR            (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_WFCPU_CLR             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1-1))
+#define AON_CMU_SOFT_RSTN_BTCPU_CLR             (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1+1-1))
+#define AON_CMU_GLOBAL_RESETN_CLR               (1 << (AON_ARST_NUM+AON_ORST_NUM+32-8-AON_ARST_NUM-AON_ORST_NUM+1+1+1+1+1+1+1+1-1))
 
 // reg_18
 #define AON_CMU_BYPASS_DIV_BTSYS                (1 << 0)
 #define AON_CMU_CFG_DIV_BTSYS(n)                (((n) & 0x3) << 1)
 #define AON_CMU_CFG_DIV_BTSYS_MASK              (0x3 << 1)
 #define AON_CMU_CFG_DIV_BTSYS_SHIFT             (1)
-#define AON_CMU_SEL_BT_PLL                      (1 << 3)
-#define AON_CMU_EN_BT_2M                        (1 << 4)
-#define AON_CMU_SEL_USB_PLLUSB                  (1 << 5)
-#define AON_CMU_CFG_DIV_USB(n)                  (((n) & 0x7) << 6)
-#define AON_CMU_CFG_DIV_USB_MASK                (0x7 << 6)
-#define AON_CMU_CFG_DIV_USB_SHIFT               (6)
-#define AON_CMU_SEL_USB_OSCX2                   (1 << 9)
-#define AON_CMU_CFG_DIV_PER(n)                  (((n) & 0x3) << 10)
-#define AON_CMU_CFG_DIV_PER_MASK                (0x3 << 10)
-#define AON_CMU_CFG_DIV_PER_SHIFT               (10)
-#define AON_CMU_BYPASS_DIV_PER                  (1 << 12)
-#define AON_CMU_RSTN_DIV_PER                    (1 << 13)
-#define AON_CMU_SEL_OSCX2_DIG                   (1 << 14)
-#define AON_CMU_SEL_X2_PHASE(n)                 (((n) & 0x1F) << 15)
-#define AON_CMU_SEL_X2_PHASE_MASK               (0x1F << 15)
-#define AON_CMU_SEL_X2_PHASE_SHIFT              (15)
-#define AON_CMU_SEL_OSCX4_DIG                   (1 << 20)
-#define AON_CMU_SEL_X4_PHASE(n)                 (((n) & 0x1F) << 21)
-#define AON_CMU_SEL_X4_PHASE_MASK               (0x1F << 21)
-#define AON_CMU_SEL_X4_PHASE_SHIFT              (21)
-#define AON_CMU_PU_MCU_PLLBB_MASK               (1 << 26)
-#define AON_CMU_PU_MCU_PLLUSB_MASK              (1 << 27)
-#define AON_CMU_PU_MCU_PLLA7_MASK               (1 << 28)
-#define AON_CMU_PU_MCU_PLLDSI_MASK              (1 << 29)
+#define AON_CMU_CFG_DIV_BT60M(n)                (((n) & 0x3) << 3)
+#define AON_CMU_CFG_DIV_BT60M_MASK              (0x3 << 3)
+#define AON_CMU_CFG_DIV_BT60M_SHIFT             (3)
+#define AON_CMU_SEL_PLL_SYS(n)                  (((n) & 0x3) << 5)
+#define AON_CMU_SEL_PLL_SYS_MASK                (0x3 << 5)
+#define AON_CMU_SEL_PLL_SYS_SHIFT               (5)
+#define AON_CMU_SEL_PLL_AUD(n)                  (((n) & 0x3) << 7)
+#define AON_CMU_SEL_PLL_AUD_MASK                (0x3 << 7)
+#define AON_CMU_SEL_PLL_AUD_SHIFT               (7)
+#define AON_CMU_SEL_OSCX2_DIG                   (1 << 9)
+#define AON_CMU_SEL_X2_PHASE(n)                 (((n) & 0x1F) << 10)
+#define AON_CMU_SEL_X2_PHASE_MASK               (0x1F << 10)
+#define AON_CMU_SEL_X2_PHASE_SHIFT              (10)
+#define AON_CMU_SEL_X4_SYS                      (1 << 15)
+#define AON_CMU_SEL_X4_AUD                      (1 << 16)
+#define AON_CMU_SEL_X4_USB                      (1 << 17)
+#define AON_CMU_SEL_X4_PHASE(n)                 (((n) & 0x1F) << 18)
+#define AON_CMU_SEL_X4_PHASE_MASK               (0x1F << 18)
+#define AON_CMU_SEL_X4_PHASE_SHIFT              (18)
+#define AON_CMU_SEL_X4_DIG                      (1 << 23)
+#define AON_CMU_CFG_DIV_PER(n)                  (((n) & 0x3) << 24)
+#define AON_CMU_CFG_DIV_PER_MASK                (0x3 << 24)
+#define AON_CMU_CFG_DIV_PER_SHIFT               (24)
+#define AON_CMU_BYPASS_DIV_PER                  (1 << 26)
+#define AON_CMU_SEL_32K_TIMER                   (1 << 27)
+#define AON_CMU_SEL_32K_WDT                     (1 << 28)
+#define AON_CMU_SEL_TIMER_FAST                  (1 << 29)
+#define AON_CMU_LPU_AUTO_SWITCH26               (1 << 30)
+#define AON_CMU_EN_MCU_WDG_RESET                (1 << 31)
 
 // reg_1c
 #define AON_CMU_EN_CLK_OUT                      (1 << 0)
-#define AON_CMU_SEL_CLK_OUT(n)                  (((n) & 0x7) << 1)
-#define AON_CMU_SEL_CLK_OUT_MASK                (0x7 << 1)
+#define AON_CMU_SEL_CLK_OUT(n)                  (((n) & 0x3) << 1)
+#define AON_CMU_SEL_CLK_OUT_MASK                (0x3 << 1)
 #define AON_CMU_SEL_CLK_OUT_SHIFT               (1)
-#define AON_CMU_CFG_CLK_OUT(n)                  (((n) & 0x1F) << 4)
-#define AON_CMU_CFG_CLK_OUT_MASK                (0x1F << 4)
-#define AON_CMU_CFG_CLK_OUT_SHIFT               (4)
-#define AON_CMU_CFG_DIV_DCDC(n)                 (((n) & 0xF) << 9)
-#define AON_CMU_CFG_DIV_DCDC_MASK               (0xF << 9)
-#define AON_CMU_CFG_DIV_DCDC_SHIFT              (9)
-#define AON_CMU_BYPASS_DIV_DCDC                 (1 << 13)
-#define AON_CMU_SEL_DCDC_OSC                    (1 << 14)
-#define AON_CMU_SEL_DCDC_PLL                    (1 << 15)
-#define AON_CMU_CLK_DCDC_DRV(n)                 (((n) & 0x3) << 16)
-#define AON_CMU_CLK_DCDC_DRV_MASK               (0x3 << 16)
-#define AON_CMU_CLK_DCDC_DRV_SHIFT              (16)
-#define AON_CMU_SEL_DCDC_PHASE0(n)              (((n) & 0x1F) << 18)
-#define AON_CMU_SEL_DCDC_PHASE0_MASK            (0x1F << 18)
-#define AON_CMU_SEL_DCDC_PHASE0_SHIFT           (18)
+#define AON_CMU_CFG_CLK_OUT(n)                  (((n) & 0xF) << 3)
+#define AON_CMU_CFG_CLK_OUT_MASK                (0xF << 3)
+#define AON_CMU_CFG_CLK_OUT_SHIFT               (3)
+#define AON_CMU_CFG_DIV_DCDC(n)                 (((n) & 0xF) << 7)
+#define AON_CMU_CFG_DIV_DCDC_MASK               (0xF << 7)
+#define AON_CMU_CFG_DIV_DCDC_SHIFT              (7)
+#define AON_CMU_BYPASS_DIV_DCDC                 (1 << 11)
+#define AON_CMU_SEL_DCDC_PLL                    (1 << 12)
+#define AON_CMU_SEL_DCDC_OSCX2                  (1 << 13)
+#define AON_CMU_CLK_DCDC_DRV(n)                 (((n) & 0x3) << 14)
+#define AON_CMU_CLK_DCDC_DRV_MASK               (0x3 << 14)
+#define AON_CMU_CLK_DCDC_DRV_SHIFT              (14)
+#define AON_CMU_EN_VOD_IIR                      (1 << 16)
+#define AON_CMU_EN_VOD_RS                       (1 << 17)
+#define AON_CMU_SEL_X4_FLS                      (1 << 18)
 
 // reg_20
 #define AON_CMU_WRITE_UNLOCK_H                  (1 << 0)
@@ -233,10 +272,10 @@ struct AONCMU_T {
 #define AON_CMU_SOFT_BOOT_MODE_SHIFT            (4)
 
 // reg_3c
-#define AON_CMU_SEL_MCU_PLLBB_PS                (1 << 0)
-#define AON_CMU_SEL_MCU_PLLUSB                  (1 << 1)
-#define AON_CMU_SEL_MCU_PLLA7USB                (1 << 2)
-#define AON_CMU_RSTN_DIV_FLS                    (1 << 3)
+#define AON_CMU_RESERVED(n)                     (((n) & 0xFFFFFFFF) << 0)
+#define AON_CMU_RESERVED_MASK                   (0xFFFFFFFF << 0)
+#define AON_CMU_RESERVED_SHIFT                  (0)
+#define AON_CMU_OSC_TO_DIG_X4                   (1 << 1)
 
 // reg_40
 #define AON_CMU_MANUAL_ACLK_ENABLE(n)           (((n) & 0xFFFFFFFF) << 0)
@@ -263,30 +302,29 @@ struct AONCMU_T {
 #define AON_CMU_MODE_OCLK_SHIFT                 (AON_ACLK_NUM)
 
 // reg_4c
-#define AON_CMU_SEL_AON_OSC                     (1 << 0)
-#define AON_CMU_SEL_AON_OSCX2                   (1 << 1)
-#define AON_CMU_SEL_AON_SPI_OSCX2               (1 << 2)
-#define AON_CMU_SEL_CODEC_ANA_2                 (1 << 3)
-#define AON_CMU_SEL_CODEC_OSC_2                 (1 << 4)
-#define AON_CMU_SEL_CODEC_OSC                   (1 << 5)
-#define AON_CMU_SEL_CODECHCLK_OSCX2             (1 << 6)
-#define AON_CMU_SEL_CODECHCLK_PLL               (1 << 7)
-#define AON_CMU_SEL_CODECHCLK_MCU               (1 << 8)
-#define AON_CMU_EN_I2S_MCLK                     (1 << 9)
-#define AON_CMU_SEL_I2S_MCLK(n)                 (((n) & 0xF) << 10)
-#define AON_CMU_SEL_I2S_MCLK_MASK               (0xF << 10)
-#define AON_CMU_SEL_I2S_MCLK_SHIFT              (10)
+#define AON_CMU_SEL_CLK_OSC                     (1 << 0)
+#define AON_CMU_SEL_CLK_OSCX2                   (1 << 1)
+#define AON_CMU_CFG_DIV_CODEC(n)                (((n) & 0x1F) << 2)
+#define AON_CMU_CFG_DIV_CODEC_MASK              (0x1F << 2)
+#define AON_CMU_CFG_DIV_CODEC_SHIFT             (2)
+#define AON_CMU_SEL_OSC_CODEC                   (1 << 7)
+#define AON_CMU_SEL_OSCX2_CODECHCLK             (1 << 8)
+#define AON_CMU_SEL_PLL_CODECHCLK               (1 << 9)
+#define AON_CMU_SEL_CODEC_HCLK_AON              (1 << 10)
+#define AON_CMU_BYPASS_LOCK_PLLUSB              (1 << 11)
+#define AON_CMU_BYPASS_LOCK_PLLBB               (1 << 12)
+#define AON_CMU_BYPASS_LOCK_PLLAUD              (1 << 13)
 #define AON_CMU_POL_SPI_CS(n)                   (((n) & 0x7) << 14)
 #define AON_CMU_POL_SPI_CS_MASK                 (0x7 << 14)
 #define AON_CMU_POL_SPI_CS_SHIFT                (14)
 #define AON_CMU_CFG_SPI_ARB(n)                  (((n) & 0x7) << 17)
 #define AON_CMU_CFG_SPI_ARB_MASK                (0x7 << 17)
 #define AON_CMU_CFG_SPI_ARB_SHIFT               (17)
-#define AON_CMU_PU_FLASH0_IO                     (1 << 20)
-#define AON_CMU_EN_VAD_IIR                      (1 << 21)
-#define AON_CMU_EN_VAD_RS                       (1 << 22)
-#define AON_CMU_EN_MCU_PLLBB_MASK               (1 << 23)
-#define AON_CMU_EN_MCU_PLLUSB_MASK              (1 << 24)
+#define AON_CMU_PU_FLASH_IO                     (1 << 20)
+#define AON_CMU_POR_SLEEP_MODE                  (1 << 21)
+#define AON_CMU_LOCK_PLLBB                      (1 << 22)
+#define AON_CMU_LOCK_PLLUSB                     (1 << 23)
+#define AON_CMU_LOCK_PLLAUD                     (1 << 24)
 
 // reg_50
 #define AON_CMU_CFG_DIV_TIMER0(n)               (((n) & 0xFFFF) << 0)
@@ -300,57 +338,70 @@ struct AONCMU_T {
 #define AON_CMU_CFG_DIV_PWM0(n)                 (((n) & 0xFFF) << 0)
 #define AON_CMU_CFG_DIV_PWM0_MASK               (0xFFF << 0)
 #define AON_CMU_CFG_DIV_PWM0_SHIFT              (0)
-#define AON_CMU_SEL_PWM0_OSC                    (1 << 12)
-#define AON_CMU_EN_CLK_PWM0_OSC                 (1 << 13)
+#define AON_CMU_SEL_OSC_PWM0                    (1 << 12)
+#define AON_CMU_EN_OSC_PWM0                     (1 << 13)
 #define AON_CMU_CFG_DIV_PWM1(n)                 (((n) & 0xFFF) << 16)
 #define AON_CMU_CFG_DIV_PWM1_MASK               (0xFFF << 16)
 #define AON_CMU_CFG_DIV_PWM1_SHIFT              (16)
-#define AON_CMU_SEL_PWM1_OSC                    (1 << 28)
-#define AON_CMU_EN_CLK_PWM1_OSC                 (1 << 29)
+#define AON_CMU_SEL_OSC_PWM1                    (1 << 28)
+#define AON_CMU_EN_OSC_PWM1                     (1 << 29)
 
 // reg_58
 #define AON_CMU_CFG_DIV_PWM2(n)                 (((n) & 0xFFF) << 0)
 #define AON_CMU_CFG_DIV_PWM2_MASK               (0xFFF << 0)
 #define AON_CMU_CFG_DIV_PWM2_SHIFT              (0)
-#define AON_CMU_SEL_PWM2_OSC                    (1 << 12)
-#define AON_CMU_EN_CLK_PWM2_OSC                 (1 << 13)
+#define AON_CMU_SEL_OSC_PWM2                    (1 << 12)
+#define AON_CMU_EN_OSC_PWM2                     (1 << 13)
 #define AON_CMU_CFG_DIV_PWM3(n)                 (((n) & 0xFFF) << 16)
 #define AON_CMU_CFG_DIV_PWM3_MASK               (0xFFF << 16)
 #define AON_CMU_CFG_DIV_PWM3_SHIFT              (16)
-#define AON_CMU_SEL_PWM3_OSC                    (1 << 28)
-#define AON_CMU_EN_CLK_PWM3_OSC                 (1 << 29)
+#define AON_CMU_SEL_OSC_PWM3                    (1 << 28)
+#define AON_CMU_EN_OSC_PWM3                     (1 << 29)
 
 // reg_5c
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP0(n)        (((n) & 0x7) << 0)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP0_MASK      (0x7 << 0)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP0_SHIFT     (0)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP1(n)        (((n) & 0x7) << 3)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP1_MASK      (0x7 << 3)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP1_SHIFT     (3)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP2(n)        (((n) & 0x7) << 6)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP2_MASK      (0x7 << 6)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP2_SHIFT     (6)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP3(n)        (((n) & 0x7) << 9)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP3_MASK      (0x7 << 9)
-#define AON_CMU_EXT_LNA_AT_GAIN_STEP3_SHIFT     (9)
-#define AON_CMU_EXT_LNA_ENABLE                  (1 << 12)
-#define AON_CMU_EXT_LNA_ENABLE_DR               (1 << 13)
-#define AON_CMU_EXT_LNA_EN_BYPASS_RXON          (1 << 14)
-#define AON_CMU_FEM_SWTCH_WF_MUX_CFG(n)         (((n) & 0x3) << 15)
-#define AON_CMU_FEM_SWTCH_WF_MUX_CFG_MASK       (0x3 << 15)
-#define AON_CMU_FEM_SWTCH_WF_MUX_CFG_SHIFT      (15)
+#define AON_CMU_RAM_EMA(n)                      (((n) & 0x7) << 0)
+#define AON_CMU_RAM_EMA_MASK                    (0x7 << 0)
+#define AON_CMU_RAM_EMA_SHIFT                   (0)
+#define AON_CMU_RAM_EMAW(n)                     (((n) & 0x3) << 3)
+#define AON_CMU_RAM_EMAW_MASK                   (0x3 << 3)
+#define AON_CMU_RAM_EMAW_SHIFT                  (3)
+#define AON_CMU_RAM_WABL                        (1 << 5)
+#define AON_CMU_RAM_WABLM(n)                    (((n) & 0x3) << 6)
+#define AON_CMU_RAM_WABLM_MASK                  (0x3 << 6)
+#define AON_CMU_RAM_WABLM_SHIFT                 (6)
+#define AON_CMU_RAM_RET1N0(n)                   (((n) & 0x7) << 8)
+#define AON_CMU_RAM_RET1N0_MASK                 (0x7 << 8)
+#define AON_CMU_RAM_RET1N0_SHIFT                (8)
+#define AON_CMU_RAM_RET2N0(n)                   (((n) & 0x7) << 11)
+#define AON_CMU_RAM_RET2N0_MASK                 (0x7 << 11)
+#define AON_CMU_RAM_RET2N0_SHIFT                (11)
+#define AON_CMU_RAM_PGEN0(n)                    (((n) & 0x7) << 14)
+#define AON_CMU_RAM_PGEN0_MASK                  (0x7 << 14)
+#define AON_CMU_RAM_PGEN0_SHIFT                 (14)
+#define AON_CMU_RAM_RET1N1(n)                   (((n) & 0x7) << 17)
+#define AON_CMU_RAM_RET1N1_MASK                 (0x7 << 17)
+#define AON_CMU_RAM_RET1N1_SHIFT                (17)
+#define AON_CMU_RAM_RET2N1(n)                   (((n) & 0x7) << 20)
+#define AON_CMU_RAM_RET2N1_MASK                 (0x7 << 20)
+#define AON_CMU_RAM_RET2N1_SHIFT                (20)
+#define AON_CMU_RAM_PGEN1(n)                    (((n) & 0x7) << 23)
+#define AON_CMU_RAM_PGEN1_MASK                  (0x7 << 23)
+#define AON_CMU_RAM_PGEN1_SHIFT                 (23)
+#define AON_CMU_RAM_EMAS                        (1 << 26)
 
 // reg_64
 #define AON_CMU_CFG_DIV_PCM(n)                  (((n) & 0x1FFF) << 0)
 #define AON_CMU_CFG_DIV_PCM_MASK                (0x1FFF << 0)
 #define AON_CMU_CFG_DIV_PCM_SHIFT               (0)
-#define AON_CMU_EN_CLK_PLL_PCM                  (1 << 13)
+#define AON_CMU_SEL_I2S_MCLK(n)                 (((n) & 0x7) << 13)
+#define AON_CMU_SEL_I2S_MCLK_MASK               (0x7 << 13)
+#define AON_CMU_SEL_I2S_MCLK_SHIFT              (13)
 #define AON_CMU_CFG_DIV_I2S0(n)                 (((n) & 0x1FFF) << 16)
 #define AON_CMU_CFG_DIV_I2S0_MASK               (0x1FFF << 16)
 #define AON_CMU_CFG_DIV_I2S0_SHIFT              (16)
 #define AON_CMU_EN_CLK_PLL_I2S0                 (1 << 29)
-#define AON_CMU_SEL_AUD_PLLUSB                  (1 << 30)
-#define AON_CMU_SEL_AUD_X4                      (1 << 31)
+#define AON_CMU_EN_CLK_PLL_PCM                  (1 << 30)
+#define AON_CMU_EN_I2S_MCLK                     (1 << 31)
 
 // reg_68
 #define AON_CMU_CFG_DIV_SPDIF0(n)               (((n) & 0x1FFF) << 0)
@@ -383,15 +434,15 @@ struct AONCMU_T {
 #define AON_CMU_CFG_DIV_CODECIIR(n)             (((n) & 0xF) << 0)
 #define AON_CMU_CFG_DIV_CODECIIR_MASK           (0xF << 0)
 #define AON_CMU_CFG_DIV_CODECIIR_SHIFT          (0)
-#define AON_CMU_SEL_CODECIIR_OSC                (1 << 4)
-#define AON_CMU_SEL_CODECIIR_OSCX2              (1 << 5)
+#define AON_CMU_SEL_OSC_CODECIIR                (1 << 4)
+#define AON_CMU_SEL_OSCX2_CODECIIR              (1 << 5)
 #define AON_CMU_BYPASS_DIV_CODECIIR             (1 << 6)
-#define AON_CMU_CFG_DIV_CODECRS0(n)             (((n) & 0xF) << 8)
-#define AON_CMU_CFG_DIV_CODECRS0_MASK           (0xF << 8)
-#define AON_CMU_CFG_DIV_CODECRS0_SHIFT          (8)
-#define AON_CMU_SEL_CODECRS0_OSC                (1 << 12)
-#define AON_CMU_SEL_CODECRS0_OSCX2              (1 << 13)
-#define AON_CMU_BYPASS_DIV_CODECRS0             (1 << 14)
+#define AON_CMU_CFG_DIV_CODECRS(n)              (((n) & 0xF) << 8)
+#define AON_CMU_CFG_DIV_CODECRS_MASK            (0xF << 8)
+#define AON_CMU_CFG_DIV_CODECRS_SHIFT           (8)
+#define AON_CMU_SEL_OSC_CODECRS                 (1 << 12)
+#define AON_CMU_SEL_OSCX2_CODECRS               (1 << 13)
+#define AON_CMU_BYPASS_DIV_CODECRS              (1 << 14)
 
 // reg_7c
 #define AON_CMU_OTP_WR_LOCK(n)                  (((n) & 0xFFFF) << 0)
@@ -445,10 +496,10 @@ struct AONCMU_T {
 #define AON_ARST_PWM                    (1 << 4)
 #define AON_ACLK_TIMER                  (1 << 5)
 #define AON_ARST_TIMER                  (1 << 5)
-#define AON_ACLK_PSC                    (1 << 10)
-#define AON_ARST_PSC                    (1 << 10)
-#define AON_ACLK_IOMUX                  (1 << 6)
-#define AON_ARST_IOMUX                  (1 << 6)
+#define AON_ACLK_PSC                    (1 << 6)
+#define AON_ARST_PSC                    (1 << 6)
+#define AON_ACLK_IOMUX                  (1 << 7)
+#define AON_ARST_IOMUX                  (1 << 7)
 #define AON_ACLK_APBC                   (1 << 8)
 #define AON_ARST_APBC                   (1 << 8)
 #define AON_ACLK_H2H_MCU                (1 << 9)

platform/hal/best2300p/reg_cmu_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/reg_cmu_best2300p.h bes/platform/hal/best2300p/reg_cmu_best2300p.h
index c0039582067..4404306c922 100644
--- a/platform/hal/best2300p/reg_cmu_best2300p.h
+++ b/platform/hal/best2300p/reg_cmu_best2300p.h
@@ -27,7 +27,7 @@ struct CMU_T {
     __IO uint32_t HCLK_MODE;        // 0x18
     __IO uint32_t PCLK_MODE;        // 0x1C
     __IO uint32_t OCLK_MODE;        // 0x20
-    __IO uint32_t RESERVED_024;     // 0x24
+    __IO uint32_t RAM_CFG3;         // 0x24
     __IO uint32_t HRESET_PULSE;     // 0x28
     __IO uint32_t PRESET_PULSE;     // 0x2C
     __IO uint32_t ORESET_PULSE;     // 0x30
@@ -126,13 +126,32 @@ struct CMU_T {
 #define CMU_MODE_OCLK_MASK                      (0xFFFFFFFF << 0)
 #define CMU_MODE_OCLK_SHIFT                     (0)
 
+// reg_24
+#define CMU_RAM3_RET1N0(n)                      (((n) & 0x1F) << 0)
+#define CMU_RAM3_RET1N0_MASK                    (0x1F << 0)
+#define CMU_RAM3_RET1N0_SHIFT                   (0)
+#define CMU_RAM3_RET2N0(n)                      (((n) & 0x1F) << 5)
+#define CMU_RAM3_RET2N0_MASK                    (0x1F << 5)
+#define CMU_RAM3_RET2N0_SHIFT                   (5)
+#define CMU_RAM3_PGEN0(n)                       (((n) & 0x1F) << 10)
+#define CMU_RAM3_PGEN0_MASK                     (0x1F << 10)
+#define CMU_RAM3_PGEN0_SHIFT                    (10)
+#define CMU_RAM3_RET1N1(n)                      (((n) & 0x1F) << 15)
+#define CMU_RAM3_RET1N1_MASK                    (0x1F << 15)
+#define CMU_RAM3_RET1N1_SHIFT                   (15)
+#define CMU_RAM3_RET2N1(n)                      (((n) & 0x1F) << 20)
+#define CMU_RAM3_RET2N1_MASK                    (0x1F << 20)
+#define CMU_RAM3_RET2N1_SHIFT                   (20)
+#define CMU_RAM3_PGEN1(n)                       (((n) & 0x1F) << 25)
+#define CMU_RAM3_PGEN1_MASK                     (0x1F << 25)
+#define CMU_RAM3_PGEN1_SHIFT                    (25)
 
 // reg_28
 #define CMU_HRESETN_PULSE(n)                    (((n) & 0xFFFFFFFF) << 0)
 #define CMU_HRESETN_PULSE_MASK                  (0xFFFFFFFF << 0)
 #define CMU_HRESETN_PULSE_SHIFT                 (0)
 
-#define SYS_PRST_NUM                            26
+#define SYS_PRST_NUM                            19
 
 // reg_2c
 #define CMU_PRESETN_PULSE(n)                    (((n) & 0xFFFFFFFF) << 0)
@@ -218,7 +237,7 @@ struct CMU_T {
 #define CMU_DEEPSLEEP_START                     (1 << 28)
 #define CMU_DEEPSLEEP_MODE                      (1 << 29)
 #define CMU_PU_OSC                              (1 << 30)
-#define CMU_WAKEDOWN_DEEPSLEEP_L                (1 << 31)
+#define CMU_WAKEUP_DEEPSLEEP_L                  (1 << 31)
 
 // reg_5c
 #define CMU_CFG_DIV_SDMMC(n)                    (((n) & 0xF) << 0)
@@ -244,32 +263,32 @@ struct CMU_T {
 #define CMU_JTAG_SEL_CP                         (1 << 25)
 
 // reg_60
-#define CMU_RSTN_DIV_MCU_ENABLE                 (1 << 0)
-#define CMU_BYPASS_DIV_MCU_ENABLE               (1 << 1)
-#define CMU_SEL_MCU_OSC_4_ENABLE                (1 << 2)
-#define CMU_SEL_MCU_OSC_2_ENABLE                (1 << 3)
-#define CMU_SEL_MCU_OSCX4_ENABLE                (1 << 4)
-#define CMU_SEL_MCU_SLOW_ENABLE                 (1 << 5)
-#define CMU_SEL_MCU_FAST_ENABLE                 (1 << 6)
-#define CMU_SEL_MCU_PLL_ENABLE                  (1 << 7)
-#define CMU_RSTN_DIV_A7_ENABLE                  (1 << 8)
-#define CMU_BYPASS_DIV_A7_ENABLE                (1 << 9)
-#define CMU_SEL_A7_OSC_4_ENABLE                 (1 << 10)
-#define CMU_SEL_A7_OSC_2_ENABLE                 (1 << 11)
+#define CMU_RSTN_DIV_FLS_ENABLE                 (1 << 0)
+#define CMU_SEL_OSC_FLS_ENABLE                  (1 << 1)
+#define CMU_SEL_OSCX2_FLS_ENABLE                (1 << 2)
+#define CMU_SEL_PLL_FLS_ENABLE                  (1 << 3)
+#define CMU_BYPASS_DIV_FLS_ENABLE               (1 << 4)
+#define CMU_RSTN_DIV_SYS_ENABLE                 (1 << 5)
+#define CMU_SEL_OSC_SYS_ENABLE                  (1 << 6)
+#define CMU_SEL_OSCX2_SYS_ENABLE                (1 << 7)
+#define CMU_SEL_PLL_SYS_ENABLE                  (1 << 8)
+#define CMU_BYPASS_DIV_SYS_ENABLE               (1 << 9)
+#define CMU_EN_PLL_ENABLE                       (1 << 10)
+#define CMU_PU_PLL_ENABLE                       (1 << 11)
 
 // reg_64
-#define CMU_RSTN_DIV_MCU_DISABLE                (1 << 0)
-#define CMU_BYPASS_DIV_MCU_DISABLE              (1 << 1)
-#define CMU_SEL_MCU_OSC_4_DISABLE               (1 << 2)
-#define CMU_SEL_MCU_OSC_2_DISABLE               (1 << 3)
-#define CMU_SEL_MCU_OSCX4_DISABLE               (1 << 4)
-#define CMU_SEL_MCU_SLOW_DISABLE                (1 << 5)
-#define CMU_SEL_MCU_FAST_DISABLE                (1 << 6)
-#define CMU_SEL_MCU_PLL_DISABLE                 (1 << 7)
-#define CMU_RSTN_DIV_A7_DISABLE                 (1 << 8)
-#define CMU_BYPASS_DIV_A7_DISABLE               (1 << 9)
-#define CMU_SEL_A7_OSC_4_DISABLE                (1 << 10)
-#define CMU_SEL_A7_OSC_2_DISABLE                (1 << 11)
+#define CMU_RSTN_DIV_FLS_DISABLE                (1 << 0)
+#define CMU_SEL_OSC_FLS_DISABLE                 (1 << 1)
+#define CMU_SEL_OSCX2_FLS_DISABLE               (1 << 2)
+#define CMU_SEL_PLL_FLS_DISABLE                 (1 << 3)
+#define CMU_BYPASS_DIV_FLS_DISABLE              (1 << 4)
+#define CMU_RSTN_DIV_SYS_DISABLE                (1 << 5)
+#define CMU_SEL_OSC_SYS_DISABLE                 (1 << 6)
+#define CMU_SEL_OSCX2_SYS_DISABLE               (1 << 7)
+#define CMU_SEL_PLL_SYS_DISABLE                 (1 << 8)
+#define CMU_BYPASS_DIV_SYS_DISABLE              (1 << 9)
+#define CMU_EN_PLL_DISABLE                      (1 << 10)
+#define CMU_PU_PLL_DISABLE                      (1 << 11)
 
 // reg_68
 #define CMU_ADMA_CH15_REQ_IDX(n)                (((n) & 0x3F) << 0)
@@ -281,39 +300,37 @@ struct CMU_T {
 #define CMU_ROM_EMA_MASK                        (0x7 << 0)
 #define CMU_ROM_EMA_SHIFT                       (0)
 #define CMU_ROM_KEN                             (1 << 3)
-#define CMU_ROM_PGEN(n)                         (((n) & 0x3) << 4)
-#define CMU_ROM_PGEN_MASK                       (0x3 << 4)
+#define CMU_ROM_PGEN(n)                         (((n) & 0x7) << 4)
+#define CMU_ROM_PGEN_MASK                       (0x7 << 4)
 #define CMU_ROM_PGEN_SHIFT                      (4)
-#define CMU_RAM_EMA(n)                          (((n) & 0x7) << 6)
-#define CMU_RAM_EMA_MASK                        (0x7 << 6)
-#define CMU_RAM_EMA_SHIFT                       (6)
-#define CMU_RAM_EMAW(n)                         (((n) & 0x3) << 9)
-#define CMU_RAM_EMAW_MASK                       (0x3 << 9)
-#define CMU_RAM_EMAW_SHIFT                      (9)
-#define CMU_RAM_EMAS                            (1 << 11)
+#define CMU_RAM_EMA(n)                          (((n) & 0x7) << 7)
+#define CMU_RAM_EMA_MASK                        (0x7 << 7)
+#define CMU_RAM_EMA_SHIFT                       (7)
+#define CMU_RAM_EMAW(n)                         (((n) & 0x3) << 10)
+#define CMU_RAM_EMAW_MASK                       (0x3 << 10)
+#define CMU_RAM_EMAW_SHIFT                      (10)
 #define CMU_RAM_WABL                            (1 << 12)
 #define CMU_RAM_WABLM(n)                        (((n) & 0x3) << 13)
 #define CMU_RAM_WABLM_MASK                      (0x3 << 13)
 #define CMU_RAM_WABLM_SHIFT                     (13)
-#define CMU_RAM_RAWL                            (1 << 15)
-#define CMU_RAM_RAWLM(n)                        (((n) & 0x3) << 16)
-#define CMU_RAM_RAWLM_MASK                      (0x3 << 16)
-#define CMU_RAM_RAWLM_SHIFT                     (16)
-#define CMU_RF_EMA(n)                           (((n) & 0x7) << 18)
-#define CMU_RF_EMA_MASK                         (0x7 << 18)
-#define CMU_RF_EMA_SHIFT                        (18)
-#define CMU_RF_EMAW(n)                          (((n) & 0x3) << 21)
-#define CMU_RF_EMAW_MASK                        (0x3 << 21)
-#define CMU_RF_EMAW_SHIFT                       (21)
-#define CMU_RF_EMAS                             (1 << 23)
-#define CMU_RF_WABL                             (1 << 24)
-#define CMU_RF_WABLM(n)                         (((n) & 0x3) << 25)
-#define CMU_RF_WABLM_MASK                       (0x3 << 25)
-#define CMU_RF_WABLM_SHIFT                      (25)
-#define CMU_RF_RAWL                             (1 << 27)
-#define CMU_RF_RAWLM(n)                         (((n) & 0x3) << 28)
-#define CMU_RF_RAWLM_MASK                       (0x3 << 28)
-#define CMU_RF_RAWLM_SHIFT                      (28)
+#define CMU_RAM_EMAS                            (1 << 15)
+#define CMU_RF_EMA(n)                           (((n) & 0x7) << 16)
+#define CMU_RF_EMA_MASK                         (0x7 << 16)
+#define CMU_RF_EMA_SHIFT                        (16)
+#define CMU_RF_EMAW(n)                          (((n) & 0x3) << 19)
+#define CMU_RF_EMAW_MASK                        (0x3 << 19)
+#define CMU_RF_EMAW_SHIFT                       (19)
+#define CMU_RF_WABL                             (1 << 21)
+#define CMU_RF_WABLM(n)                         (((n) & 0x3) << 22)
+#define CMU_RF_WABLM_MASK                       (0x3 << 22)
+#define CMU_RF_WABLM_SHIFT                      (22)
+#define CMU_RF_EMAS                             (1 << 24)
+#define CMU_RF_RET1N0                           (1 << 25)
+#define CMU_RF_RET2N0                           (1 << 26)
+#define CMU_RF_PGEN0                            (1 << 27)
+#define CMU_RF_RET1N1                           (1 << 28)
+#define CMU_RF_RET2N1                           (1 << 29)
+#define CMU_RF_PGEN1                            (1 << 30)
 
 // reg_70
 #define CMU_CFG_DIV_UART0(n)                    (((n) & 0x1F) << 0)
@@ -360,14 +377,26 @@ struct CMU_T {
 #define CMU_POL_CLK_I2S1_OUT                    (1 << 26)
 
 // reg_78
-#define CMU_RAM_RET1N0(n)                       (((n) & 0xFFFFFFFF) << 0)
-#define CMU_RAM_RET1N0_MASK                     (0xFFFFFFFF << 0)
+#define CMU_RAM_RET1N0(n)                       (((n) & 0x3FF) << 0)
+#define CMU_RAM_RET1N0_MASK                     (0x3FF << 0)
 #define CMU_RAM_RET1N0_SHIFT                    (0)
+#define CMU_RAM_RET2N0(n)                       (((n) & 0x3FF) << 10)
+#define CMU_RAM_RET2N0_MASK                     (0x3FF << 10)
+#define CMU_RAM_RET2N0_SHIFT                    (10)
+#define CMU_RAM_PGEN0(n)                        (((n) & 0x3FF) << 20)
+#define CMU_RAM_PGEN0_MASK                      (0x3FF << 20)
+#define CMU_RAM_PGEN0_SHIFT                     (20)
 
 // reg_7c
-#define CMU_RAM_RET1N1(n)                       (((n) & 0xFFFFFFFF) << 0)
-#define CMU_RAM_RET1N1_MASK                     (0xFFFFFFFF << 0)
+#define CMU_RAM_RET1N1(n)                       (((n) & 0x3FF) << 0)
+#define CMU_RAM_RET1N1_MASK                     (0x3FF << 0)
 #define CMU_RAM_RET1N1_SHIFT                    (0)
+#define CMU_RAM_RET2N1(n)                       (((n) & 0x3FF) << 10)
+#define CMU_RAM_RET2N1_MASK                     (0x3FF << 10)
+#define CMU_RAM_RET2N1_SHIFT                    (10)
+#define CMU_RAM_PGEN1(n)                        (((n) & 0x3FF) << 20)
+#define CMU_RAM_PGEN1_MASK                      (0x3FF << 20)
+#define CMU_RAM_PGEN1_SHIFT                     (20)
 
 // reg_80
 #define CMU_WRITE_UNLOCK_H                      (1 << 0)
@@ -379,8 +408,8 @@ struct CMU_T {
 #define CMU_WAKEUP_IRQ_MASK0_SHIFT              (0)
 
 // reg_88
-#define CMU_WAKEUP_IRQ_MASK1(n)                 (((n) & 0xFFFFFFFF) << 0)
-#define CMU_WAKEUP_IRQ_MASK1_MASK               (0xFFFFFFFF << 0)
+#define CMU_WAKEUP_IRQ_MASK1(n)                 (((n) & 0xFFFFF) << 0)
+#define CMU_WAKEUP_IRQ_MASK1_MASK               (0xFFFFF << 0)
 #define CMU_WAKEUP_IRQ_MASK1_SHIFT              (0)
 
 // reg_8c
@@ -446,35 +475,38 @@ struct CMU_T {
 #define CMU_BT_ALLIRQ_MASK_CLR                  (1 << 4)
 
 // reg_a8
-#define CMU_CFG_DIV_MCU(n)                      (((n) & 0x3) << 0)
-#define CMU_CFG_DIV_MCU_MASK                    (0x3 << 0)
-#define CMU_CFG_DIV_MCU_SHIFT                   (0)
-#define CMU_SEL_SMP_MCU(n)                      (((n) & 0x7) << 2)
-#define CMU_SEL_SMP_MCU_MASK                    (0x7 << 2)
+#define CMU_CFG_DIV_SYS(n)                      (((n) & 0x3) << 0)
+#define CMU_CFG_DIV_SYS_MASK                    (0x3 << 0)
+#define CMU_CFG_DIV_SYS_SHIFT                   (0)
+#define CMU_SEL_SMP_MCU(n)                      (((n) & 0x3) << 2)
+#define CMU_SEL_SMP_MCU_MASK                    (0x3 << 2)
 #define CMU_SEL_SMP_MCU_SHIFT                   (2)
-#define CMU_SEL_USB_6M                          (1 << 5)
-#define CMU_SEL_USB_SRC(n)                      (((n) & 0x7) << 6)
-#define CMU_SEL_USB_SRC_MASK                    (0x7 << 6)
-#define CMU_SEL_USB_SRC_SHIFT                   (6)
-#define CMU_POL_CLK_USB                         (1 << 9)
-#define CMU_USB_ID                              (1 << 10)
-#define CMU_CFG_DIV_PCLK(n)                     (((n) & 0x3) << 11)
-#define CMU_CFG_DIV_PCLK_MASK                   (0x3 << 11)
-#define CMU_CFG_DIV_PCLK_SHIFT                  (11)
-#define CMU_CFG_DIV_SPI0(n)                     (((n) & 0xF) << 13)
-#define CMU_CFG_DIV_SPI0_MASK                   (0xF << 13)
-#define CMU_CFG_DIV_SPI0_SHIFT                  (13)
-#define CMU_SEL_OSCX2_SPI0                      (1 << 17)
-#define CMU_SEL_PLL_SPI0                        (1 << 18)
-#define CMU_EN_PLL_SPI0                         (1 << 19)
-#define CMU_CFG_DIV_SPI1(n)                     (((n) & 0xF) << 20)
-#define CMU_CFG_DIV_SPI1_MASK                   (0xF << 20)
-#define CMU_CFG_DIV_SPI1_SHIFT                  (20)
-#define CMU_SEL_OSCX2_SPI1                      (1 << 24)
-#define CMU_SEL_PLL_SPI1                        (1 << 25)
-#define CMU_EN_PLL_SPI1                         (1 << 26)
-#define CMU_SEL_OSCX2_SPI2                      (1 << 27)
-#define CMU_DSD_PCM_DMAREQ_SEL                  (1 << 28)
+#define CMU_CFG_DIV_FLS(n)                      (((n) & 0x3) << 4)
+#define CMU_CFG_DIV_FLS_MASK                    (0x3 << 4)
+#define CMU_CFG_DIV_FLS_SHIFT                   (4)
+#define CMU_SEL_USB_6M                          (1 << 6)
+#define CMU_SEL_USB_SRC(n)                      (((n) & 0x7) << 7)
+#define CMU_SEL_USB_SRC_MASK                    (0x7 << 7)
+#define CMU_SEL_USB_SRC_SHIFT                   (7)
+#define CMU_POL_CLK_USB                         (1 << 10)
+#define CMU_USB_ID                              (1 << 11)
+#define CMU_CFG_DIV_PCLK(n)                     (((n) & 0x3) << 12)
+#define CMU_CFG_DIV_PCLK_MASK                   (0x3 << 12)
+#define CMU_CFG_DIV_PCLK_SHIFT                  (12)
+#define CMU_CFG_DIV_SPI0(n)                     (((n) & 0xF) << 14)
+#define CMU_CFG_DIV_SPI0_MASK                   (0xF << 14)
+#define CMU_CFG_DIV_SPI0_SHIFT                  (14)
+#define CMU_SEL_OSCX2_SPI0                      (1 << 18)
+#define CMU_SEL_PLL_SPI0                        (1 << 19)
+#define CMU_EN_PLL_SPI0                         (1 << 20)
+#define CMU_CFG_DIV_SPI1(n)                     (((n) & 0xF) << 21)
+#define CMU_CFG_DIV_SPI1_MASK                   (0xF << 21)
+#define CMU_CFG_DIV_SPI1_SHIFT                  (21)
+#define CMU_SEL_OSCX2_SPI1                      (1 << 25)
+#define CMU_SEL_PLL_SPI1                        (1 << 26)
+#define CMU_EN_PLL_SPI1                         (1 << 27)
+#define CMU_SEL_OSCX2_SPI2                      (1 << 28)
+#define CMU_DSD_PCM_DMAREQ_SEL                  (1 << 29)
 
 // reg_ac
 #define CMU_DMA_HANDSHAKE_SWAP(n)               (((n) & 0xFFFF) << 0)
@@ -490,8 +522,8 @@ struct CMU_T {
 #define CMU_MCU2BT_INTISR_MASK0_SHIFT           (0)
 
 // reg_b4
-#define CMU_MCU2BT_INTISR_MASK1(n)              (((n) & 0xFFFFFFFF) << 0)
-#define CMU_MCU2BT_INTISR_MASK1_MASK            (0xFFFFFFFF << 0)
+#define CMU_MCU2BT_INTISR_MASK1(n)              (((n) & 0xFFFFF) << 0)
+#define CMU_MCU2BT_INTISR_MASK1_MASK            (0xFFFFF << 0)
 #define CMU_MCU2BT_INTISR_MASK1_SHIFT           (0)
 
 // reg_b8
@@ -666,70 +698,68 @@ struct CMU_T {
 #define CMU_DCODE_ACC_SECROM_EN                 (1 << 5)
 
 // MCU System AHB Clocks:
-#define SYS_HCLK_CORE0                  (1 << 0)
-#define SYS_HRST_CORE0                  (1 << 0)
-#define SYS_HCLK_CACHE0                 (1 << 1)
-#define SYS_HRST_CACHE0                 (1 << 1)
-#define SYS_HCLK_CORE1                  (1 << 2)
-#define SYS_HRST_CORE1                  (1 << 2)
-#define SYS_HCLK_CACHE1                 (1 << 3)
-#define SYS_HRST_CACHE1                 (1 << 3)
-#define SYS_HCLK_ADMA                   (1 << 4)
-#define SYS_HRST_ADMA                   (1 << 4)
-#define SYS_HCLK_GDMA                   (1 << 5)
-#define SYS_HRST_GDMA                   (1 << 5)
-#define SYS_HCLK_BCM                    (1 << 6)
-#define SYS_HRST_BCM                    (1 << 6)
-#define SYS_HCLK_USBC                   (1 << 7)
-#define SYS_HRST_USBC                   (1 << 7)
-#define SYS_HCLK_USBH                   (1 << 8)
-#define SYS_HRST_USBH                   (1 << 8)
-#define SYS_HCLK_I2C_SLAVE              (1 << 9)
-#define SYS_HRST_I2C_SLAVE              (1 << 9)
-#define SYS_HCLK_AX2H_A7                (1 << 10)
-#define SYS_HRST_AX2H_A7                (1 << 10)
-#define SYS_HCLK_AH2H_WF                (1 << 11)
-#define SYS_HRST_AH2H_WF                (1 << 11)
-#define SYS_HCLK_AH2H_BT                (1 << 12)
-#define SYS_HRST_AH2H_BT                (1 << 12)
-#define SYS_HCLK_CODEC                  (1 << 13)
-#define SYS_HRST_CODEC                  (1 << 13)
-#define SYS_HCLK_AHB1                   (1 << 14)
-#define SYS_HRST_AHB1                   (1 << 14)
-#define SYS_HCLK_AHB0                   (1 << 15)
-#define SYS_HRST_AHB0                   (1 << 15)
-#define SYS_HCLK_PSRAM1G                (1 << 16)
-#define SYS_HRST_PSRAM1G                (1 << 16)
-#define SYS_HCLK_PSRAM200               (1 << 17)
-#define SYS_HRST_PSRAM200               (1 << 17)
-#define SYS_HCLK_FLASH                  (1 << 18)
-#define SYS_HRST_FLASH                  (1 << 18)
-#define SYS_HCLK_RAM5                   (1 << 19)
-#define SYS_HRST_RAM5                   (1 << 19)
-#define SYS_HCLK_RAM4                   (1 << 20)
-#define SYS_HRST_RAM4                   (1 << 20)
-#define SYS_HCLK_RAM3                   (1 << 21)
-#define SYS_HRST_RAM3                   (1 << 21)
-#define SYS_HCLK_RAM2                   (1 << 22)
-#define SYS_HRST_RAM2                   (1 << 22)
-#define SYS_HCLK_RAM1                   (1 << 23)
-#define SYS_HRST_RAM1                   (1 << 23)
-#define SYS_HCLK_RAM0                   (1 << 24)
-#define SYS_HRST_RAM0                   (1 << 24)
-#define SYS_HCLK_ROM0                   (1 << 25)
-#define SYS_HRST_ROM0                   (1 << 25)
-#define SYS_HCLK_BT_DUMP                (1 << 26)
-#define SYS_HRST_BT_DUMP                (1 << 26)
-#define SYS_HCLK_WF_DUMP                (1 << 27)
-#define SYS_HRST_WF_DUMP                (1 << 27)
-#define SYS_HCLK_SDMMC                  (1 << 28)
-#define SYS_HRST_SDMMC                  (1 << 28)
-#define SYS_HCLK_CHECKSUM               (1 << 29)
-#define SYS_HRST_CHECKSUM               (1 << 29)
-#define SYS_HCLK_CRC                    (1 << 30)
-#define SYS_HRST_CRC                    (1 << 30)
-#define SYS_HCLK_FLASH1                 (1 << 31)
-#define SYS_HRST_FLASH1                 (1 << 31)
+#define SYS_HCLK_MCU                    (1 << 0)
+#define SYS_HRST_MCU                    (1 << 0)
+#define SYS_HCLK_ROM0                   (1 << 1)
+#define SYS_HRST_ROM0                   (1 << 1)
+#define SYS_HCLK_ROM1                   (1 << 2)
+#define SYS_HRST_ROM1                   (1 << 2)
+#define SYS_HCLK_ROM2                   (1 << 3)
+#define SYS_HRST_ROM2                   (1 << 3)
+#define SYS_HCLK_RAM0                   (1 << 4)
+#define SYS_HRST_RAM0                   (1 << 4)
+#define SYS_HCLK_RAM1                   (1 << 5)
+#define SYS_HRST_RAM1                   (1 << 5)
+#define SYS_HCLK_RAM2                   (1 << 6)
+#define SYS_HRST_RAM2                   (1 << 6)
+#define SYS_HCLK_RAMRET                 (1 << 7)
+#define SYS_HRST_RAMRET                 (1 << 7)
+#define SYS_HCLK_AHB0                   (1 << 8)
+#define SYS_HRST_AHB0                   (1 << 8)
+#define SYS_HCLK_AHB1                   (1 << 9)
+#define SYS_HRST_AHB1                   (1 << 9)
+#define SYS_HCLK_AH2H_BT                (1 << 10)
+#define SYS_HRST_AH2H_BT                (1 << 10)
+#define SYS_HCLK_ADMA                   (1 << 11)
+#define SYS_HRST_ADMA                   (1 << 11)
+#define SYS_HCLK_GDMA                   (1 << 12)
+#define SYS_HRST_GDMA                   (1 << 12)
+#define SYS_HCLK_EXTMEM                 (1 << 13)
+#define SYS_HRST_EXTMEM                 (1 << 13)
+#define SYS_HCLK_FLASH                  (1 << 14)
+#define SYS_HRST_FLASH                  (1 << 14)
+#define SYS_HCLK_SDMMC                  (1 << 15)
+#define SYS_HRST_SDMMC                  (1 << 15)
+#define SYS_HCLK_USBC                   (1 << 16)
+#define SYS_HRST_USBC                   (1 << 16)
+#define SYS_HCLK_CODEC                  (1 << 17)
+#define SYS_HRST_CODEC                  (1 << 17)
+#define SYS_HCLK_FFT                    (1 << 18)
+#define SYS_HRST_FFT                    (1 << 18)
+#define SYS_HCLK_I2C_SLAVE              (1 << 19)
+#define SYS_HRST_I2C_SLAVE              (1 << 19)
+#define SYS_HCLK_USBH                   (1 << 20)
+#define SYS_HRST_USBH                   (1 << 20)
+#define SYS_HCLK_SENSOR_HUB             (1 << 21)
+#define SYS_HRST_SENSOR_HUB             (1 << 21)
+#define SYS_HCLK_BT_DUMP                (1 << 22)
+#define SYS_HRST_BT_DUMP                (1 << 22)
+#define SYS_HCLK_CP                     (1 << 23)
+#define SYS_HRST_CP                     (1 << 23)
+#define SYS_HCLK_RAM3                   (1 << 24)
+#define SYS_HRST_RAM3                   (1 << 24)
+#define SYS_HCLK_RAM4                   (1 << 25)
+#define SYS_HRST_RAM4                   (1 << 25)
+#define SYS_HCLK_RAM5                   (1 << 26)
+#define SYS_HRST_RAM5                   (1 << 26)
+#define SYS_HCLK_RAM6                   (1 << 27)
+#define SYS_HRST_RAM6                   (1 << 27)
+#define SYS_HCLK_BCM                    (1 << 28)
+#define SYS_HRST_BCM                    (1 << 28)
+#define SYS_HCLK_ICACHE0                (1 << 29)
+#define SYS_HRST_ICACHE0                (1 << 29)
+#define SYS_HCLK_ICACHE1                (1 << 30)
+#define SYS_HRST_ICACHE1                (1 << 30)
 
 // MCU System APB Clocks:
 #define SYS_PCLK_CMU                    (1 << 0)
@@ -766,55 +796,55 @@ struct CMU_T {
 #define SYS_PRST_I2S0                   (1 << 15)
 #define SYS_PCLK_SPDIF0                 (1 << 16)
 #define SYS_PRST_SPDIF0                 (1 << 16)
-#define SYS_PCLK_BCM                    (1 << 20)
-#define SYS_PRST_BCM                    (1 << 20)
-#define SYS_PCLK_I2S1                   (1 << 25)
-#define SYS_PRST_I2S1                   (1 << 25)
+#define SYS_PCLK_I2S1                   (1 << 17)
+#define SYS_PRST_I2S1                   (1 << 17)
+#define SYS_PCLK_BCM                    (1 << 18)
+#define SYS_PRST_BCM                    (1 << 18)
 
 // MCU System Other Clocks:
 #define SYS_OCLK_SLEEP                  (1 << 0)
 #define SYS_ORST_SLEEP                  (1 << 0)
-#define SYS_OCLK_USB                    (1 << 1)
-#define SYS_ORST_USB                    (1 << 1)
-#define SYS_OCLK_USB32K                 (1 << 2)
-#define SYS_ORST_USB32K                 (1 << 2)
-#define SYS_OCLK_FLASH                  (1 << 5)
-#define SYS_ORST_FLASH                  (1 << 5)
-#define SYS_OCLK_SDMMC                  (1 << 6)
-#define SYS_ORST_SDMMC                  (1 << 6)
-#define SYS_OCLK_WDT                    (1 << 7)
-#define SYS_ORST_WDT                    (1 << 7)
-#define SYS_OCLK_TIMER0                 (1 << 8)
-#define SYS_ORST_TIMER0                 (1 << 8)
-#define SYS_OCLK_TIMER1                 (1 << 9)
-#define SYS_ORST_TIMER1                 (1 << 9)
-#define SYS_OCLK_TIMER2                 (1 << 10)
-#define SYS_ORST_TIMER2                 (1 << 10)
-#define SYS_OCLK_I2C0                   (1 << 11)
-#define SYS_ORST_I2C0                   (1 << 11)
-#define SYS_OCLK_I2C1                   (1 << 12)
-#define SYS_ORST_I2C1                   (1 << 12)
-#define SYS_OCLK_SPI                    (1 << 13)
-#define SYS_ORST_SPI                    (1 << 13)
-#define SYS_OCLK_SLCD                   (1 << 14)
-#define SYS_ORST_SLCD                   (1 << 14)
-#define SYS_OCLK_SPI_ITN                (1 << 15)
-#define SYS_ORST_SPI_ITN                (1 << 15)
-#define SYS_OCLK_SPI_PHY                (1 << 16)
-#define SYS_ORST_SPI_PHY                (1 << 16)
-#define SYS_OCLK_UART0                  (1 << 17)
-#define SYS_ORST_UART0                  (1 << 17)
-#define SYS_OCLK_UART1                  (1 << 18)
-#define SYS_ORST_UART1                  (1 << 18)
-#define SYS_OCLK_UART2                  (1 << 19)
-#define SYS_ORST_UART2                  (1 << 19)
-#define SYS_OCLK_PCM                    (1 << 20)
-#define SYS_ORST_PCM                    (1 << 20)
-#define SYS_OCLK_I2S0                   (1 << 21)
-#define SYS_ORST_I2S0                   (1 << 21)
-#define SYS_OCLK_SPDIF0                 (1 << 22)
-#define SYS_ORST_SPDIF0                 (1 << 22)
-#define SYS_OCLK_I2S1                   (1 << 23)
-#define SYS_ORST_I2S1                   (1 << 23)
+#define SYS_OCLK_FLASH                  (1 << 1)
+#define SYS_ORST_FLASH                  (1 << 1)
+#define SYS_OCLK_USB                    (1 << 2)
+#define SYS_ORST_USB                    (1 << 2)
+#define SYS_OCLK_SDMMC                  (1 << 3)
+#define SYS_ORST_SDMMC                  (1 << 3)
+#define SYS_OCLK_WDT                    (1 << 4)
+#define SYS_ORST_WDT                    (1 << 4)
+#define SYS_OCLK_TIMER0                 (1 << 5)
+#define SYS_ORST_TIMER0                 (1 << 5)
+#define SYS_OCLK_TIMER1                 (1 << 6)
+#define SYS_ORST_TIMER1                 (1 << 6)
+#define SYS_OCLK_TIMER2                 (1 << 7)
+#define SYS_ORST_TIMER2                 (1 << 7)
+#define SYS_OCLK_I2C0                   (1 << 8)
+#define SYS_ORST_I2C0                   (1 << 8)
+#define SYS_OCLK_I2C1                   (1 << 9)
+#define SYS_ORST_I2C1                   (1 << 9)
+#define SYS_OCLK_SPI                    (1 << 10)
+#define SYS_ORST_SPI                    (1 << 10)
+#define SYS_OCLK_SLCD                   (1 << 11)
+#define SYS_ORST_SLCD                   (1 << 11)
+#define SYS_OCLK_SPI_ITN                (1 << 12)
+#define SYS_ORST_SPI_ITN                (1 << 12)
+#define SYS_OCLK_SPI_PHY                (1 << 13)
+#define SYS_ORST_SPI_PHY                (1 << 13)
+#define SYS_OCLK_UART0                  (1 << 14)
+#define SYS_ORST_UART0                  (1 << 14)
+#define SYS_OCLK_UART1                  (1 << 15)
+#define SYS_ORST_UART1                  (1 << 15)
+#define SYS_OCLK_UART2                  (1 << 16)
+#define SYS_ORST_UART2                  (1 << 16)
+#define SYS_OCLK_I2S0                   (1 << 17)
+#define SYS_ORST_I2S0                   (1 << 17)
+#define SYS_OCLK_SPDIF0                 (1 << 18)
+#define SYS_ORST_SPDIF0                 (1 << 18)
+#define SYS_OCLK_PCM                    (1 << 19)
+#define SYS_ORST_PCM                    (1 << 19)
+#define SYS_OCLK_USB32K                 (1 << 20)
+#define SYS_ORST_USB32K                 (1 << 20)
+#define SYS_OCLK_I2S1                   (1 << 21)
+#define SYS_ORST_I2S1                   (1 << 21)
 
 #endif

platform/hal/best2300p/reg_codec_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/reg_codec_best2300p.h bes/platform/hal/best2300p/reg_codec_best2300p.h
index cfe2da003af..c7842879075 100644
--- a/platform/hal/best2300p/reg_codec_best2300p.h
+++ b/platform/hal/best2300p/reg_codec_best2300p.h
@@ -171,9 +171,9 @@ struct CODEC_T {
 #define CODEC_ADC_ENABLE_CH4                                (1 << 6)
 #define CODEC_ADC_ENABLE_CH5                                (1 << 7)
 #define CODEC_ADC_ENABLE_CH6                                (1 << 8)
-#define CODEC_DAC_ENABLE                                    (1 << 10)
-#define CODEC_DMACTRL_RX                                    (1 << 11)
-#define CODEC_DMACTRL_TX                                    (1 << 12)
+#define CODEC_DAC_ENABLE                                    (1 << 9)
+#define CODEC_DMACTRL_RX                                    (1 << 10)
+#define CODEC_DMACTRL_TX                                    (1 << 11)
 
 // reg_04
 #define CODEC_RX_FIFO_FLUSH_CH0                             (1 << 0)
@@ -183,9 +183,12 @@ struct CODEC_T {
 #define CODEC_RX_FIFO_FLUSH_CH4                             (1 << 4)
 #define CODEC_RX_FIFO_FLUSH_CH5                             (1 << 5)
 #define CODEC_RX_FIFO_FLUSH_CH6                             (1 << 6)
-#define CODEC_TX_FIFO_FLUSH                                 (1 << 8)
-#define CODEC_DSD_RX_FIFO_FLUSH                             (1 << 9)
-#define CODEC_DSD_TX_FIFO_FLUSH                             (1 << 10)
+#define CODEC_TX_FIFO_FLUSH                                 (1 << 7)
+#define CODEC_DSD_RX_FIFO_FLUSH                             (1 << 8)
+#define CODEC_DSD_TX_FIFO_FLUSH                             (1 << 9)
+#define CODEC_MC_FIFO_FLUSH                                 (1 << 10)
+#define CODEC_IIR_RX_FIFO_FLUSH                             (1 << 11)
+#define CODEC_IIR_TX_FIFO_FLUSH                             (1 << 12)
 
 // reg_08
 #define CODEC_CODEC_RX_THRESHOLD(n)                         (((n) & 0xF) << 0)
@@ -200,50 +203,71 @@ struct CODEC_T {
 #define CODEC_DSD_TX_THRESHOLD(n)                           (((n) & 0x7) << 12)
 #define CODEC_DSD_TX_THRESHOLD_MASK                         (0x7 << 12)
 #define CODEC_DSD_TX_THRESHOLD_SHIFT                        (12)
+#define CODEC_MC_THRESHOLD(n)                               (((n) & 0xF) << 15)
+#define CODEC_MC_THRESHOLD_MASK                             (0xF << 15)
+#define CODEC_MC_THRESHOLD_SHIFT                            (15)
+#define CODEC_IIR_RX_THRESHOLD(n)                           (((n) & 0x3F) << 19)
+#define CODEC_IIR_RX_THRESHOLD_MASK                         (0x3F << 19)
+#define CODEC_IIR_RX_THRESHOLD_SHIFT                        (19)
+#define CODEC_IIR_TX_THRESHOLD(n)                           (((n) & 0x3F) << 25)
+#define CODEC_IIR_TX_THRESHOLD_MASK                         (0x3F << 25)
+#define CODEC_IIR_TX_THRESHOLD_SHIFT                        (25)
 
 // reg_0c
-#define CODEC_CODEC_RX_OVERFLOW(n)                          (((n) & 0xFF) << 0)
-#define CODEC_CODEC_RX_OVERFLOW_MASK                        (0xFF << 0)
+#define CODEC_CODEC_RX_OVERFLOW(n)                          (((n) & 0x1F) << 0)
+#define CODEC_CODEC_RX_OVERFLOW_MASK                        (0x1F << 0)
 #define CODEC_CODEC_RX_OVERFLOW_SHIFT                       (0)
-#define CODEC_CODEC_RX_UNDERFLOW(n)                         (((n) & 0xFF) << 8)
-#define CODEC_CODEC_RX_UNDERFLOW_MASK                       (0xFF << 8)
-#define CODEC_CODEC_RX_UNDERFLOW_SHIFT                      (8)
-#define CODEC_CODEC_TX_OVERFLOW                             (1 << 16)
-#define CODEC_CODEC_TX_UNDERFLOW                            (1 << 17)
-#define CODEC_DSD_RX_OVERFLOW                               (1 << 18)
-#define CODEC_DSD_RX_UNDERFLOW                              (1 << 19)
-#define CODEC_DSD_TX_OVERFLOW                               (1 << 20)
-#define CODEC_DSD_TX_UNDERFLOW                              (1 << 21)
+#define CODEC_CODEC_RX_UNDERFLOW(n)                         (((n) & 0x1F) << 5)
+#define CODEC_CODEC_RX_UNDERFLOW_MASK                       (0x1F << 5)
+#define CODEC_CODEC_RX_UNDERFLOW_SHIFT                      (5)
+#define CODEC_CODEC_TX_OVERFLOW                             (1 << 10)
+#define CODEC_CODEC_TX_UNDERFLOW                            (1 << 11)
+#define CODEC_DSD_RX_OVERFLOW                               (1 << 12)
+#define CODEC_DSD_RX_UNDERFLOW                              (1 << 13)
+#define CODEC_DSD_TX_OVERFLOW                               (1 << 14)
+#define CODEC_DSD_TX_UNDERFLOW                              (1 << 15)
+#define CODEC_MC_OVERFLOW                                   (1 << 16)
+#define CODEC_MC_UNDERFLOW                                  (1 << 17)
+#define CODEC_IIR_RX_OVERFLOW                               (1 << 18)
+#define CODEC_IIR_RX_UNDERFLOW                              (1 << 19)
+#define CODEC_IIR_TX_OVERFLOW                               (1 << 20)
+#define CODEC_IIR_TX_UNDERFLOW                              (1 << 21)
 #define CODEC_EVENT_TRIGGER                                 (1 << 22)
-#define CODEC_VAD_FIND                                      (1 << 23)
-#define CODEC_VAD_NOT_FIND                                  (1 << 24)
-#define CODEC_BT_TRIGGER                                    (1 << 25)
-#define CODEC_TSF_TRIGGER                                   (1 << 26)
-#define CODEC_ADC_MAX_OVERFLOW                              (1 << 27)
-#define CODEC_TIME_TRIGGER                                  (1 << 28)
-#define CODEC_BT_TRIGGER1                                   (1 << 29)
+#define CODEC_FB_CHECK_ERROR_TRIG_CH0                       (1 << 23)
+#define CODEC_FB_CHECK_ERROR_TRIG_CH1                       (1 << 24)
+#define CODEC_VAD_FIND                                      (1 << 25)
+#define CODEC_VAD_NOT_FIND                                  (1 << 26)
+#define CODEC_BT_TRIGGER                                    (1 << 27)
+#define CODEC_ADC_MAX_OVERFLOW                              (1 << 28)
+#define CODEC_TIME_TRIGGER_STATUS                           (1 << 29)
 
 // reg_10
-#define CODEC_CODEC_RX_OVERFLOW_MSK(n)                      (((n) & 0xFF) << 0)
-#define CODEC_CODEC_RX_OVERFLOW_MSK_MASK                    (0xFF << 0)
+#define CODEC_CODEC_RX_OVERFLOW_MSK(n)                      (((n) & 0x1F) << 0)
+#define CODEC_CODEC_RX_OVERFLOW_MSK_MASK                    (0x1F << 0)
 #define CODEC_CODEC_RX_OVERFLOW_MSK_SHIFT                   (0)
-#define CODEC_CODEC_RX_UNDERFLOW_MSK(n)                     (((n) & 0xFF) << 8)
-#define CODEC_CODEC_RX_UNDERFLOW_MSK_MASK                   (0xFF << 8)
-#define CODEC_CODEC_RX_UNDERFLOW_MSK_SHIFT                  (8)
-#define CODEC_CODEC_TX_OVERFLOW_MSK                         (1 << 16)
-#define CODEC_CODEC_TX_UNDERFLOW_MSK                        (1 << 17)
-#define CODEC_DSD_RX_OVERFLOW_MSK                           (1 << 18)
-#define CODEC_DSD_RX_UNDERFLOW_MSK                          (1 << 19)
-#define CODEC_DSD_TX_OVERFLOW_MSK                           (1 << 20)
-#define CODEC_DSD_TX_UNDERFLOW_MSK                          (1 << 21)
+#define CODEC_CODEC_RX_UNDERFLOW_MSK(n)                     (((n) & 0x1F) << 5)
+#define CODEC_CODEC_RX_UNDERFLOW_MSK_MASK                   (0x1F << 5)
+#define CODEC_CODEC_RX_UNDERFLOW_MSK_SHIFT                  (5)
+#define CODEC_CODEC_TX_OVERFLOW_MSK                         (1 << 10)
+#define CODEC_CODEC_TX_UNDERFLOW_MSK                        (1 << 11)
+#define CODEC_DSD_RX_OVERFLOW_MSK                           (1 << 12)
+#define CODEC_DSD_RX_UNDERFLOW_MSK                          (1 << 13)
+#define CODEC_DSD_TX_OVERFLOW_MSK                           (1 << 14)
+#define CODEC_DSD_TX_UNDERFLOW_MSK                          (1 << 15)
+#define CODEC_MC_OVERFLOW_MSK                               (1 << 16)
+#define CODEC_MC_UNDERFLOW_MSK                              (1 << 17)
+#define CODEC_IIR_RX_OVERFLOW_MSK                           (1 << 18)
+#define CODEC_IIR_RX_UNDERFLOW_MSK                          (1 << 19)
+#define CODEC_IIR_TX_OVERFLOW_MSK                           (1 << 20)
+#define CODEC_IIR_TX_UNDERFLOW_MSK                          (1 << 21)
 #define CODEC_EVENT_TRIGGER_MSK                             (1 << 22)
-#define CODEC_VAD_FIND_MSK                                  (1 << 23)
-#define CODEC_VAD_NOT_FIND_MSK                              (1 << 24)
-#define CODEC_BT_TRIGGER_MSK                                (1 << 25)
-#define CODEC_TSF_TRIGGER_MSK                               (1 << 26)
-#define CODEC_ADC_MAX_OVERFLOW_MSK                          (1 << 27)
-#define CODEC_TIME_TRIGGER_MSK                              (1 << 28)
-#define CODEC_BT_TRIGGER1_MSK                               (1 << 29)
+#define CODEC_FB_CHECK_ERROR_TRIG_CH0_MSK                   (1 << 23)
+#define CODEC_FB_CHECK_ERROR_TRIG_CH1_MSK                   (1 << 24)
+#define CODEC_VAD_FIND_MSK                                  (1 << 25)
+#define CODEC_VAD_NOT_FIND_MSK                              (1 << 26)
+#define CODEC_BT_TRIGGER_MSK                                (1 << 27)
+#define CODEC_ADC_MAX_OVERFLOW_MSK                          (1 << 28)
+#define CODEC_TIME_TRIGGER_MSK                              (1 << 29)
 
 // reg_14
 #define CODEC_FIFO_COUNT_CH0(n)                             (((n) & 0xF) << 0)
@@ -261,26 +285,35 @@ struct CODEC_T {
 #define CODEC_FIFO_COUNT_CH4(n)                             (((n) & 0xF) << 16)
 #define CODEC_FIFO_COUNT_CH4_MASK                           (0xF << 16)
 #define CODEC_FIFO_COUNT_CH4_SHIFT                          (16)
-#define CODEC_FIFO_COUNT_CH5(n)                             (((n) & 0xF) << 20)
-#define CODEC_FIFO_COUNT_CH5_MASK                           (0xF << 20)
-#define CODEC_FIFO_COUNT_CH5_SHIFT                          (20)
-#define CODEC_FIFO_COUNT_CH6(n)                             (((n) & 0xF) << 24)
-#define CODEC_FIFO_COUNT_CH6_MASK                           (0xF << 24)
-#define CODEC_FIFO_COUNT_CH6_SHIFT                          (24)
+#define CODEC_FIFO_COUNT_RX_DSD(n)                          (((n) & 0xF) << 20)
+#define CODEC_FIFO_COUNT_RX_DSD_MASK                        (0xF << 20)
+#define CODEC_FIFO_COUNT_RX_DSD_SHIFT                       (20)
+#define CODEC_FIFO_COUNT_RX_IIR(n)                          (((n) & 0x3F) << 24)
+#define CODEC_FIFO_COUNT_RX_IIR_MASK                        (0x3F << 24)
+#define CODEC_FIFO_COUNT_RX_IIR_SHIFT                       (24)
 
 // reg_18
 #define CODEC_FIFO_COUNT_TX(n)                              (((n) & 0xF) << 0)
 #define CODEC_FIFO_COUNT_TX_MASK                            (0xF << 0)
 #define CODEC_FIFO_COUNT_TX_SHIFT                           (0)
-#define CODEC_STATE_RX_CH(n)                                (((n) & 0x1FF) << 4)
-#define CODEC_STATE_RX_CH_MASK                              (0x1FF << 4)
+#define CODEC_STATE_RX_CH(n)                                (((n) & 0x3F) << 4)
+#define CODEC_STATE_RX_CH_MASK                              (0x3F << 4)
 #define CODEC_STATE_RX_CH_SHIFT                             (4)
-#define CODEC_FIFO_COUNT_TX_DSD(n)                          (((n) & 0x7) << 13)
-#define CODEC_FIFO_COUNT_TX_DSD_MASK                        (0x7 << 13)
-#define CODEC_FIFO_COUNT_TX_DSD_SHIFT                       (13)
-#define CODEC_FIFO_COUNT_RX_DSD(n)                          (((n) & 0xF) << 16)
-#define CODEC_FIFO_COUNT_RX_DSD_MASK                        (0xF << 16)
-#define CODEC_FIFO_COUNT_RX_DSD_SHIFT                       (16)
+#define CODEC_FIFO_COUNT_TX_DSD(n)                          (((n) & 0x7) << 10)
+#define CODEC_FIFO_COUNT_TX_DSD_MASK                        (0x7 << 10)
+#define CODEC_FIFO_COUNT_TX_DSD_SHIFT                       (10)
+#define CODEC_MC_FIFO_COUNT(n)                              (((n) & 0xF) << 13)
+#define CODEC_MC_FIFO_COUNT_MASK                            (0xF << 13)
+#define CODEC_MC_FIFO_COUNT_SHIFT                           (13)
+#define CODEC_FIFO_COUNT_TX_IIR(n)                          (((n) & 0x3F) << 17)
+#define CODEC_FIFO_COUNT_TX_IIR_MASK                        (0x3F << 17)
+#define CODEC_FIFO_COUNT_TX_IIR_SHIFT                       (17)
+#define CODEC_FIFO_COUNT_CH5(n)                             (((n) & 0xF) << 23)
+#define CODEC_FIFO_COUNT_CH5_MASK                           (0xF << 23)
+#define CODEC_FIFO_COUNT_CH5_SHIFT                          (23)
+#define CODEC_FIFO_COUNT_CH6(n)                             (((n) & 0xF) << 27)
+#define CODEC_FIFO_COUNT_CH6_MASK                           (0xF << 27)
+#define CODEC_FIFO_COUNT_CH6_SHIFT                          (27)
 
 // reg_1c
 #define CODEC_RX_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
@@ -313,24 +346,30 @@ struct CODEC_T {
 #define CODEC_RX_FIFO_DATA_SHIFT                            (0)
 
 // reg_34
-#define CODEC_RX_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
-#define CODEC_RX_FIFO_DATA_MASK                             (0xFFFFFFFF << 0)
-#define CODEC_RX_FIFO_DATA_SHIFT                            (0)
+#define CODEC_RX_FIFO_DATA_DSD(n)                           (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_RX_FIFO_DATA_DSD_MASK                         (0xFFFFFFFF << 0)
+#define CODEC_RX_FIFO_DATA_DSD_SHIFT                        (0)
 
 // reg_38
-#define CODEC_RX_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
-#define CODEC_RX_FIFO_DATA_MASK                             (0xFFFFFFFF << 0)
-#define CODEC_RX_FIFO_DATA_SHIFT                            (0)
+#define CODEC_MC_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_MC_FIFO_DATA_MASK                             (0xFFFFFFFF << 0)
+#define CODEC_MC_FIFO_DATA_SHIFT                            (0)
 
 // reg_3c
-#define CODEC_RX_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
-#define CODEC_RX_FIFO_DATA_MASK                             (0xFFFFFFFF << 0)
-#define CODEC_RX_FIFO_DATA_SHIFT                            (0)
+#define CODEC_RX_FIFO_DATA_IIR(n)                           (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_RX_FIFO_DATA_IIR_MASK                         (0xFFFFFFFF << 0)
+#define CODEC_RX_FIFO_DATA_IIR_SHIFT                        (0)
 
 // reg_40
-#define CODEC_MODE_16BIT_ADC                                (1 << 0)
-#define CODEC_MODE_24BIT_ADC                                (1 << 1)
-#define CODEC_MODE_32BIT_ADC                                (1 << 2)
+#define CODEC_MODE_16BIT_ADC_CH0                            (1 << 0)
+#define CODEC_MODE_16BIT_ADC_CH1                            (1 << 1)
+#define CODEC_MODE_16BIT_ADC_CH2                            (1 << 2)
+#define CODEC_MODE_16BIT_ADC_CH3                            (1 << 3)
+#define CODEC_MODE_16BIT_ADC_CH4                            (1 << 4)
+#define CODEC_MODE_16BIT_ADC_CH5                            (1 << 5)
+#define CODEC_MODE_16BIT_ADC_CH6                            (1 << 6)
+#define CODEC_MODE_24BIT_ADC                                (1 << 7)
+#define CODEC_MODE_32BIT_ADC                                (1 << 8)
 
 // reg_44
 #define CODEC_DUAL_CHANNEL_DAC                              (1 << 0)
@@ -351,9 +390,15 @@ struct CODEC_T {
 #define CODEC_DSD_IN_16BIT                                  (1 << 9)
 
 // reg_4c
-#define CODEC_RX_FIFO_DATA_DSD(n)                           (((n) & 0xFFFFFFFF) << 0)
-#define CODEC_RX_FIFO_DATA_DSD_MASK                         (0xFFFFFFFF << 0)
-#define CODEC_RX_FIFO_DATA_DSD_SHIFT                        (0)
+#define CODEC_MC_ENABLE                                     (1 << 0)
+#define CODEC_DUAL_CHANNEL_MC                               (1 << 1)
+#define CODEC_MODE_16BIT_MC                                 (1 << 2)
+#define CODEC_DMA_CTRL_MC                                   (1 << 3)
+#define CODEC_MC_DELAY(n)                                   (((n) & 0xFF) << 4)
+#define CODEC_MC_DELAY_MASK                                 (0xFF << 4)
+#define CODEC_MC_DELAY_SHIFT                                (4)
+#define CODEC_MC_RATE_SEL                                   (1 << 12)
+#define CODEC_MODE_32BIT_MC                                 (1 << 13)
 
 // reg_50
 #define CODEC_CODEC_COUNT_KEEP(n)                           (((n) & 0xFFFFFFFF) << 0)
@@ -375,45 +420,53 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_ENABLE_SEL_SHIFT                    (6)
 #define CODEC_GPIO_TRIGGER_DB_ENABLE                        (1 << 8)
 #define CODEC_STAMP_CLR_USED                                (1 << 9)
-#define CODEC_EVENT_SEL(n)                                  (((n) & 0x3) << 10)
-#define CODEC_EVENT_SEL_MASK                                (0x3 << 10)
-#define CODEC_EVENT_SEL_SHIFT                               (10)
-#define CODEC_EVENT_FOR_CAPTURE                             (1 << 12)
-#define CODEC_EVENT_FOR_EN                                  (1 << 13)
-#define CODEC_TSF_EVENT_SEL                                 (1 << 14)
-#define CODEC_TEST_PORT_SEL(n)                              (((n) & 0x7) << 15)
-#define CODEC_TEST_PORT_SEL_MASK                            (0x7 << 15)
-#define CODEC_TEST_PORT_SEL_SHIFT                           (15)
+#define CODEC_EVENT_SEL                                     (1 << 10)
+#define CODEC_EVENT_FOR_CAPTURE                             (1 << 11)
+#define CODEC_TEST_PORT_SEL(n)                              (((n) & 0x7) << 12)
+#define CODEC_TEST_PORT_SEL_MASK                            (0x7 << 12)
+#define CODEC_TEST_PORT_SEL_SHIFT                           (12)
+#define CODEC_PLL_OSC_TRIGGER_SEL(n)                        (((n) & 0x3) << 15)
+#define CODEC_PLL_OSC_TRIGGER_SEL_MASK                      (0x3 << 15)
+#define CODEC_PLL_OSC_TRIGGER_SEL_SHIFT                     (15)
+#define CODEC_FAULT_MUTE_DAC_ENABLE                         (1 << 17)
 
 // reg_58
+#define CODEC_RX_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_RX_FIFO_DATA_MASK                             (0xFFFFFFFF << 0)
+#define CODEC_RX_FIFO_DATA_SHIFT                            (0)
+
+// reg_5c
+#define CODEC_RX_FIFO_DATA(n)                               (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_RX_FIFO_DATA_MASK                             (0xFFFFFFFF << 0)
+#define CODEC_RX_FIFO_DATA_SHIFT                            (0)
 
 // reg_60
-#define CODEC_EN_CLK_ADC_ANA(n)                             (((n) & 0x7) << 0)
-#define CODEC_EN_CLK_ADC_ANA_MASK                           (0x7 << 0)
+#define CODEC_EN_CLK_ADC_ANA(n)                             (((n) & 0x1F) << 0)
+#define CODEC_EN_CLK_ADC_ANA_MASK                           (0x1F << 0)
 #define CODEC_EN_CLK_ADC_ANA_SHIFT                          (0)
-#define CODEC_EN_CLK_ADC(n)                                 (((n) & 0x1FF) << 3)
-#define CODEC_EN_CLK_ADC_MASK                               (0x1FF << 3)
-#define CODEC_EN_CLK_ADC_SHIFT                              (3)
-#define CODEC_EN_CLK_DAC                                    (1 << 12)
-#define CODEC_POL_ADC_ANA(n)                                (((n) & 0x7) << 13)
-#define CODEC_POL_ADC_ANA_MASK                              (0x7 << 13)
-#define CODEC_POL_ADC_ANA_SHIFT                             (13)
-#define CODEC_POL_DAC_OUT                                   (1 << 16)
-#define CODEC_CFG_CLK_OUT(n)                                (((n) & 0x7) << 17)
-#define CODEC_CFG_CLK_OUT_MASK                              (0x7 << 17)
-#define CODEC_CFG_CLK_OUT_SHIFT                             (17)
+#define CODEC_EN_CLK_ADC(n)                                 (((n) & 0x3F) << 5)
+#define CODEC_EN_CLK_ADC_MASK                               (0x3F << 5)
+#define CODEC_EN_CLK_ADC_SHIFT                              (5)
+#define CODEC_EN_CLK_DAC                                    (1 << 11)
+#define CODEC_POL_ADC_ANA(n)                                (((n) & 0x1F) << 12)
+#define CODEC_POL_ADC_ANA_MASK                              (0x1F << 12)
+#define CODEC_POL_ADC_ANA_SHIFT                             (12)
+#define CODEC_POL_DAC_OUT                                   (1 << 17)
+#define CODEC_CFG_CLK_OUT(n)                                (((n) & 0x7) << 18)
+#define CODEC_CFG_CLK_OUT_MASK                              (0x7 << 18)
+#define CODEC_CFG_CLK_OUT_SHIFT                             (18)
 
 // reg_64
-#define CODEC_SOFT_RSTN_ADC_ANA(n)                          (((n) & 0x7) << 0)
-#define CODEC_SOFT_RSTN_ADC_ANA_MASK                        (0x7 << 0)
+#define CODEC_SOFT_RSTN_ADC_ANA(n)                          (((n) & 0x1F) << 0)
+#define CODEC_SOFT_RSTN_ADC_ANA_MASK                        (0x1F << 0)
 #define CODEC_SOFT_RSTN_ADC_ANA_SHIFT                       (0)
-#define CODEC_SOFT_RSTN_ADC(n)                              (((n) & 0x1FF) << 3)
-#define CODEC_SOFT_RSTN_ADC_MASK                            (0x1FF << 3)
-#define CODEC_SOFT_RSTN_ADC_SHIFT                           (3)
-#define CODEC_SOFT_RSTN_DAC                                 (1 << 12)
-#define CODEC_SOFT_RSTN_RS0                                 (1 << 13)
-#define CODEC_SOFT_RSTN_IIR                                 (1 << 15)
-#define CODEC_SOFT_RSTN_32K                                 (1 << 16)
+#define CODEC_SOFT_RSTN_ADC(n)                              (((n) & 0x3F) << 5)
+#define CODEC_SOFT_RSTN_ADC_MASK                            (0x3F << 5)
+#define CODEC_SOFT_RSTN_ADC_SHIFT                           (5)
+#define CODEC_SOFT_RSTN_DAC                                 (1 << 11)
+#define CODEC_SOFT_RSTN_RS                                  (1 << 12)
+#define CODEC_SOFT_RSTN_IIR                                 (1 << 13)
+#define CODEC_SOFT_RSTN_32K                                 (1 << 14)
 
 // reg_68
 #define CODEC_RET1N_RF                                      (1 << 0)
@@ -452,16 +505,35 @@ struct CODEC_T {
 #define CODEC_PGEN_ROM_1                                    (1 << 29)
 
 // reg_6c
-#define CODEC_CODEC_DAC_HBF4_DELAY_SEL                      (1 << 0)
-#define CODEC_TRIG_TIME(n)                                  (((n) & 0x3FFFFF) << 1)
-#define CODEC_TRIG_TIME_MASK                                (0x3FFFFF << 1)
-#define CODEC_TRIG_TIME_SHIFT                               (1)
-#define CODEC_TRIG_TIME_ENABLE                              (1 << 23)
-#define CODEC_GET_CNT_TRIG                                  (1 << 24)
+#define CODEC_CODEC_RX5_6_OVERFLOW(n)                       (((n) & 0x3) << 0)
+#define CODEC_CODEC_RX5_6_OVERFLOW_MASK                     (0x3 << 0)
+#define CODEC_CODEC_RX5_6_OVERFLOW_SHIFT                    (0)
+#define CODEC_CODEC_RX5_6_UNDERFLOW(n)                      (((n) & 0x3) << 2)
+#define CODEC_CODEC_RX5_6_UNDERFLOW_MASK                    (0x3 << 2)
+#define CODEC_CODEC_RX5_6_UNDERFLOW_SHIFT                   (2)
 
 // reg_70
+#define CODEC_CODEC_RX5_6_OVERFLOW_MSK(n)                   (((n) & 0x3) << 0)
+#define CODEC_CODEC_RX5_6_OVERFLOW_MSK_MASK                 (0x3 << 0)
+#define CODEC_CODEC_RX5_6_OVERFLOW_MSK_SHIFT                (0)
+#define CODEC_CODEC_RX5_6_UNDERFLOW_MSK(n)                  (((n) & 0x3) << 2)
+#define CODEC_CODEC_RX5_6_UNDERFLOW_MSK_MASK                (0x3 << 2)
+#define CODEC_CODEC_RX5_6_UNDERFLOW_MSK_SHIFT               (2)
 
 // reg_78
+#define CODEC_CODEC_SIDE_TONE_CH_SEL                        (1 << 0)
+#define CODEC_CODEC_ADC_IIR_CH0_SEL(n)                      (((n) & 0x7) << 1)
+#define CODEC_CODEC_ADC_IIR_CH0_SEL_MASK                    (0x7 << 1)
+#define CODEC_CODEC_ADC_IIR_CH0_SEL_SHIFT                   (1)
+#define CODEC_CODEC_ADC_IIR_CH1_SEL(n)                      (((n) & 0x7) << 4)
+#define CODEC_CODEC_ADC_IIR_CH1_SEL_MASK                    (0x7 << 4)
+#define CODEC_CODEC_ADC_IIR_CH1_SEL_SHIFT                   (4)
+#define CODEC_CODEC_DAC_HBF4_DELAY_SEL                      (1 << 7)
+#define CODEC_TRIG_TIME(n)                                  (((n) & 0x3FFFFF) << 8)
+#define CODEC_TRIG_TIME_MASK                                (0x3FFFFF << 8)
+#define CODEC_TRIG_TIME_SHIFT                               (8)
+#define CODEC_TRIG_TIME_ENABLE                              (1 << 30)
+#define CODEC_GET_CNT_TRIG                                  (1 << 31)
 
 // reg_7c
 #define CODEC_RESERVED_REG1(n)                              (((n) & 0xFFFFFFFF) << 0)
@@ -475,20 +547,20 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_EN_CH2                              (1 << 3)
 #define CODEC_CODEC_ADC_EN_CH3                              (1 << 4)
 #define CODEC_CODEC_ADC_EN_CH4                              (1 << 5)
-#define CODEC_CODEC_SIDE_TONE_GAIN(n)                       (((n) & 0x1F) << 9)
-#define CODEC_CODEC_SIDE_TONE_GAIN_MASK                     (0x1F << 9)
-#define CODEC_CODEC_SIDE_TONE_GAIN_SHIFT                    (9)
-#define CODEC_CODEC_SIDE_TONE_MIC_SEL(n)                    (((n) & 0x7) << 14)
-#define CODEC_CODEC_ADC_LOOP                                (1 << 17)
-#define CODEC_CODEC_LOOP_SEL_L(n)                           (((n) & 0x7) << 18)
-#define CODEC_CODEC_LOOP_SEL_L_MASK                         (0x7 << 18)
-#define CODEC_CODEC_LOOP_SEL_L_SHIFT                        (18)
-#define CODEC_CODEC_LOOP_SEL_R(n)                           (((n) & 0x7) << 21)
-#define CODEC_CODEC_LOOP_SEL_R_MASK                         (0x7 << 21)
-#define CODEC_CODEC_LOOP_SEL_R_SHIFT                        (21)
-#define CODEC_CODEC_TEST_PORT_SEL(n)                        (((n) & 0x1F) << 24)
-#define CODEC_CODEC_TEST_PORT_SEL_MASK                      (0x1F << 24)
-#define CODEC_CODEC_TEST_PORT_SEL_SHIFT                     (24)
+#define CODEC_CODEC_SIDE_TONE_GAIN(n)                       (((n) & 0x1F) << 6)
+#define CODEC_CODEC_SIDE_TONE_GAIN_MASK                     (0x1F << 6)
+#define CODEC_CODEC_SIDE_TONE_GAIN_SHIFT                    (6)
+#define CODEC_CODEC_SIDE_TONE_MIC_SEL                       (1 << 11)
+#define CODEC_CODEC_ADC_LOOP                                (1 << 12)
+#define CODEC_CODEC_LOOP_SEL_L(n)                           (((n) & 0x7) << 13)
+#define CODEC_CODEC_LOOP_SEL_L_MASK                         (0x7 << 13)
+#define CODEC_CODEC_LOOP_SEL_L_SHIFT                        (13)
+#define CODEC_CODEC_LOOP_SEL_R(n)                           (((n) & 0x7) << 16)
+#define CODEC_CODEC_LOOP_SEL_R_MASK                         (0x7 << 16)
+#define CODEC_CODEC_LOOP_SEL_R_SHIFT                        (16)
+#define CODEC_CODEC_TEST_PORT_SEL(n)                        (((n) & 0x1F) << 19)
+#define CODEC_CODEC_TEST_PORT_SEL_MASK                      (0x1F << 19)
+#define CODEC_CODEC_TEST_PORT_SEL_SHIFT                     (19)
 
 // reg_84
 #define CODEC_CODEC_ADC_SIGNED_CH0                          (1 << 0)
@@ -548,34 +620,42 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_HBF3_SEL_CH2_SHIFT                  (30)
 
 // reg_90
-#define CODEC_CODEC_ADC_DOWN_SEL_CH3(n)                     (((n) & 0x3) << 0)
-#define CODEC_CODEC_ADC_DOWN_SEL_CH3_MASK                   (0x3 << 0)
-#define CODEC_CODEC_ADC_DOWN_SEL_CH3_SHIFT                  (0)
-#define CODEC_CODEC_ADC_HBF3_BYPASS_CH3                     (1 << 2)
-#define CODEC_CODEC_ADC_HBF2_BYPASS_CH3                     (1 << 3)
-#define CODEC_CODEC_ADC_HBF1_BYPASS_CH3                     (1 << 4)
-#define CODEC_CODEC_ADC_GAIN_SEL_CH3                        (1 << 5)
-#define CODEC_CODEC_ADC_GAIN_CH3(n)                         (((n) & 0xFFFFF) << 6)
-#define CODEC_CODEC_ADC_GAIN_CH3_MASK                       (0xFFFFF << 6)
-#define CODEC_CODEC_ADC_GAIN_CH3_SHIFT                      (6)
-#define CODEC_CODEC_ADC_HBF3_SEL_CH3(n)                     (((n) & 0x3) << 26)
-#define CODEC_CODEC_ADC_HBF3_SEL_CH3_MASK                   (0x3 << 26)
-#define CODEC_CODEC_ADC_HBF3_SEL_CH3_SHIFT                  (26)
+#define CODEC_CODEC_ADC_SIGNED_CH3                          (1 << 0)
+#define CODEC_CODEC_ADC_IN_SEL_CH3(n)                       (((n) & 0x7) << 1)
+#define CODEC_CODEC_ADC_IN_SEL_CH3_MASK                     (0x7 << 1)
+#define CODEC_CODEC_ADC_IN_SEL_CH3_SHIFT                    (1)
+#define CODEC_CODEC_ADC_DOWN_SEL_CH3(n)                     (((n) & 0x3) << 4)
+#define CODEC_CODEC_ADC_DOWN_SEL_CH3_MASK                   (0x3 << 4)
+#define CODEC_CODEC_ADC_DOWN_SEL_CH3_SHIFT                  (4)
+#define CODEC_CODEC_ADC_HBF3_BYPASS_CH3                     (1 << 6)
+#define CODEC_CODEC_ADC_HBF2_BYPASS_CH3                     (1 << 7)
+#define CODEC_CODEC_ADC_HBF1_BYPASS_CH3                     (1 << 8)
+#define CODEC_CODEC_ADC_GAIN_SEL_CH3                        (1 << 9)
+#define CODEC_CODEC_ADC_GAIN_CH3(n)                         (((n) & 0xFFFFF) << 10)
+#define CODEC_CODEC_ADC_GAIN_CH3_MASK                       (0xFFFFF << 10)
+#define CODEC_CODEC_ADC_GAIN_CH3_SHIFT                      (10)
+#define CODEC_CODEC_ADC_HBF3_SEL_CH3(n)                     (((n) & 0x3) << 30)
+#define CODEC_CODEC_ADC_HBF3_SEL_CH3_MASK                   (0x3 << 30)
+#define CODEC_CODEC_ADC_HBF3_SEL_CH3_SHIFT                  (30)
 
 // reg_94
-#define CODEC_CODEC_ADC_DOWN_SEL_CH4(n)                     (((n) & 0x3) << 0)
-#define CODEC_CODEC_ADC_DOWN_SEL_CH4_MASK                   (0x3 << 0)
-#define CODEC_CODEC_ADC_DOWN_SEL_CH4_SHIFT                  (0)
-#define CODEC_CODEC_ADC_HBF3_BYPASS_CH4                     (1 << 2)
-#define CODEC_CODEC_ADC_HBF2_BYPASS_CH4                     (1 << 3)
-#define CODEC_CODEC_ADC_HBF1_BYPASS_CH4                     (1 << 4)
-#define CODEC_CODEC_ADC_GAIN_SEL_CH4                        (1 << 5)
-#define CODEC_CODEC_ADC_GAIN_CH4(n)                         (((n) & 0xFFFFF) << 6)
-#define CODEC_CODEC_ADC_GAIN_CH4_MASK                       (0xFFFFF << 6)
-#define CODEC_CODEC_ADC_GAIN_CH4_SHIFT                      (6)
-#define CODEC_CODEC_ADC_HBF3_SEL_CH4(n)                     (((n) & 0x3) << 26)
-#define CODEC_CODEC_ADC_HBF3_SEL_CH4_MASK                   (0x3 << 26)
-#define CODEC_CODEC_ADC_HBF3_SEL_CH4_SHIFT                  (26)
+#define CODEC_CODEC_ADC_SIGNED_CH4                          (1 << 0)
+#define CODEC_CODEC_ADC_IN_SEL_CH4(n)                       (((n) & 0x7) << 1)
+#define CODEC_CODEC_ADC_IN_SEL_CH4_MASK                     (0x7 << 1)
+#define CODEC_CODEC_ADC_IN_SEL_CH4_SHIFT                    (1)
+#define CODEC_CODEC_ADC_DOWN_SEL_CH4(n)                     (((n) & 0x3) << 4)
+#define CODEC_CODEC_ADC_DOWN_SEL_CH4_MASK                   (0x3 << 4)
+#define CODEC_CODEC_ADC_DOWN_SEL_CH4_SHIFT                  (4)
+#define CODEC_CODEC_ADC_HBF3_BYPASS_CH4                     (1 << 6)
+#define CODEC_CODEC_ADC_HBF2_BYPASS_CH4                     (1 << 7)
+#define CODEC_CODEC_ADC_HBF1_BYPASS_CH4                     (1 << 8)
+#define CODEC_CODEC_ADC_GAIN_SEL_CH4                        (1 << 9)
+#define CODEC_CODEC_ADC_GAIN_CH4(n)                         (((n) & 0xFFFFF) << 10)
+#define CODEC_CODEC_ADC_GAIN_CH4_MASK                       (0xFFFFF << 10)
+#define CODEC_CODEC_ADC_GAIN_CH4_SHIFT                      (10)
+#define CODEC_CODEC_ADC_HBF3_SEL_CH4(n)                     (((n) & 0x3) << 30)
+#define CODEC_CODEC_ADC_HBF3_SEL_CH4_MASK                   (0x3 << 30)
+#define CODEC_CODEC_ADC_HBF3_SEL_CH4_SHIFT                  (30)
 
 // reg_98
 #define CODEC_CODEC_DAC_EN                                  (1 << 0)
@@ -604,9 +684,11 @@ struct CODEC_T {
 #define CODEC_CODEC_DAC_LR_SWAP                             (1 << 24)
 #define CODEC_CODEC_DAC_SDM_H4_6M_CH0                       (1 << 25)
 #define CODEC_CODEC_DAC_SDM_H4_6M_CH1                       (1 << 26)
-#define CODEC_CODEC_DAC_SDM_CLOSE                           (1 << 27)
-#define CODEC_CODEC_DAC_USE_HBF4                            (1 << 28)
-#define CODEC_CODEC_DAC_USE_HBF5                            (1 << 29)
+#define CODEC_CODEC_DAC_L_FIR_UPSAMPLE                      (1 << 27)
+#define CODEC_CODEC_DAC_R_FIR_UPSAMPLE                      (1 << 28)
+#define CODEC_CODEC_DAC_SDM_CLOSE                           (1 << 29)
+#define CODEC_CODEC_DAC_USE_HBF4                            (1 << 30)
+#define CODEC_CODEC_DAC_USE_HBF5                            (1 << 31)
 
 // reg_9c
 #define CODEC_CODEC_DAC_GAIN_CH0(n)                         (((n) & 0xFFFFF) << 0)
@@ -619,9 +701,9 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_GAIN_UPDATE_CH2                     (1 << 24)
 #define CODEC_CODEC_ADC_GAIN_UPDATE_CH3                     (1 << 25)
 #define CODEC_CODEC_ADC_GAIN_UPDATE_CH4                     (1 << 26)
-#define CODEC_CODEC_DAC_GAIN_TRIGGER_SEL(n)                 (((n) & 0x3) << 30)
-#define CODEC_CODEC_DAC_GAIN_TRIGGER_SEL_MASK               (0x3 << 30)
-#define CODEC_CODEC_DAC_GAIN_TRIGGER_SEL_SHIFT              (30)
+#define CODEC_CODEC_DAC_GAIN_TRIGGER_SEL(n)                 (((n) & 0x3) << 27)
+#define CODEC_CODEC_DAC_GAIN_TRIGGER_SEL_MASK               (0x3 << 27)
+#define CODEC_CODEC_DAC_GAIN_TRIGGER_SEL_SHIFT              (27)
 
 // reg_a0
 #define CODEC_CODEC_DAC_GAIN_CH1(n)                         (((n) & 0xFFFFF) << 0)
@@ -645,12 +727,11 @@ struct CODEC_T {
 // reg_a4
 #define CODEC_CODEC_PDM_ENABLE                              (1 << 0)
 #define CODEC_CODEC_PDM_DATA_INV                            (1 << 1)
-#define CODEC_CODEC_PDM_RATE_SEL(n)                         (((n) & 0x3) << 2)
-#define CODEC_CODEC_PDM_RATE_SEL_MASK                       (0x3 << 2)
-#define CODEC_CODEC_PDM_RATE_SEL_SHIFT                      (2)
-#define CODEC_CODEC_PDM_ADC_SEL_CH0                         (1 << 4)
-#define CODEC_CODEC_PDM_ADC_SEL_CH1                         (1 << 5)
-#define CODEC_CODEC_PDM_ADC_SEL_CH2                         (1 << 6)
+#define CODEC_CODEC_PDM_ADC_SEL_CH0                         (1 << 2)
+#define CODEC_CODEC_PDM_ADC_SEL_CH1                         (1 << 3)
+#define CODEC_CODEC_PDM_ADC_SEL_CH2                         (1 << 4)
+#define CODEC_CODEC_PDM_ADC_SEL_CH3                         (1 << 5)
+#define CODEC_CODEC_PDM_ADC_SEL_CH4                         (1 << 6)
 
 // reg_a8
 #define CODEC_CODEC_PDM_MUX_CH0(n)                          (((n) & 0x7) << 0)
@@ -668,28 +749,41 @@ struct CODEC_T {
 #define CODEC_CODEC_PDM_MUX_CH4(n)                          (((n) & 0x7) << 12)
 #define CODEC_CODEC_PDM_MUX_CH4_MASK                        (0x7 << 12)
 #define CODEC_CODEC_PDM_MUX_CH4_SHIFT                       (12)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH0(n)                    (((n) & 0x3) << 18)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH0_MASK                  (0x3 << 18)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH0_SHIFT                 (18)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH1(n)                    (((n) & 0x3) << 20)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH1_MASK                  (0x3 << 20)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH1_SHIFT                 (20)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH2(n)                    (((n) & 0x3) << 22)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH2_MASK                  (0x3 << 22)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH2_SHIFT                 (22)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH3(n)                    (((n) & 0x3) << 24)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH3_MASK                  (0x3 << 24)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH3_SHIFT                 (24)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH4(n)                    (((n) & 0x3) << 26)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH4_MASK                  (0x3 << 26)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH4_SHIFT                 (26)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH5(n)                    (((n) & 0x3) << 28)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH5_MASK                  (0x3 << 28)
-#define CODEC_CODEC_PDM_CAP_PHASE_CH5_SHIFT                 (28)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH0(n)                    (((n) & 0x3) << 15)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH0_MASK                  (0x3 << 15)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH0_SHIFT                 (15)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH1(n)                    (((n) & 0x3) << 17)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH1_MASK                  (0x3 << 17)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH1_SHIFT                 (17)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH2(n)                    (((n) & 0x3) << 19)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH2_MASK                  (0x3 << 19)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH2_SHIFT                 (19)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH3(n)                    (((n) & 0x3) << 21)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH3_MASK                  (0x3 << 21)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH3_SHIFT                 (21)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH4(n)                    (((n) & 0x3) << 23)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH4_MASK                  (0x3 << 23)
+#define CODEC_CODEC_PDM_CAP_PHASE_CH4_SHIFT                 (23)
 
 // reg_b0
+#define CODEC_CODEC_CLASSG_EN                               (1 << 0)
+#define CODEC_CODEC_CLASSG_QUICK_DOWN                       (1 << 1)
+#define CODEC_CODEC_CLASSG_STEP_3_4N                        (1 << 2)
+#define CODEC_CODEC_CLASSG_LR                               (1 << 3)
+#define CODEC_CODEC_CLASSG_WINDOW(n)                        (((n) & 0xFFF) << 4)
+#define CODEC_CODEC_CLASSG_WINDOW_MASK                      (0xFFF << 4)
+#define CODEC_CODEC_CLASSG_WINDOW_SHIFT                     (4)
 
 // reg_b4
+#define CODEC_CODEC_CLASSG_THD0(n)                          (((n) & 0xFF) << 0)
+#define CODEC_CODEC_CLASSG_THD0_MASK                        (0xFF << 0)
+#define CODEC_CODEC_CLASSG_THD0_SHIFT                       (0)
+#define CODEC_CODEC_CLASSG_THD1(n)                          (((n) & 0xFF) << 8)
+#define CODEC_CODEC_CLASSG_THD1_MASK                        (0xFF << 8)
+#define CODEC_CODEC_CLASSG_THD1_SHIFT                       (8)
+#define CODEC_CODEC_CLASSG_THD2(n)                          (((n) & 0xFF) << 16)
+#define CODEC_CODEC_CLASSG_THD2_MASK                        (0xFF << 16)
+#define CODEC_CODEC_CLASSG_THD2_SHIFT                       (16)
 
 // reg_b8
 #define CODEC_CODEC_DSD_ENABLE_L                            (1 << 0)
@@ -700,106 +794,140 @@ struct CODEC_T {
 #define CODEC_CODEC_DSD_SAMPLE_RATE_SHIFT                   (3)
 
 // reg_bc
+#define CODEC_CODEC_ADC_MC_EN_CH0                           (1 << 0)
+#define CODEC_CODEC_ADC_MC_EN_CH1                           (1 << 1)
+#define CODEC_CODEC_FEEDBACK_MC_EN_CH0                      (1 << 2)
+#define CODEC_CODEC_FEEDBACK_MC_EN_CH1                      (1 << 3)
 
 // reg_c0
 #define CODEC_CODEC_DRE_ENABLE_CH0                          (1 << 0)
-#define CODEC_CODEC_DRE_STEP_MODE_CH0(n)                    (((n) & 0x7) << 1)
-#define CODEC_CODEC_DRE_STEP_MODE_CH0_MASK                  (0x7 << 1)
+#define CODEC_CODEC_DRE_STEP_MODE_CH0(n)                    (((n) & 0x3) << 1)
+#define CODEC_CODEC_DRE_STEP_MODE_CH0_MASK                  (0x3 << 1)
 #define CODEC_CODEC_DRE_STEP_MODE_CH0_SHIFT                 (1)
-#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH0(n)                 (((n) & 0xF) << 4)
-#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH0_MASK               (0xF << 4)
-#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH0_SHIFT              (4)
-#define CODEC_CODEC_DRE_DELAY_CH0(n)                        (((n) & 0xFF) << 8)
-#define CODEC_CODEC_DRE_DELAY_CH0_MASK                      (0xFF << 8)
-#define CODEC_CODEC_DRE_DELAY_CH0_SHIFT                     (8)
-#define CODEC_CODEC_DRE_AMP_HIGH_CH0(n)                     (((n) & 0xFFFF) << 16)
-#define CODEC_CODEC_DRE_AMP_HIGH_CH0_MASK                   (0xFFFF << 16)
-#define CODEC_CODEC_DRE_AMP_HIGH_CH0_SHIFT                  (16)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_SIGN_CH0              (1 << 25)
-#define CODEC_CODEC_DRE_GAIN_OFFSET_CH0(n)                  (((n) & 0x1F) << 26)
-#define CODEC_CODEC_DRE_GAIN_OFFSET_CH0_MASK                (0x1F << 26)
-#define CODEC_CODEC_DRE_GAIN_OFFSET_CH0_SHIFT               (26)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH0(n)                (((n) & 0xF) << 3)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH0_MASK              (0xF << 3)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH0_SHIFT             (3)
+#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH0(n)                 (((n) & 0xF) << 7)
+#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH0_MASK               (0xF << 7)
+#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH0_SHIFT              (7)
+#define CODEC_CODEC_DRE_DELAY_CH0(n)                        (((n) & 0x3F) << 11)
+#define CODEC_CODEC_DRE_DELAY_CH0_MASK                      (0x3F << 11)
+#define CODEC_CODEC_DRE_DELAY_CH0_SHIFT                     (11)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_SIGN_CH0              (1 << 17)
+#define CODEC_CODEC_DRE_GAIN_OFFSET_CH0(n)                  (((n) & 0x7) << 18)
+#define CODEC_CODEC_DRE_GAIN_OFFSET_CH0_MASK                (0x7 << 18)
+#define CODEC_CODEC_DRE_GAIN_OFFSET_CH0_SHIFT               (18)
 
 // reg_c4
-#define CODEC_CODEC_DRE_WINDOW_CH0(n)                       (((n) & 0x1FFFFF) << 0)
-#define CODEC_CODEC_DRE_WINDOW_CH0_MASK                     (0x1FFFFF << 0)
-#define CODEC_CODEC_DRE_WINDOW_CH0_SHIFT                    (0)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH0(n)                (((n) & 0xF) << 21)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH0_MASK              (0xF << 21)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH0_SHIFT             (21)
+#define CODEC_CODEC_DRE_AMP_HIGH_CH0(n)                     (((n) & 0x7FF) << 0)
+#define CODEC_CODEC_DRE_AMP_HIGH_CH0_MASK                   (0x7FF << 0)
+#define CODEC_CODEC_DRE_AMP_HIGH_CH0_SHIFT                  (0)
+#define CODEC_CODEC_DRE_WINDOW_CH0(n)                       (((n) & 0x1FFFFF) << 11)
+#define CODEC_CODEC_DRE_WINDOW_CH0_MASK                     (0x1FFFFF << 11)
+#define CODEC_CODEC_DRE_WINDOW_CH0_SHIFT                    (11)
 
 // reg_c8
 #define CODEC_CODEC_DRE_ENABLE_CH1                          (1 << 0)
-#define CODEC_CODEC_DRE_STEP_MODE_CH1(n)                    (((n) & 0x7) << 1)
-#define CODEC_CODEC_DRE_STEP_MODE_CH1_MASK                  (0x7 << 1)
+#define CODEC_CODEC_DRE_STEP_MODE_CH1(n)                    (((n) & 0x3) << 1)
+#define CODEC_CODEC_DRE_STEP_MODE_CH1_MASK                  (0x3 << 1)
 #define CODEC_CODEC_DRE_STEP_MODE_CH1_SHIFT                 (1)
-#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH1(n)                 (((n) & 0xF) << 4)
-#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH1_MASK               (0xF << 4)
-#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH1_SHIFT              (4)
-#define CODEC_CODEC_DRE_DELAY_CH1(n)                        (((n) & 0xFF) << 8)
-#define CODEC_CODEC_DRE_DELAY_CH1_MASK                      (0xFF << 8)
-#define CODEC_CODEC_DRE_DELAY_CH1_SHIFT                     (8)
-#define CODEC_CODEC_DRE_AMP_HIGH_CH1(n)                     (((n) & 0xFFFF) << 16)
-#define CODEC_CODEC_DRE_AMP_HIGH_CH1_MASK                   (0xFFFF << 16)
-#define CODEC_CODEC_DRE_AMP_HIGH_CH1_SHIFT                  (16)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_SIGN_CH1              (1 << 25)
-#define CODEC_CODEC_DRE_GAIN_OFFSET_CH1(n)                  (((n) & 0x1F) << 26)
-#define CODEC_CODEC_DRE_GAIN_OFFSET_CH1_MASK                (0x1F << 26)
-#define CODEC_CODEC_DRE_GAIN_OFFSET_CH1_SHIFT               (26)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH1(n)                (((n) & 0xF) << 3)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH1_MASK              (0xF << 3)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH1_SHIFT             (3)
+#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH1(n)                 (((n) & 0xF) << 7)
+#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH1_MASK               (0xF << 7)
+#define CODEC_CODEC_DRE_INI_ANA_GAIN_CH1_SHIFT              (7)
+#define CODEC_CODEC_DRE_DELAY_CH1(n)                        (((n) & 0x3F) << 11)
+#define CODEC_CODEC_DRE_DELAY_CH1_MASK                      (0x3F << 11)
+#define CODEC_CODEC_DRE_DELAY_CH1_SHIFT                     (11)
+#define CODEC_CODEC_DRE_THD_DB_OFFSET_SIGN_CH1              (1 << 17)
+#define CODEC_CODEC_DRE_GAIN_OFFSET_CH1(n)                  (((n) & 0x7) << 18)
+#define CODEC_CODEC_DRE_GAIN_OFFSET_CH1_MASK                (0x7 << 18)
+#define CODEC_CODEC_DRE_GAIN_OFFSET_CH1_SHIFT               (18)
 
 // reg_cc
-#define CODEC_CODEC_DRE_WINDOW_CH1(n)                       (((n) & 0x1FFFFF) << 0)
-#define CODEC_CODEC_DRE_WINDOW_CH1_MASK                     (0x1FFFFF << 0)
-#define CODEC_CODEC_DRE_WINDOW_CH1_SHIFT                    (0)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH1(n)                (((n) & 0xF) << 21)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH1_MASK              (0xF << 21)
-#define CODEC_CODEC_DRE_THD_DB_OFFSET_CH1_SHIFT             (21)
+#define CODEC_CODEC_DRE_AMP_HIGH_CH1(n)                     (((n) & 0x7FF) << 0)
+#define CODEC_CODEC_DRE_AMP_HIGH_CH1_MASK                   (0x7FF << 0)
+#define CODEC_CODEC_DRE_AMP_HIGH_CH1_SHIFT                  (0)
+#define CODEC_CODEC_DRE_WINDOW_CH1(n)                       (((n) & 0x1FFFFF) << 11)
+#define CODEC_CODEC_DRE_WINDOW_CH1_MASK                     (0x1FFFFF << 11)
+#define CODEC_CODEC_DRE_WINDOW_CH1_SHIFT                    (11)
 
 // reg_d0
-#define CODEC_CODEC_DRE_ANA_GAIN_CH0_SYNC(n)                (((n) & 0x1F) << 0)
-#define CODEC_CODEC_DRE_ANA_GAIN_CH0_SYNC_MASK              (0x1F << 0)
-#define CODEC_CODEC_DRE_ANA_GAIN_CH0_SYNC_SHIFT             (0)
-#define CODEC_CODEC_DRE_COUNT_CH0_SYNC(n)                   (((n) & 0x1FFFFF) << 5)
-#define CODEC_CODEC_DRE_COUNT_CH0_SYNC_MASK                 (0x1FFFFF << 5)
-#define CODEC_CODEC_DRE_COUNT_CH0_SYNC_SHIFT                (5)
+#define CODEC_CODEC_ANC_ENABLE_CH0                          (1 << 0)
+#define CODEC_CODEC_ANC_ENABLE_CH1                          (1 << 1)
+#define CODEC_CODEC_DUAL_ANC_CH0                            (1 << 2)
+#define CODEC_CODEC_DUAL_ANC_CH1                            (1 << 3)
+#define CODEC_CODEC_ANC_MUTE_CH0                            (1 << 4)
+#define CODEC_CODEC_ANC_MUTE_CH1                            (1 << 5)
+#define CODEC_CODEC_FF_CH0_FIR_EN                           (1 << 6)
+#define CODEC_CODEC_FF_CH1_FIR_EN                           (1 << 7)
+#define CODEC_CODEC_FB_CH0_FIR_EN                           (1 << 8)
+#define CODEC_CODEC_FB_CH1_FIR_EN                           (1 << 9)
+#define CODEC_CODEC_ANC_RATE_SEL                            (1 << 10)
+#define CODEC_CODEC_ANC_FF_SR_SEL(n)                        (((n) & 0x3) << 11)
+#define CODEC_CODEC_ANC_FF_SR_SEL_MASK                      (0x3 << 11)
+#define CODEC_CODEC_ANC_FF_SR_SEL_SHIFT                     (11)
+#define CODEC_CODEC_ANC_FF_IN_PHASE_SEL(n)                  (((n) & 0x7) << 13)
+#define CODEC_CODEC_ANC_FF_IN_PHASE_SEL_MASK                (0x7 << 13)
+#define CODEC_CODEC_ANC_FF_IN_PHASE_SEL_SHIFT               (13)
+#define CODEC_CODEC_ANC_FB_SR_SEL(n)                        (((n) & 0x3) << 16)
+#define CODEC_CODEC_ANC_FB_SR_SEL_MASK                      (0x3 << 16)
+#define CODEC_CODEC_ANC_FB_SR_SEL_SHIFT                     (16)
+#define CODEC_CODEC_ANC_FB_IN_PHASE_SEL(n)                  (((n) & 0x7) << 18)
+#define CODEC_CODEC_ANC_FB_IN_PHASE_SEL_MASK                (0x7 << 18)
+#define CODEC_CODEC_ANC_FB_IN_PHASE_SEL_SHIFT               (18)
+#define CODEC_CODEC_FEEDBACK_CH0                            (1 << 21)
+#define CODEC_CODEC_FEEDBACK_CH1                            (1 << 22)
+#define CODEC_CODEC_ADC_FIR_DS_EN_CH2                       (1 << 23)
+#define CODEC_CODEC_ADC_FIR_DS_SEL_CH2                      (1 << 24)
+#define CODEC_CODEC_ADC_FIR_DS_EN_CH3                       (1 << 25)
+#define CODEC_CODEC_ADC_FIR_DS_SEL_CH3                      (1 << 26)
 
 // reg_d4
-#define CODEC_CODEC_DRE_ANA_GAIN_CH1_SYNC(n)                (((n) & 0x1F) << 0)
-#define CODEC_CODEC_DRE_ANA_GAIN_CH1_SYNC_MASK              (0x1F << 0)
-#define CODEC_CODEC_DRE_ANA_GAIN_CH1_SYNC_SHIFT             (0)
-#define CODEC_CODEC_DRE_COUNT_CH1_SYNC(n)                   (((n) & 0x1FFFFF) << 5)
-#define CODEC_CODEC_DRE_COUNT_CH1_SYNC_MASK                 (0x1FFFFF << 5)
-#define CODEC_CODEC_DRE_COUNT_CH1_SYNC_SHIFT                (5)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FF_CH0(n)                 (((n) & 0xFFF) << 0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FF_CH0_MASK               (0xFFF << 0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FF_CH0_SHIFT              (0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FF_CH1(n)                 (((n) & 0xFFF) << 12)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FF_CH1_MASK               (0xFFF << 12)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FF_CH1_SHIFT              (12)
+#define CODEC_CODEC_ANC_MUTE_GAIN_PASS0_FF_CH0              (1 << 24)
+#define CODEC_CODEC_ANC_MUTE_GAIN_PASS0_FF_CH1              (1 << 25)
 
 // reg_d8
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_TH(n)                  (((n) & 0xFFFFFFFF) << 0)
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_TH_MASK                (0xFFFFFFFF << 0)
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_TH_SHIFT               (0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FB_CH0(n)                 (((n) & 0xFFF) << 0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FB_CH0_MASK               (0xFFF << 0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FB_CH0_SHIFT              (0)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FB_CH1(n)                 (((n) & 0xFFF) << 12)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FB_CH1_MASK               (0xFFF << 12)
+#define CODEC_CODEC_ANC_MUTE_GAIN_FB_CH1_SHIFT              (12)
+#define CODEC_CODEC_ANC_MUTE_GAIN_PASS0_FB_CH0              (1 << 24)
+#define CODEC_CODEC_ANC_MUTE_GAIN_PASS0_FB_CH1              (1 << 25)
 
 // reg_dc
-#define CODEC_CODEC_DEQ_IIR_ENABLE                          (1 << 0)
-#define CODEC_CODEC_DEQ_IIR_IIRA_ENABLE                     (1 << 1)
-#define CODEC_CODEC_DEQ_IIR_IIRB_ENABLE                     (1 << 2)
-#define CODEC_CODEC_DEQ_IIR_CH0_BYPASS                      (1 << 3)
-#define CODEC_CODEC_DEQ_IIR_CH1_BYPASS                      (1 << 4)
-#define CODEC_CODEC_DEQ_IIR_GAINCAL_EXT_CH0_BYPASS          (1 << 5)
-#define CODEC_CODEC_DEQ_IIR_GAINCAL_EXT_CH1_BYPASS          (1 << 6)
-#define CODEC_CODEC_DEQ_IIR_GAINUSE_EXT_CH0_BYPASS          (1 << 7)
-#define CODEC_CODEC_DEQ_IIR_GAINUSE_EXT_CH1_BYPASS          (1 << 8)
-#define CODEC_CODEC_DEQ_IIR_COUNT_CH0(n)                    (((n) & 0x3F) << 9)
-#define CODEC_CODEC_DEQ_IIR_COUNT_CH0_MASK                  (0x3F << 9)
-#define CODEC_CODEC_DEQ_IIR_COUNT_CH0_SHIFT                 (9)
-#define CODEC_CODEC_DEQ_IIR_COUNT_CH1(n)                    (((n) & 0x3F) << 15)
-#define CODEC_CODEC_DEQ_IIR_COUNT_CH1_MASK                  (0x3F << 15)
-#define CODEC_CODEC_DEQ_IIR_COUNT_CH1_SHIFT                 (15)
-#define CODEC_CODEC_DEQ_IIR_COEF_SWAP                       (1 << 21)
-#define CODEC_CODEC_DEQ_IIR_AUTO_STOP                       (1 << 22)
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_UPDATE_CH0             (1 << 23)
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_UPDATE_CH1             (1 << 24)
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_SEL_CH0                (1 << 25)
-#define CODEC_CODEC_DEQ_IIR_GAIN_EXT_SEL_CH1                (1 << 26)
-#define CODEC_CODEC_DAC_L_IIR_ENABLE                        (1 << 27)
-#define CODEC_CODEC_DAC_R_IIR_ENABLE                        (1 << 28)
+#define CODEC_CODEC_IIR_ENABLE                              (1 << 0)
+#define CODEC_CODEC_IIR_CH0_BYPASS                          (1 << 1)
+#define CODEC_CODEC_IIR_CH1_BYPASS                          (1 << 2)
+#define CODEC_CODEC_IIR_CH2_BYPASS                          (1 << 3)
+#define CODEC_CODEC_IIR_CH3_BYPASS                          (1 << 4)
+#define CODEC_CODEC_IIR_COUNT_CH0(n)                        (((n) & 0xF) << 5)
+#define CODEC_CODEC_IIR_COUNT_CH0_MASK                      (0xF << 5)
+#define CODEC_CODEC_IIR_COUNT_CH0_SHIFT                     (5)
+#define CODEC_CODEC_IIR_COUNT_CH1(n)                        (((n) & 0xF) << 9)
+#define CODEC_CODEC_IIR_COUNT_CH1_MASK                      (0xF << 9)
+#define CODEC_CODEC_IIR_COUNT_CH1_SHIFT                     (9)
+#define CODEC_CODEC_IIR_COUNT_CH2(n)                        (((n) & 0xF) << 13)
+#define CODEC_CODEC_IIR_COUNT_CH2_MASK                      (0xF << 13)
+#define CODEC_CODEC_IIR_COUNT_CH2_SHIFT                     (13)
+#define CODEC_CODEC_IIR_COUNT_CH3(n)                        (((n) & 0xF) << 17)
+#define CODEC_CODEC_IIR_COUNT_CH3_MASK                      (0xF << 17)
+#define CODEC_CODEC_IIR_COUNT_CH3_SHIFT                     (17)
+#define CODEC_CODEC_DAC_L_IIR_ENABLE                        (1 << 21)
+#define CODEC_CODEC_DAC_R_IIR_ENABLE                        (1 << 22)
+#define CODEC_CODEC_ADC_CH0_IIR_ENABLE                      (1 << 23)
+#define CODEC_CODEC_ADC_CH1_IIR_ENABLE                      (1 << 24)
+#define CODEC_CODEC_IIR_COEF_SWAP                           (1 << 25)
+#define CODEC_CODEC_IIR_COEF_SWAP_STATUS                    (1 << 26)
 
 // reg_e0
 #define CODEC_CODEC_DAC_DC_CH0(n)                           (((n) & 0x7FFFF) << 0)
@@ -816,22 +944,22 @@ struct CODEC_T {
 #define CODEC_CODEC_RESAMPLE_DAC_ENABLE                     (1 << 0)
 #define CODEC_CODEC_RESAMPLE_DAC_L_ENABLE                   (1 << 1)
 #define CODEC_CODEC_RESAMPLE_DAC_R_ENABLE                   (1 << 2)
-#define CODEC_CODEC_RESAMPLE_DAC_FIFO_ENABLE                (1 << 3)
-#define CODEC_CODEC_RESAMPLE_ADC_ENABLE                     (1 << 4)
-#define CODEC_CODEC_RESAMPLE_ADC_CH_CNT(n)                  (((n) & 0x7) << 5)
-#define CODEC_CODEC_RESAMPLE_ADC_CH_CNT_MASK                (0x7 << 5)
-#define CODEC_CODEC_RESAMPLE_ADC_CH_CNT_SHIFT               (5)
-#define CODEC_CODEC_RESAMPLE_DAC_PHASE_UPDATE               (1 << 8)
-#define CODEC_CODEC_RESAMPLE_DAC_UPDATE_TRIGGER_SEL(n)      (((n) & 0x3) << 9)
-#define CODEC_CODEC_RESAMPLE_DAC_UPDATE_TRIGGER_SEL_MASK    (0x3 << 9)
-#define CODEC_CODEC_RESAMPLE_DAC_UPDATE_TRIGGER_SEL_SHIFT   (9)
-#define CODEC_CODEC_RESAMPLE_ADC_PHASE_UPDATE               (1 << 11)
-#define CODEC_CODEC_RESAMPLE_ADC_UPDATE_TRIGGER_SEL(n)      (((n) & 0x3) << 12)
-#define CODEC_CODEC_RESAMPLE_ADC_UPDATE_TRIGGER_SEL_MASK    (0x3 << 12)
-#define CODEC_CODEC_RESAMPLE_ADC_UPDATE_TRIGGER_SEL_SHIFT   (12)
-#define CODEC_CODEC_RESAMPLE_DAC_ENABLE_TRIGGER_SEL(n)      (((n) & 0x3) << 14)
-#define CODEC_CODEC_RESAMPLE_DAC_ENABLE_TRIGGER_SEL_MASK    (0x3 << 14)
-#define CODEC_CODEC_RESAMPLE_DAC_ENABLE_TRIGGER_SEL_SHIFT   (14)
+#define CODEC_CODEC_RESAMPLE_ADC_ENABLE                     (1 << 3)
+#define CODEC_CODEC_RESAMPLE_ADC_DUAL_CH                    (1 << 4)
+#define CODEC_CODEC_RESAMPLE_ADC_CH0_SEL(n)                 (((n) & 0x7) << 5)
+#define CODEC_CODEC_RESAMPLE_ADC_CH0_SEL_MASK               (0x7 << 5)
+#define CODEC_CODEC_RESAMPLE_ADC_CH0_SEL_SHIFT              (5)
+#define CODEC_CODEC_RESAMPLE_ADC_CH1_SEL(n)                 (((n) & 0x7) << 8)
+#define CODEC_CODEC_RESAMPLE_ADC_CH1_SEL_MASK               (0x7 << 8)
+#define CODEC_CODEC_RESAMPLE_ADC_CH1_SEL_SHIFT              (8)
+#define CODEC_CODEC_RESAMPLE_DAC_PHASE_UPDATE               (1 << 11)
+#define CODEC_CODEC_RESAMPLE_DAC_TRIGGER_SEL(n)             (((n) & 0x3) << 12)
+#define CODEC_CODEC_RESAMPLE_DAC_TRIGGER_SEL_MASK           (0x3 << 12)
+#define CODEC_CODEC_RESAMPLE_DAC_TRIGGER_SEL_SHIFT          (12)
+#define CODEC_CODEC_RESAMPLE_ADC_PHASE_UPDATE               (1 << 14)
+#define CODEC_CODEC_RESAMPLE_ADC_TRIGGER_SEL(n)             (((n) & 0x3) << 15)
+#define CODEC_CODEC_RESAMPLE_ADC_TRIGGER_SEL_MASK           (0x3 << 15)
+#define CODEC_CODEC_RESAMPLE_ADC_TRIGGER_SEL_SHIFT          (15)
 
 // reg_e8
 #define CODEC_CODEC_DAC_DC_CH1(n)                           (((n) & 0x7FFFF) << 0)
@@ -848,19 +976,21 @@ struct CODEC_T {
 #define CODEC_CODEC_RAMP_STEP_CH0(n)                        (((n) & 0xFFF) << 0)
 #define CODEC_CODEC_RAMP_STEP_CH0_MASK                      (0xFFF << 0)
 #define CODEC_CODEC_RAMP_STEP_CH0_SHIFT                     (0)
-#define CODEC_CODEC_RAMP_EN_CH0                             (1 << 12)
-#define CODEC_CODEC_RAMP_INTERVAL_CH0(n)                    (((n) & 0x7) << 13)
-#define CODEC_CODEC_RAMP_INTERVAL_CH0_MASK                  (0x7 << 13)
-#define CODEC_CODEC_RAMP_INTERVAL_CH0_SHIFT                 (13)
+#define CODEC_CODEC_RAMP_DIRECT_CH0                         (1 << 12)
+#define CODEC_CODEC_RAMP_EN_CH0                             (1 << 13)
+#define CODEC_CODEC_RAMP_INTERVAL_CH0(n)                    (((n) & 0x7) << 14)
+#define CODEC_CODEC_RAMP_INTERVAL_CH0_MASK                  (0x7 << 14)
+#define CODEC_CODEC_RAMP_INTERVAL_CH0_SHIFT                 (14)
 
 // reg_f0
 #define CODEC_CODEC_RAMP_STEP_CH1(n)                        (((n) & 0xFFF) << 0)
 #define CODEC_CODEC_RAMP_STEP_CH1_MASK                      (0xFFF << 0)
 #define CODEC_CODEC_RAMP_STEP_CH1_SHIFT                     (0)
-#define CODEC_CODEC_RAMP_EN_CH1                             (1 << 12)
-#define CODEC_CODEC_RAMP_INTERVAL_CH1(n)                    (((n) & 0x7) << 13)
-#define CODEC_CODEC_RAMP_INTERVAL_CH1_MASK                  (0x7 << 13)
-#define CODEC_CODEC_RAMP_INTERVAL_CH1_SHIFT                 (13)
+#define CODEC_CODEC_RAMP_DIRECT_CH1                         (1 << 12)
+#define CODEC_CODEC_RAMP_EN_CH1                             (1 << 13)
+#define CODEC_CODEC_RAMP_INTERVAL_CH1(n)                    (((n) & 0x7) << 14)
+#define CODEC_CODEC_RAMP_INTERVAL_CH1_MASK                  (0x7 << 14)
+#define CODEC_CODEC_RAMP_INTERVAL_CH1_SHIFT                 (14)
 
 // reg_f4
 #define CODEC_CODEC_RESAMPLE_DAC_PHASE_INC(n)               (((n) & 0xFFFFFFFF) << 0)
@@ -873,38 +1003,246 @@ struct CODEC_T {
 #define CODEC_CODEC_RESAMPLE_ADC_PHASE_INC_SHIFT            (0)
 
 // reg_100
+#define CODEC_FIR_STREAM_ENABLE_CH0                         (1 << 0)
+#define CODEC_FIR_STREAM_ENABLE_CH1                         (1 << 1)
+#define CODEC_FIR_STREAM_ENABLE_CH2                         (1 << 2)
+#define CODEC_FIR_STREAM_ENABLE_CH3                         (1 << 3)
+#define CODEC_FIR_ENABLE_CH0                                (1 << 4)
+#define CODEC_FIR_ENABLE_CH1                                (1 << 5)
+#define CODEC_FIR_ENABLE_CH2                                (1 << 6)
+#define CODEC_FIR_ENABLE_CH3                                (1 << 7)
+#define CODEC_DMA_CTRL_RX_FIR                               (1 << 8)
+#define CODEC_DMA_CTRL_TX_FIR                               (1 << 9)
+#define CODEC_FIR_UPSAMPLE_CH0                              (1 << 10)
+#define CODEC_FIR_UPSAMPLE_CH1                              (1 << 11)
+#define CODEC_FIR_UPSAMPLE_CH2                              (1 << 12)
+#define CODEC_FIR_UPSAMPLE_CH3                              (1 << 13)
+#define CODEC_MODE_32BIT_FIR                                (1 << 14)
+#define CODEC_FIR_RESERVED_REG0                             (1 << 15)
+#define CODEC_MODE_16BIT_FIR_TX_CH0                         (1 << 16)
+#define CODEC_MODE_16BIT_FIR_RX_CH0                         (1 << 17)
+#define CODEC_MODE_16BIT_FIR_TX_CH1                         (1 << 18)
+#define CODEC_MODE_16BIT_FIR_RX_CH1                         (1 << 19)
+#define CODEC_MODE_16BIT_FIR_TX_CH2                         (1 << 20)
+#define CODEC_MODE_16BIT_FIR_RX_CH2                         (1 << 21)
+#define CODEC_MODE_16BIT_FIR_TX_CH3                         (1 << 22)
+#define CODEC_MODE_16BIT_FIR_RX_CH3                         (1 << 23)
 
 // reg_104
+#define CODEC_FIR_ACCESS_OFFSET_CH0(n)                      (((n) & 0x7) << 0)
+#define CODEC_FIR_ACCESS_OFFSET_CH0_MASK                    (0x7 << 0)
+#define CODEC_FIR_ACCESS_OFFSET_CH0_SHIFT                   (0)
+#define CODEC_FIR_ACCESS_OFFSET_CH1(n)                      (((n) & 0x7) << 3)
+#define CODEC_FIR_ACCESS_OFFSET_CH1_MASK                    (0x7 << 3)
+#define CODEC_FIR_ACCESS_OFFSET_CH1_SHIFT                   (3)
+#define CODEC_FIR_ACCESS_OFFSET_CH2(n)                      (((n) & 0x7) << 6)
+#define CODEC_FIR_ACCESS_OFFSET_CH2_MASK                    (0x7 << 6)
+#define CODEC_FIR_ACCESS_OFFSET_CH2_SHIFT                   (6)
+#define CODEC_FIR_ACCESS_OFFSET_CH3(n)                      (((n) & 0x7) << 9)
+#define CODEC_FIR_ACCESS_OFFSET_CH3_MASK                    (0x7 << 9)
+#define CODEC_FIR_ACCESS_OFFSET_CH3_SHIFT                   (9)
 
 // reg_108
+#define CODEC_STREAM0_FIR1_CH0                              (1 << 0)
+#define CODEC_FIR_MODE_CH0(n)                               (((n) & 0x3) << 1)
+#define CODEC_FIR_MODE_CH0_MASK                             (0x3 << 1)
+#define CODEC_FIR_MODE_CH0_SHIFT                            (1)
+#define CODEC_FIR_ORDER_CH0(n)                              (((n) & 0x3FF) << 3)
+#define CODEC_FIR_ORDER_CH0_MASK                            (0x3FF << 3)
+#define CODEC_FIR_ORDER_CH0_SHIFT                           (3)
+#define CODEC_FIR_SAMPLE_START_CH0(n)                       (((n) & 0x1FF) << 13)
+#define CODEC_FIR_SAMPLE_START_CH0_MASK                     (0x1FF << 13)
+#define CODEC_FIR_SAMPLE_START_CH0_SHIFT                    (13)
+#define CODEC_FIR_SAMPLE_NUM_CH0(n)                         (((n) & 0x1FF) << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH0_MASK                       (0x1FF << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH0_SHIFT                      (22)
+#define CODEC_FIR_DO_REMAP_CH0                              (1 << 31)
 
 // reg_10c
+#define CODEC_FIR_RESULT_BASE_ADDR_CH0(n)                   (((n) & 0x1FF) << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH0_MASK                 (0x1FF << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH0_SHIFT                (0)
+#define CODEC_FIR_SLIDE_OFFSET_CH0(n)                       (((n) & 0x3F) << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH0_MASK                     (0x3F << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH0_SHIFT                    (9)
+#define CODEC_FIR_BURST_LENGTH_CH0(n)                       (((n) & 0x3F) << 15)
+#define CODEC_FIR_BURST_LENGTH_CH0_MASK                     (0x3F << 15)
+#define CODEC_FIR_BURST_LENGTH_CH0_SHIFT                    (15)
+#define CODEC_FIR_GAIN_SEL_CH0(n)                           (((n) & 0xF) << 21)
+#define CODEC_FIR_GAIN_SEL_CH0_MASK                         (0xF << 21)
+#define CODEC_FIR_GAIN_SEL_CH0_SHIFT                        (21)
+#define CODEC_FIR_LOOP_NUM_CH0(n)                           (((n) & 0x7F) << 25)
+#define CODEC_FIR_LOOP_NUM_CH0_MASK                         (0x7F << 25)
+#define CODEC_FIR_LOOP_NUM_CH0_SHIFT                        (25)
 
 // reg_110
+#define CODEC_STREAM0_FIR1_CH1                              (1 << 0)
+#define CODEC_FIR_MODE_CH1(n)                               (((n) & 0x3) << 1)
+#define CODEC_FIR_MODE_CH1_MASK                             (0x3 << 1)
+#define CODEC_FIR_MODE_CH1_SHIFT                            (1)
+#define CODEC_FIR_ORDER_CH1(n)                              (((n) & 0x3FF) << 3)
+#define CODEC_FIR_ORDER_CH1_MASK                            (0x3FF << 3)
+#define CODEC_FIR_ORDER_CH1_SHIFT                           (3)
+#define CODEC_FIR_SAMPLE_START_CH1(n)                       (((n) & 0x1FF) << 13)
+#define CODEC_FIR_SAMPLE_START_CH1_MASK                     (0x1FF << 13)
+#define CODEC_FIR_SAMPLE_START_CH1_SHIFT                    (13)
+#define CODEC_FIR_SAMPLE_NUM_CH1(n)                         (((n) & 0x1FF) << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH1_MASK                       (0x1FF << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH1_SHIFT                      (22)
+#define CODEC_FIR_DO_REMAP_CH1                              (1 << 31)
 
 // reg_114
+#define CODEC_FIR_RESULT_BASE_ADDR_CH1(n)                   (((n) & 0x1FF) << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH1_MASK                 (0x1FF << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH1_SHIFT                (0)
+#define CODEC_FIR_SLIDE_OFFSET_CH1(n)                       (((n) & 0x3F) << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH1_MASK                     (0x3F << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH1_SHIFT                    (9)
+#define CODEC_FIR_BURST_LENGTH_CH1(n)                       (((n) & 0x3F) << 15)
+#define CODEC_FIR_BURST_LENGTH_CH1_MASK                     (0x3F << 15)
+#define CODEC_FIR_BURST_LENGTH_CH1_SHIFT                    (15)
+#define CODEC_FIR_GAIN_SEL_CH1(n)                           (((n) & 0xF) << 21)
+#define CODEC_FIR_GAIN_SEL_CH1_MASK                         (0xF << 21)
+#define CODEC_FIR_GAIN_SEL_CH1_SHIFT                        (21)
+#define CODEC_FIR_LOOP_NUM_CH1(n)                           (((n) & 0x7F) << 25)
+#define CODEC_FIR_LOOP_NUM_CH1_MASK                         (0x7F << 25)
+#define CODEC_FIR_LOOP_NUM_CH1_SHIFT                        (25)
 
 // reg_118
+#define CODEC_STREAM0_FIR1_CH2                              (1 << 0)
+#define CODEC_FIR_MODE_CH2(n)                               (((n) & 0x3) << 1)
+#define CODEC_FIR_MODE_CH2_MASK                             (0x3 << 1)
+#define CODEC_FIR_MODE_CH2_SHIFT                            (1)
+#define CODEC_FIR_ORDER_CH2(n)                              (((n) & 0x3FF) << 3)
+#define CODEC_FIR_ORDER_CH2_MASK                            (0x3FF << 3)
+#define CODEC_FIR_ORDER_CH2_SHIFT                           (3)
+#define CODEC_FIR_SAMPLE_START_CH2(n)                       (((n) & 0x1FF) << 13)
+#define CODEC_FIR_SAMPLE_START_CH2_MASK                     (0x1FF << 13)
+#define CODEC_FIR_SAMPLE_START_CH2_SHIFT                    (13)
+#define CODEC_FIR_SAMPLE_NUM_CH2(n)                         (((n) & 0x1FF) << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH2_MASK                       (0x1FF << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH2_SHIFT                      (22)
+#define CODEC_FIR_DO_REMAP_CH2                              (1 << 31)
 
 // reg_11c
+#define CODEC_FIR_RESULT_BASE_ADDR_CH2(n)                   (((n) & 0x1FF) << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH2_MASK                 (0x1FF << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH2_SHIFT                (0)
+#define CODEC_FIR_SLIDE_OFFSET_CH2(n)                       (((n) & 0x3F) << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH2_MASK                     (0x3F << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH2_SHIFT                    (9)
+#define CODEC_FIR_BURST_LENGTH_CH2(n)                       (((n) & 0x3F) << 15)
+#define CODEC_FIR_BURST_LENGTH_CH2_MASK                     (0x3F << 15)
+#define CODEC_FIR_BURST_LENGTH_CH2_SHIFT                    (15)
+#define CODEC_FIR_GAIN_SEL_CH2(n)                           (((n) & 0xF) << 21)
+#define CODEC_FIR_GAIN_SEL_CH2_MASK                         (0xF << 21)
+#define CODEC_FIR_GAIN_SEL_CH2_SHIFT                        (21)
+#define CODEC_FIR_LOOP_NUM_CH2(n)                           (((n) & 0x7F) << 25)
+#define CODEC_FIR_LOOP_NUM_CH2_MASK                         (0x7F << 25)
+#define CODEC_FIR_LOOP_NUM_CH2_SHIFT                        (25)
 
 // reg_120
+#define CODEC_STREAM0_FIR1_CH3                              (1 << 0)
+#define CODEC_FIR_MODE_CH3(n)                               (((n) & 0x3) << 1)
+#define CODEC_FIR_MODE_CH3_MASK                             (0x3 << 1)
+#define CODEC_FIR_MODE_CH3_SHIFT                            (1)
+#define CODEC_FIR_ORDER_CH3(n)                              (((n) & 0x3FF) << 3)
+#define CODEC_FIR_ORDER_CH3_MASK                            (0x3FF << 3)
+#define CODEC_FIR_ORDER_CH3_SHIFT                           (3)
+#define CODEC_FIR_SAMPLE_START_CH3(n)                       (((n) & 0x1FF) << 13)
+#define CODEC_FIR_SAMPLE_START_CH3_MASK                     (0x1FF << 13)
+#define CODEC_FIR_SAMPLE_START_CH3_SHIFT                    (13)
+#define CODEC_FIR_SAMPLE_NUM_CH3(n)                         (((n) & 0x1FF) << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH3_MASK                       (0x1FF << 22)
+#define CODEC_FIR_SAMPLE_NUM_CH3_SHIFT                      (22)
+#define CODEC_FIR_DO_REMAP_CH3                              (1 << 31)
 
 // reg_124
+#define CODEC_FIR_RESULT_BASE_ADDR_CH3(n)                   (((n) & 0x1FF) << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH3_MASK                 (0x1FF << 0)
+#define CODEC_FIR_RESULT_BASE_ADDR_CH3_SHIFT                (0)
+#define CODEC_FIR_SLIDE_OFFSET_CH3(n)                       (((n) & 0x3F) << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH3_MASK                     (0x3F << 9)
+#define CODEC_FIR_SLIDE_OFFSET_CH3_SHIFT                    (9)
+#define CODEC_FIR_BURST_LENGTH_CH3(n)                       (((n) & 0x3F) << 15)
+#define CODEC_FIR_BURST_LENGTH_CH3_MASK                     (0x3F << 15)
+#define CODEC_FIR_BURST_LENGTH_CH3_SHIFT                    (15)
+#define CODEC_FIR_GAIN_SEL_CH3(n)                           (((n) & 0xF) << 21)
+#define CODEC_FIR_GAIN_SEL_CH3_MASK                         (0xF << 21)
+#define CODEC_FIR_GAIN_SEL_CH3_SHIFT                        (21)
+#define CODEC_FIR_LOOP_NUM_CH3(n)                           (((n) & 0x7F) << 25)
+#define CODEC_FIR_LOOP_NUM_CH3_MASK                         (0x7F << 25)
+#define CODEC_FIR_LOOP_NUM_CH3_SHIFT                        (25)
 
 // reg_128
+#define CODEC_AHB_IIR_ENABLE                                (1 << 0)
+#define CODEC_DO_SAMPLE_INI                                 (1 << 1)
+#define CODEC_USE_SAMPLE_HIGH_HALF                          (1 << 2)
+#define CODEC_AHB_IIR_IF_EN                                 (1 << 3)
+#define CODEC_DMA_CTRL_RX_IIR                               (1 << 4)
+#define CODEC_DMA_CTRL_TX_IIR                               (1 << 5)
+#define CODEC_MODE_32BIT_IIR                                (1 << 6)
+#define CODEC_MODE_16BIT_IIR                                (1 << 7)
+#define CODEC_AHB_IIR_MAX_CNT(n)                            (((n) & 0xF) << 8)
+#define CODEC_AHB_IIR_MAX_CNT_MASK                          (0xF << 8)
+#define CODEC_AHB_IIR_MAX_CNT_SHIFT                         (8)
+#define CODEC_IIR_MULTI_CYCLE_MODE(n)                       (((n) & 0x3) << 12)
+#define CODEC_IIR_MULTI_CYCLE_MODE_MASK                     (0x3 << 12)
+#define CODEC_IIR_MULTI_CYCLE_MODE_SHIFT                    (12)
 
 // reg_130
+#define CODEC_CODEC_FB_CHECK_ENABLE_CH0                     (1 << 0)
+#define CODEC_CODEC_FB_CHECK_ACC_SAMPLE_RATE_CH0(n)         (((n) & 0x3) << 1)
+#define CODEC_CODEC_FB_CHECK_ACC_SAMPLE_RATE_CH0_MASK       (0x3 << 1)
+#define CODEC_CODEC_FB_CHECK_ACC_SAMPLE_RATE_CH0_SHIFT      (1)
+#define CODEC_CODEC_FB_CHECK_SRC_SEL_CH0(n)                 (((n) & 0x3) << 3)
+#define CODEC_CODEC_FB_CHECK_SRC_SEL_CH0_MASK               (0x3 << 3)
+#define CODEC_CODEC_FB_CHECK_SRC_SEL_CH0_SHIFT              (3)
+#define CODEC_CODEC_FB_CHECK_KEEP_SEL_CH0                   (1 << 5)
+#define CODEC_CODEC_FB_CHECK_ACC_WINDOW_CH0(n)              (((n) & 0xFFF) << 6)
+#define CODEC_CODEC_FB_CHECK_ACC_WINDOW_CH0_MASK            (0xFFF << 6)
+#define CODEC_CODEC_FB_CHECK_ACC_WINDOW_CH0_SHIFT           (6)
+#define CODEC_CODEC_FB_CHECK_TRIG_WINDOW_CH0(n)             (((n) & 0x3FF) << 18)
+#define CODEC_CODEC_FB_CHECK_TRIG_WINDOW_CH0_MASK           (0x3FF << 18)
+#define CODEC_CODEC_FB_CHECK_TRIG_WINDOW_CH0_SHIFT          (18)
+#define CODEC_CODEC_FB_CHECK_KEEP_CH0                       (1 << 28)
 
 // reg_134
+#define CODEC_CODEC_FB_CHECK_ENABLE_CH1                     (1 << 0)
+#define CODEC_CODEC_FB_CHECK_ACC_SAMPLE_RATE_CH1(n)         (((n) & 0x3) << 1)
+#define CODEC_CODEC_FB_CHECK_ACC_SAMPLE_RATE_CH1_MASK       (0x3 << 1)
+#define CODEC_CODEC_FB_CHECK_ACC_SAMPLE_RATE_CH1_SHIFT      (1)
+#define CODEC_CODEC_FB_CHECK_SRC_SEL_CH1(n)                 (((n) & 0x3) << 3)
+#define CODEC_CODEC_FB_CHECK_SRC_SEL_CH1_MASK               (0x3 << 3)
+#define CODEC_CODEC_FB_CHECK_SRC_SEL_CH1_SHIFT              (3)
+#define CODEC_CODEC_FB_CHECK_KEEP_SEL_CH1                   (1 << 5)
+#define CODEC_CODEC_FB_CHECK_ACC_WINDOW_CH1(n)              (((n) & 0xFFF) << 6)
+#define CODEC_CODEC_FB_CHECK_ACC_WINDOW_CH1_MASK            (0xFFF << 6)
+#define CODEC_CODEC_FB_CHECK_ACC_WINDOW_CH1_SHIFT           (6)
+#define CODEC_CODEC_FB_CHECK_TRIG_WINDOW_CH1(n)             (((n) & 0x3FF) << 18)
+#define CODEC_CODEC_FB_CHECK_TRIG_WINDOW_CH1_MASK           (0x3FF << 18)
+#define CODEC_CODEC_FB_CHECK_TRIG_WINDOW_CH1_SHIFT          (18)
+#define CODEC_CODEC_FB_CHECK_KEEP_CH1                       (1 << 28)
 
 // reg_138
+#define CODEC_CODEC_FB_CHECK_THRESHOLD_CH0(n)               (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_CODEC_FB_CHECK_THRESHOLD_CH0_MASK             (0xFFFFFFFF << 0)
+#define CODEC_CODEC_FB_CHECK_THRESHOLD_CH0_SHIFT            (0)
 
 // reg_13c
+#define CODEC_CODEC_FB_CHECK_THRESHOLD_CH1(n)               (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_CODEC_FB_CHECK_THRESHOLD_CH1_MASK             (0xFFFFFFFF << 0)
+#define CODEC_CODEC_FB_CHECK_THRESHOLD_CH1_SHIFT            (0)
 
 // reg_140
+#define CODEC_CODEC_FB_CHECK_DATA_AVG_KEEP_CH0(n)           (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_CODEC_FB_CHECK_DATA_AVG_KEEP_CH0_MASK         (0xFFFFFFFF << 0)
+#define CODEC_CODEC_FB_CHECK_DATA_AVG_KEEP_CH0_SHIFT        (0)
 
 // reg_144
+#define CODEC_CODEC_FB_CHECK_DATA_AVG_KEEP_CH1(n)           (((n) & 0xFFFFFFFF) << 0)
+#define CODEC_CODEC_FB_CHECK_DATA_AVG_KEEP_CH1_MASK         (0xFFFFFFFF << 0)
+#define CODEC_CODEC_FB_CHECK_DATA_AVG_KEEP_CH1_SHIFT        (0)
 
 // reg_148
 #define CODEC_VAD_EN                                        (1 << 0)
@@ -912,7 +1250,7 @@ struct CODEC_T {
 #define CODEC_VAD_DC_CANCEL_BYPASS                          (1 << 2)
 #define CODEC_VAD_PRE_BYPASS                                (1 << 3)
 #define CODEC_VAD_DIG_MODE                                  (1 << 4)
-#define CODEC_VAD_FINISH                                    (1 << 24)
+#define CODEC_VAD_FINISH                                    (1 << 5)
 
 // reg_14c
 #define CODEC_VAD_U_DC(n)                                   (((n) & 0xF) << 0)
@@ -970,9 +1308,12 @@ struct CODEC_T {
 #define CODEC_VAD_PSD_TH2_SHIFT                             (0)
 
 // reg_160
-#define CODEC_VAD_MEM_ADDR_CNT(n)                           (((n) & 0x1FFFF) << 0)
-#define CODEC_VAD_MEM_ADDR_CNT_MASK                         (0x1FFFF << 0)
-#define CODEC_VAD_MEM_ADDR_CNT_SHIFT                        (0)
+#define CODEC_VAD_MEM_ADDR_CNT(n)                           (((n) & 0x1FFF) << 1)
+#define CODEC_VAD_MEM_ADDR_CNT_MASK                         (0x1FFF << 1)
+#define CODEC_VAD_MEM_ADDR_CNT_SHIFT                        (1)
+#define CODEC_VAD_MEM_DATA_CNT(n)                           (((n) & 0x1FFF) << 15)
+#define CODEC_VAD_MEM_DATA_CNT_MASK                         (0x1FFF << 15)
+#define CODEC_VAD_MEM_DATA_CNT_SHIFT                        (15)
 
 // reg_164
 #define CODEC_SMIN_SYC(n)                                   (((n) & 0x7FFFFFF) << 0)
@@ -985,6 +1326,18 @@ struct CODEC_T {
 #define CODEC_PSD_SYC_SHIFT                                 (0)
 
 // reg_170
+#define CODEC_FIR_CH0_STATE(n)                              (((n) & 0xFF) << 0)
+#define CODEC_FIR_CH0_STATE_MASK                            (0xFF << 0)
+#define CODEC_FIR_CH0_STATE_SHIFT                           (0)
+#define CODEC_FIR_CH1_STATE(n)                              (((n) & 0xFF) << 8)
+#define CODEC_FIR_CH1_STATE_MASK                            (0xFF << 8)
+#define CODEC_FIR_CH1_STATE_SHIFT                           (8)
+#define CODEC_FIR_CH2_STATE(n)                              (((n) & 0xFF) << 16)
+#define CODEC_FIR_CH2_STATE_MASK                            (0xFF << 16)
+#define CODEC_FIR_CH2_STATE_SHIFT                           (16)
+#define CODEC_FIR_CH3_STATE(n)                              (((n) & 0xFF) << 24)
+#define CODEC_FIR_CH3_STATE_MASK                            (0xFF << 24)
+#define CODEC_FIR_CH3_STATE_SHIFT                           (24)
 
 // reg_174
 #define CODEC_CODEC_ADC_DC_DOUT_CH0_SYNC(n)                 (((n) & 0x1FFFFF) << 0)
@@ -1042,96 +1395,96 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_DC_UPDATE_CH4                       (1 << 15)
 
 // reg_1a0
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP0_CH0(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP0_CH0_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP0_CH0_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP1_CH0(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP1_CH0_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP1_CH0_SHIFT            (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP0(n)                   (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP0_MASK                 (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP0_SHIFT                (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP1(n)                   (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP1_MASK                 (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP1_SHIFT                (14)
 
 // reg_1a4
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP2_CH0(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP2_CH0_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP2_CH0_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP3_CH0(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP3_CH0_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP3_CH0_SHIFT            (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP2(n)                   (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP2_MASK                 (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP2_SHIFT                (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP3(n)                   (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP3_MASK                 (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP3_SHIFT                (14)
 
 // reg_1a8
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_CH0(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_CH0_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_CH0_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_CH0(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_CH0_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_CH0_SHIFT            (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP4(n)                   (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_MASK                 (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_SHIFT                (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP5(n)                   (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_MASK                 (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_SHIFT                (14)
 
 // reg_1ac
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_CH0(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_CH0_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_CH0_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_CH0(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_CH0_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_CH0_SHIFT            (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP6(n)                   (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_MASK                 (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_SHIFT                (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP7(n)                   (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_MASK                 (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_SHIFT                (14)
 
 // reg_1b0
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_CH0(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_CH0_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_CH0_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_CH0(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_CH0_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_CH0_SHIFT            (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP8(n)                   (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_MASK                 (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_SHIFT                (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP9(n)                   (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_MASK                 (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_SHIFT                (14)
 
 // reg_1b4
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_CH0(n)              (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_CH0_MASK            (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_CH0_SHIFT           (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_CH0(n)              (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_CH0_MASK            (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_CH0_SHIFT           (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP10(n)                  (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_MASK                (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_SHIFT               (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP11(n)                  (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_MASK                (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_SHIFT               (14)
 
 // reg_1b8
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_CH0(n)              (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_CH0_MASK            (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_CH0_SHIFT           (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_CH0(n)              (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_CH0_MASK            (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_CH0_SHIFT           (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP12(n)                  (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_MASK                (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_SHIFT               (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP13(n)                  (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_MASK                (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_SHIFT               (14)
 
 // reg_1bc
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_CH0(n)              (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_CH0_MASK            (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_CH0_SHIFT           (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_CH0(n)              (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_CH0_MASK            (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_CH0_SHIFT           (14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP14(n)                  (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_MASK                (0x3FFF << 0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_SHIFT               (0)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP15(n)                  (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_MASK                (0x3FFF << 14)
+#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_SHIFT               (14)
 
 // reg_1c0
 #define CODEC_CODEC_ADC_DRE_ENABLE_CH0                      (1 << 0)
-#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH0(n)                (((n) & 0x7) << 1)
-#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH0_MASK              (0x7 << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH0(n)                (((n) & 0x3) << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH0_MASK              (0x3 << 1)
 #define CODEC_CODEC_ADC_DRE_STEP_MODE_CH0_SHIFT             (1)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH0(n)            (((n) & 0xF) << 4)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH0_MASK          (0xF << 4)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH0_SHIFT         (4)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH0(n)             (((n) & 0xF) << 8)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH0_MASK           (0xF << 8)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH0_SHIFT          (8)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH0(n)                (((n) & 0x7) << 12)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH0_MASK              (0x7 << 12)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH0_SHIFT             (12)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH0(n)                (((n) & 0x1F) << 15)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH0_MASK              (0x1F << 15)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH0_SHIFT             (15)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH0          (1 << 20)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH0(n)                  (((n) & 0x3) << 21)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH0_MASK                (0x3 << 21)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH0_SHIFT               (21)
-#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH0            (1 << 23)
-#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH0                   (1 << 24)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH0(n)           (((n) & 0x3) << 25)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH0_MASK         (0x3 << 25)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH0_SHIFT        (25)
-#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH0_SYNC            (1 << 27)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH0(n)            (((n) & 0xF) << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH0_MASK          (0xF << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH0_SHIFT         (3)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH0(n)             (((n) & 0xF) << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH0_MASK           (0xF << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH0_SHIFT          (7)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH0(n)                (((n) & 0x7) << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH0_MASK              (0x7 << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH0_SHIFT             (11)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH0(n)                (((n) & 0x1F) << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH0_MASK              (0x1F << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH0_SHIFT             (14)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH0          (1 << 19)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH0(n)                  (((n) & 0x3) << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH0_MASK                (0x3 << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH0_SHIFT               (20)
+#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH0            (1 << 22)
+#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH0                   (1 << 23)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH0(n)           (((n) & 0x3) << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH0_MASK         (0x3 << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH0_SHIFT        (24)
+#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH0                 (1 << 26)
 
 // reg_1c4
 #define CODEC_CODEC_ADC_DRE_AMP_HIGH_CH0(n)                 (((n) & 0x7FF) << 0)
@@ -1143,31 +1496,31 @@ struct CODEC_T {
 
 // reg_1c8
 #define CODEC_CODEC_ADC_DRE_ENABLE_CH1                      (1 << 0)
-#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH1(n)                (((n) & 0x7) << 1)
-#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH1_MASK              (0x7 << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH1(n)                (((n) & 0x3) << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH1_MASK              (0x3 << 1)
 #define CODEC_CODEC_ADC_DRE_STEP_MODE_CH1_SHIFT             (1)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH1(n)            (((n) & 0xF) << 4)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH1_MASK          (0xF << 4)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH1_SHIFT         (4)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH1(n)             (((n) & 0xF) << 8)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH1_MASK           (0xF << 8)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH1_SHIFT          (8)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH1(n)                (((n) & 0x7) << 12)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH1_MASK              (0x7 << 12)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH1_SHIFT             (12)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH1(n)                (((n) & 0x1F) << 15)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH1_MASK              (0x1F << 15)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH1_SHIFT             (15)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH1          (1 << 20)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH1(n)                  (((n) & 0x3) << 21)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH1_MASK                (0x3 << 21)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH1_SHIFT               (21)
-#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH1            (1 << 23)
-#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH1                   (1 << 24)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH1(n)           (((n) & 0x3) << 25)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH1_MASK         (0x3 << 25)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH1_SHIFT        (25)
-#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH1_SYNC            (1 << 27)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH1(n)            (((n) & 0xF) << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH1_MASK          (0xF << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH1_SHIFT         (3)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH1(n)             (((n) & 0xF) << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH1_MASK           (0xF << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH1_SHIFT          (7)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH1(n)                (((n) & 0x7) << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH1_MASK              (0x7 << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH1_SHIFT             (11)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH1(n)                (((n) & 0x1F) << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH1_MASK              (0x1F << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH1_SHIFT             (14)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH1          (1 << 19)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH1(n)                  (((n) & 0x3) << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH1_MASK                (0x3 << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH1_SHIFT               (20)
+#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH1            (1 << 22)
+#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH1                   (1 << 23)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH1(n)           (((n) & 0x3) << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH1_MASK         (0x3 << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH1_SHIFT        (24)
+#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH1                 (1 << 26)
 
 // reg_1cc
 #define CODEC_CODEC_ADC_DRE_AMP_HIGH_CH1(n)                 (((n) & 0x7FF) << 0)
@@ -1179,31 +1532,31 @@ struct CODEC_T {
 
 // reg_1d0
 #define CODEC_CODEC_ADC_DRE_ENABLE_CH2                      (1 << 0)
-#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH2(n)                (((n) & 0x7) << 1)
-#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH2_MASK              (0x7 << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH2(n)                (((n) & 0x3) << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH2_MASK              (0x3 << 1)
 #define CODEC_CODEC_ADC_DRE_STEP_MODE_CH2_SHIFT             (1)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH2(n)            (((n) & 0xF) << 4)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH2_MASK          (0xF << 4)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH2_SHIFT         (4)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH2(n)             (((n) & 0xF) << 8)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH2_MASK           (0xF << 8)
-#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH2_SHIFT          (8)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH2(n)                (((n) & 0x7) << 12)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH2_MASK              (0x7 << 12)
-#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH2_SHIFT             (12)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH2(n)                (((n) & 0x1F) << 15)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH2_MASK              (0x1F << 15)
-#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH2_SHIFT             (15)
-#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH2          (1 << 20)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH2(n)                  (((n) & 0x3) << 21)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH2_MASK                (0x3 << 21)
-#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH2_SHIFT               (21)
-#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH2            (1 << 23)
-#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH2                   (1 << 24)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH2(n)           (((n) & 0x3) << 25)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH2_MASK         (0x3 << 25)
-#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH2_SHIFT        (25)
-#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH2_SYNC            (1 << 27)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH2(n)            (((n) & 0xF) << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH2_MASK          (0xF << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH2_SHIFT         (3)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH2(n)             (((n) & 0xF) << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH2_MASK           (0xF << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH2_SHIFT          (7)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH2(n)                (((n) & 0x7) << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH2_MASK              (0x7 << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH2_SHIFT             (11)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH2(n)                (((n) & 0x1F) << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH2_MASK              (0x1F << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH2_SHIFT             (14)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH2          (1 << 19)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH2(n)                  (((n) & 0x3) << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH2_MASK                (0x3 << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH2_SHIFT               (20)
+#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH2            (1 << 22)
+#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH2                   (1 << 23)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH2(n)           (((n) & 0x3) << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH2_MASK         (0x3 << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH2_SHIFT        (24)
+#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH2                 (1 << 26)
 
 // reg_1d4
 #define CODEC_CODEC_ADC_DRE_AMP_HIGH_CH2(n)                 (((n) & 0x7FF) << 0)
@@ -1214,8 +1567,40 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_DRE_WINDOW_CH2_SHIFT                (11)
 
 // reg_1d8
+#define CODEC_CODEC_ADC_DRE_ENABLE_CH3                      (1 << 0)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH3(n)                (((n) & 0x3) << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH3_MASK              (0x3 << 1)
+#define CODEC_CODEC_ADC_DRE_STEP_MODE_CH3_SHIFT             (1)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH3(n)            (((n) & 0xF) << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH3_MASK          (0xF << 3)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_CH3_SHIFT         (3)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH3(n)             (((n) & 0xF) << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH3_MASK           (0xF << 7)
+#define CODEC_CODEC_ADC_DRE_INI_ANA_GAIN_CH3_SHIFT          (7)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH3(n)                (((n) & 0x7) << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH3_MASK              (0x7 << 11)
+#define CODEC_CODEC_ADC_DRE_DELAY_DIG_CH3_SHIFT             (11)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH3(n)                (((n) & 0x1F) << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH3_MASK              (0x1F << 14)
+#define CODEC_CODEC_ADC_DRE_DELAY_ANA_CH3_SHIFT             (14)
+#define CODEC_CODEC_ADC_DRE_THD_DB_OFFSET_SIGN_CH3          (1 << 19)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH3(n)                  (((n) & 0x3) << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH3_MASK                (0x3 << 20)
+#define CODEC_CODEC_ADC_DRE_BIT_SEL_CH3_SHIFT               (20)
+#define CODEC_CODEC_ADC_DRE_OVERFLOW_MUTE_EN_CH3            (1 << 22)
+#define CODEC_CODEC_ADC_DRE_MUTE_MODE_CH3                   (1 << 23)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH3(n)           (((n) & 0x3) << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH3_MASK         (0x3 << 24)
+#define CODEC_CODEC_ADC_DRE_MUTE_RANGE_SEL_CH3_SHIFT        (24)
+#define CODEC_CODEC_ADC_DRE_MUTE_STATUS_CH3                 (1 << 26)
 
 // reg_1dc
+#define CODEC_CODEC_ADC_DRE_AMP_HIGH_CH3(n)                 (((n) & 0x7FF) << 0)
+#define CODEC_CODEC_ADC_DRE_AMP_HIGH_CH3_MASK               (0x7FF << 0)
+#define CODEC_CODEC_ADC_DRE_AMP_HIGH_CH3_SHIFT              (0)
+#define CODEC_CODEC_ADC_DRE_WINDOW_CH3(n)                   (((n) & 0xFFFFF) << 11)
+#define CODEC_CODEC_ADC_DRE_WINDOW_CH3_MASK                 (0xFFFFF << 11)
+#define CODEC_CODEC_ADC_DRE_WINDOW_CH3_SHIFT                (11)
 
 // reg_1e0
 #define CODEC_CODEC_ADC_DRE_GAIN_STEP0_CH0(n)               (((n) & 0x3FFF) << 0)
@@ -1234,28 +1619,52 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_DRE_GAIN_STEP3_CH0_SHIFT            (14)
 
 // reg_1e8
-#define CODEC_CODEC_ADC_DRE_DC_STEP0_CH0(n)                 (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_ADC_DRE_DC_STEP0_CH0_MASK               (0x3FFF << 0)
-#define CODEC_CODEC_ADC_DRE_DC_STEP0_CH0_SHIFT              (0)
-#define CODEC_CODEC_ADC_DRE_DC_STEP1_CH0(n)                 (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_ADC_DRE_DC_STEP1_CH0_MASK               (0x3FFF << 14)
-#define CODEC_CODEC_ADC_DRE_DC_STEP1_CH0_SHIFT              (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP4_CH0(n)               (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP4_CH0_MASK             (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP4_CH0_SHIFT            (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP5_CH0(n)               (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP5_CH0_MASK             (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP5_CH0_SHIFT            (14)
 
 // reg_1ec
-#define CODEC_CODEC_ADC_DRE_DC_STEP2_CH0(n)                 (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_ADC_DRE_DC_STEP2_CH0_MASK               (0x3FFF << 0)
-#define CODEC_CODEC_ADC_DRE_DC_STEP2_CH0_SHIFT              (0)
-#define CODEC_CODEC_ADC_DRE_DC_STEP3_CH0(n)                 (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_ADC_DRE_DC_STEP3_CH0_MASK               (0x3FFF << 14)
-#define CODEC_CODEC_ADC_DRE_DC_STEP3_CH0_SHIFT              (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP6_CH0(n)               (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP6_CH0_MASK             (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP6_CH0_SHIFT            (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP7_CH0(n)               (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP7_CH0_MASK             (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP7_CH0_SHIFT            (14)
 
 // reg_1f0
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP8_CH0(n)               (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP8_CH0_MASK             (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP8_CH0_SHIFT            (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP9_CH0(n)               (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP9_CH0_MASK             (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP9_CH0_SHIFT            (14)
 
 // reg_1f4
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP10_CH0(n)              (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP10_CH0_MASK            (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP10_CH0_SHIFT           (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP11_CH0(n)              (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP11_CH0_MASK            (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP11_CH0_SHIFT           (14)
 
 // reg_1f8
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP12_CH0(n)              (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP12_CH0_MASK            (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP12_CH0_SHIFT           (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP13_CH0(n)              (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP13_CH0_MASK            (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP13_CH0_SHIFT           (14)
 
 // reg_1fc
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP14_CH0(n)              (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP14_CH0_MASK            (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP14_CH0_SHIFT           (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP15_CH0(n)              (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP15_CH0_MASK            (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP15_CH0_SHIFT           (14)
 
 // reg_200
 #define CODEC_CODEC_ADC_DRE_GAIN_STEP0_CH1(n)               (((n) & 0x3FFF) << 0)
@@ -1274,52 +1683,52 @@ struct CODEC_T {
 #define CODEC_CODEC_ADC_DRE_GAIN_STEP3_CH1_SHIFT            (14)
 
 // reg_208
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_CH1(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_CH1_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP4_CH1_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_CH1(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_CH1_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP5_CH1_SHIFT            (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP4_CH1(n)               (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP4_CH1_MASK             (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP4_CH1_SHIFT            (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP5_CH1(n)               (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP5_CH1_MASK             (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP5_CH1_SHIFT            (14)
 
 // reg_20c
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_CH1(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_CH1_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP6_CH1_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_CH1(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_CH1_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP7_CH1_SHIFT            (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP6_CH1(n)               (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP6_CH1_MASK             (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP6_CH1_SHIFT            (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP7_CH1(n)               (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP7_CH1_MASK             (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP7_CH1_SHIFT            (14)
 
 // reg_210
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_CH1(n)               (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_CH1_MASK             (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP8_CH1_SHIFT            (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_CH1(n)               (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_CH1_MASK             (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP9_CH1_SHIFT            (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP8_CH1(n)               (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP8_CH1_MASK             (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP8_CH1_SHIFT            (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP9_CH1(n)               (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP9_CH1_MASK             (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP9_CH1_SHIFT            (14)
 
 // reg_214
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_CH1(n)              (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_CH1_MASK            (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP10_CH1_SHIFT           (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_CH1(n)              (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_CH1_MASK            (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP11_CH1_SHIFT           (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP10_CH1(n)              (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP10_CH1_MASK            (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP10_CH1_SHIFT           (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP11_CH1(n)              (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP11_CH1_MASK            (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP11_CH1_SHIFT           (14)
 
 // reg_218
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_CH1(n)              (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_CH1_MASK            (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP12_CH1_SHIFT           (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_CH1(n)              (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_CH1_MASK            (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP13_CH1_SHIFT           (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP12_CH1(n)              (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP12_CH1_MASK            (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP12_CH1_SHIFT           (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP13_CH1(n)              (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP13_CH1_MASK            (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP13_CH1_SHIFT           (14)
 
 // reg_21c
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_CH1(n)              (((n) & 0x3FFF) << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_CH1_MASK            (0x3FFF << 0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP14_CH1_SHIFT           (0)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_CH1(n)              (((n) & 0x3FFF) << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_CH1_MASK            (0x3FFF << 14)
-#define CODEC_CODEC_DAC_DRE_GAIN_STEP15_CH1_SHIFT           (14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP14_CH1(n)              (((n) & 0x3FFF) << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP14_CH1_MASK            (0x3FFF << 0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP14_CH1_SHIFT           (0)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP15_CH1(n)              (((n) & 0x3FFF) << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP15_CH1_MASK            (0x3FFF << 14)
+#define CODEC_CODEC_ADC_DRE_GAIN_STEP15_CH1_SHIFT           (14)
 
 // reg_220
 #define CODEC_VAD_DELAY1(n)                                 (((n) & 0x3FF) << 0)
@@ -1332,9 +1741,44 @@ struct CODEC_T {
 #define CODEC_VAD_DELAY2_SHIFT                              (0)
 
 // reg_228
+#define CODEC_CODEC_MC_ENABLE_CH0                           (1 << 0)
+#define CODEC_CODEC_MC_SEL_CH0                              (1 << 1)
+#define CODEC_CODEC_DOWN_SEL_MC_CH0(n)                      (((n) & 0x3) << 2)
+#define CODEC_CODEC_DOWN_SEL_MC_CH0_MASK                    (0x3 << 2)
+#define CODEC_CODEC_DOWN_SEL_MC_CH0_SHIFT                   (2)
+#define CODEC_CODEC_MC_SINC_BYPASS_CH0                      (1 << 4)
+#define CODEC_CODEC_MC_ENABLE_CH1                           (1 << 5)
+#define CODEC_CODEC_MC_SEL_CH1                              (1 << 6)
+#define CODEC_CODEC_DOWN_SEL_MC_CH1(n)                      (((n) & 0x3) << 7)
+#define CODEC_CODEC_DOWN_SEL_MC_CH1_MASK                    (0x3 << 7)
+#define CODEC_CODEC_DOWN_SEL_MC_CH1_SHIFT                   (7)
+#define CODEC_CODEC_MC_SINC_BYPASS_CH1                      (1 << 9)
+#define CODEC_CODEC_RESAMPLE_MC_ENABLE                      (1 << 10)
+#define CODEC_CODEC_RESAMPLE_MC_DUAL_CH                     (1 << 11)
 
 // reg_22c
+#define CODEC_CODEC_TT_ENABLE                               (1 << 0)
+#define CODEC_CODEC_MUTE_GAIN_COEF_TT(n)                    (((n) & 0xFFF) << 1)
+#define CODEC_CODEC_MUTE_GAIN_COEF_TT_MASK                  (0xFFF << 1)
+#define CODEC_CODEC_MUTE_GAIN_COEF_TT_SHIFT                 (1)
+#define CODEC_CODEC_MUTE_GAIN_PASS0_TT                      (1 << 13)
+#define CODEC_CODEC_MM_ENABLE                               (1 << 14)
+#define CODEC_CODEC_MUTE_GAIN_COEF_MM(n)                    (((n) & 0xFFF) << 15)
+#define CODEC_CODEC_MUTE_GAIN_COEF_MM_MASK                  (0xFFF << 15)
+#define CODEC_CODEC_MUTE_GAIN_COEF_MM_SHIFT                 (15)
+#define CODEC_CODEC_MUTE_GAIN_PASS0_MM                      (1 << 27)
 
 // reg_230
+#define CODEC_CODEC_MM_FIFO_EN                              (1 << 0)
+#define CODEC_CODEC_MM_FIFO_BYPASS                          (1 << 1)
+#define CODEC_CODEC_MM_DELAY_UPDATE                         (1 << 2)
+#define CODEC_CODEC_MM_DELAY(n)                             (((n) & 0x1F) << 3)
+#define CODEC_CODEC_MM_DELAY_MASK                           (0x1F << 3)
+#define CODEC_CODEC_MM_DELAY_SHIFT                          (3)
+#define CODEC_VAD_EXT_EN                                    (1 << 8)
+#define CODEC_VAD_SRC_SEL                                   (1 << 9)
+#define CODEC_VAD_DATA_EXT_SWAP                             (1 << 10)
+#define CODEC_MC_EN_SEL                                     (1 << 11)
+#define CODEC_MC_RATE_SRC_SEL                               (1 << 12)
 
 #endif

platform/hal/best2300p/reg_iomux_best2300p.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/best2300p/reg_iomux_best2300p.h bes/platform/hal/best2300p/reg_iomux_best2300p.h
index 9610b1208c5..de4a2fd867f 100644
--- a/platform/hal/best2300p/reg_iomux_best2300p.h
+++ b/platform/hal/best2300p/reg_iomux_best2300p.h
@@ -263,16 +263,16 @@ struct IOMUX_T {
 #define IOMUX_GPIO_PCM_MODE                     (1 << 2)
 #define IOMUX_BT_RXTX_SW_EN                     (1 << 3)
 #define IOMUX_I2C1_M_SEL_GPIO                   (1 << 4)
-#define IOMUX_SPILCD0_WM3                       (1 << 6)
-#define IOMUX_SPILCD1_WM3                       (1 << 7)
-#define IOMUX_CFG_EN_CLK_REQIN                  (1 << 10)
-#define IOMUX_CFG_POL_CLK_REQIN                 (1 << 11)
-#define IOMUX_CFG_EN_CLK_REQOUT                 (1 << 12)
-#define IOMUX_CFG_POL_CLK_REQOUT                (1 << 13)
-#define IOMUX_BT_UART_HALFN                     (1 << 14)
-#define IOMUX_UART0_HALFN                       (1 << 15)
-#define IOMUX_UART1_HALFN                       (1 << 16)
-#define IOMUX_UART2_HALFN                       (1 << 17)
+#define IOMUX_SPILCD0_WM3                       (1 << 5)
+#define IOMUX_SPILCD1_WM3                       (1 << 6)
+#define IOMUX_CFG_EN_CLK_REQIN                  (1 << 7)
+#define IOMUX_CFG_POL_CLK_REQIN                 (1 << 8)
+#define IOMUX_CFG_EN_CLK_REQOUT                 (1 << 9)
+#define IOMUX_CFG_POL_CLK_REQOUT                (1 << 10)
+#define IOMUX_BT_UART_HALFN                     (1 << 11)
+#define IOMUX_UART0_HALFN                       (1 << 12)
+#define IOMUX_UART1_HALFN                       (1 << 13)
+#define IOMUX_UART2_HALFN                       (1 << 14)
 
 // reg_54
 #define IOMUX_CFG_GPIO_OENB_P0_POL(n)           (((n) & 0xFF) << 0)

platform/hal/hal_aud.h

Declared BES License in SDK version.
Relicense to Apache-2.0.

Diff of changes (click to view)

diff --git reconstruction/platform/hal/hal_aud.h bes/platform/hal/hal_aud.h
index 0a97765a049..77f862a4d1e 100644
--- a/platform/hal/hal_aud.h
+++ b/platform/hal/hal_aud.h
@@ -70,10 +70,10 @@ extern "C" {
 #define CODEC_CMU_DIV                       8
 #define CODEC_PLAYBACK_BIT_DEPTH            20
 
-#elif defined(CHIP_BEST2003)
+#elif defined(CHIP_BEST2001)
 
-#define CODEC_PLL_DIV                       156
-#define CODEC_CMU_DIV                       13
+#define CODEC_PLL_DIV                       38
+#define CODEC_CMU_DIV                       8
 #define CODEC_PLAYBACK_BIT_DEPTH            20
 
 #else
@@ -135,8 +135,10 @@ enum AUD_SAMPRATE_T {
     AUD_SAMPRATE_352800 = 352800,
     AUD_SAMPRATE_384000 = 384000,
     AUD_SAMPRATE_406250 = 406250,     // 26M / 64
+    AUD_SAMPRATE_512000 = 512000,
     AUD_SAMPRATE_705600 = 705600,
     AUD_SAMPRATE_768000 = 768000,
+    AUD_SAMPRATE_1024000 = 1024000,
 };
 
 enum AUD_CHANNEL_NUM_T {
@@ -202,7 +204,9 @@ enum AUD_STREAM_ID_T {
     AUD_STREAM_ID_0 = 0,
     AUD_STREAM_ID_1,
     AUD_STREAM_ID_2,
+#ifdef __ANC_ASSIST__
     AUD_STREAM_ID_3,
+#endif
     AUD_STREAM_ID_NUM,
 };
 
@@ -223,8 +227,11 @@ enum AUD_IO_PATH_T {
     AUD_INPUT_PATH_ASRMIC,
     AUD_INPUT_PATH_LINEIN,
     AUD_INPUT_PATH_NTMIC,
+    AUD_INPUT_PATH_ANC_WNR,
     AUD_INPUT_PATH_USBAUDIO,
-    AUD_INPUT_PATH_ANC_ASSIST,
+#ifdef __ANC_ASSIST__
+    AUD_INPUT_PATH_AF_ANC,
+#endif
     // Output path
     AUD_OUTPUT_PATH_SPEAKER,
 };
@@ -235,11 +242,11 @@ struct AUD_IO_PATH_CFG_T {
 };
 
 enum ANC_TYPE_T {
-    ANC_NOTYPE          = 0,
-    ANC_FEEDFORWARD     = (1 << 0),
-    ANC_FEEDBACK        = (1 << 1),
-    ANC_TALKTHRU        = (1 << 2),
-    ANC_MUSICCANCLE     = (1 << 3),
+    ANC_NOTYPE          = (1 << 0),
+    ANC_FEEDFORWARD     = (1 << 1),
+    ANC_FEEDBACK        = (1 << 2),
+    ANC_TALKTHRU        = (1 << 3),
+    ANC_MUSICCANCLE     = (1 << 4),
 };
 
 struct CODEC_DAC_VOL_T {
@@ -251,7 +258,10 @@ struct CODEC_DAC_VOL_T {
 typedef signed char CODEC_ADC_VOL_T;
 
 enum TGT_VOLUME_LEVEL_T {
-    TGT_VOLUME_LEVEL_MUTE = 0,
+    TGT_VOLUME_LEVEL_WARNINGTONE = 0,
+
+    TGT_VOLUME_LEVEL_MUTE,
+    TGT_VOLUME_LEVEL_0,
     TGT_VOLUME_LEVEL_1,
     TGT_VOLUME_LEVEL_2,
     TGT_VOLUME_LEVEL_3,
@@ -272,7 +282,7 @@ enum TGT_VOLUME_LEVEL_T {
 };
 
 enum TGT_ADC_VOL_LEVEL_T {
-    TGT_ADC_VOL_LEVEL_0 = 0,
+    TGT_ADC_VOL_LEVEL_0,
     TGT_ADC_VOL_LEVEL_1,
     TGT_ADC_VOL_LEVEL_2,
     TGT_ADC_VOL_LEVEL_3,

OneDeuxTriSeiGo mentioned this issue

Tracking Issue for Relicensing Effort #76

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