fix: only pass TSC deadline feature if the host supports it

AMD hosts do not have TSC deadline enabled, and that seems to cause issues like in firecracker-microvm#4099. Only expose TSC_DEADLINE to the guest if the host supports it. Closes firecracker-microvm#4099 Signed-off-by: Pablo Barbáchano <[email protected]>
pb8o · Jun 26, 2024 · ad6c967 · ad6c967
1 parent 950b89a
commit ad6c967
Show file tree

Hide file tree

Showing 2 changed files with 11 additions and 2 deletions.
diff --git a/src/vmm/src/cpu_config/x86_64/cpuid/normalize.rs b/src/vmm/src/cpu_config/x86_64/cpuid/normalize.rs
@@ -247,7 +247,14 @@ impl super::Cpuid {
         // operation using a TSC deadline value.
         //
         // tsc_deadline: 24,
-        set_bit(&mut leaf_1.result.ecx, ECX_TSC_DEADLINE_BITINDEX, true);
+        let host_leaf_1 = cpuid(0x1);
+        // Pass-through the value of the host
+        let host_tsc_deadline = ((1 << ECX_TSC_DEADLINE_BITINDEX) & host_leaf_1.ecx) != 0;
+        set_bit(
+            &mut leaf_1.result.ecx,
+            ECX_TSC_DEADLINE_BITINDEX,
+            host_tsc_deadline,
+        );
 
         // Hypervisor bit
         set_bit(&mut leaf_1.result.ecx, ECX_HYPERVISOR_BITINDEX, true);

diff --git a/tests/integration_tests/functional/test_cpu_features.py b/tests/integration_tests/functional/test_cpu_features.py
@@ -903,7 +903,9 @@ def check_enabled_features(test_microvm, cpu_template):
         "SSE4.2 extensions": "true",
         "x2APIC: extended xAPIC support": "true",
         "POPCNT instruction": "true",
-        "time stamp counter deadline": "true",
+        "time stamp counter deadline": (
+            "true" if global_props.cpu_vendor == "intel" else "false"
+        ),
         "XSAVE/XSTOR states": "true",
         "OS-enabled XSAVE/XSTOR": "true",
         "AVX: advanced vector extensions": "true",