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    • User examples for various open-source FPGA toolchaings
      Verilog
      0100Updated Dec 7, 2024Dec 7, 2024
    • Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more
      Shell
      21110Updated Nov 24, 2024Nov 24, 2024
    • IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
      Python
      Apache License 2.0
      79000Updated Nov 21, 2024Nov 21, 2024
    • sample project for openxc7
      Verilog
      2000Updated Oct 8, 2024Oct 8, 2024
    • The core of the CaaS platform, configuration parser and Makefile generator
      Python
      GNU General Public License v3.0
      0020Updated Oct 2, 2024Oct 2, 2024
    • Compiling as a Service backend.
      Python
      MIT License
      2100Updated Aug 7, 2024Aug 7, 2024
    • Universal utility for programming FPGA
      C++
      Apache License 2.0
      268000Updated Jul 13, 2024Jul 13, 2024
    • Demo projects for various Kintex FPGA boards
      Verilog
      BSD 3-Clause "New" or "Revised" License
      17100Updated Jun 12, 2024Jun 12, 2024
    • SystemVerilog
      0100Updated May 5, 2024May 5, 2024
    • new fpgaol platform with CodeEdit, Compiling and Program
      Vue
      MIT License
      2000Updated Apr 17, 2024Apr 17, 2024
    • ss_blast

      Public
      Loading bitstream via Slave SelectMAP 32-bit via ZYNQ AXI GPIO
      C
      1300Updated Apr 13, 2024Apr 13, 2024
    • core_jpeg

      Public
      High throughput JPEG decoder in Verilog for FPGA
      Verilog
      Apache License 2.0
      42000Updated Mar 12, 2024Mar 12, 2024
    • An open source replacement of the Xilinx bootgen application.
      C
      BSD 2-Clause "Simplified" License
      50000Updated Feb 26, 2024Feb 26, 2024
    • Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
      Verilog
      1000Updated Feb 22, 2024Feb 22, 2024
    • Academic project to test the https://caas.symbioticeda.com/ platform.
      Verilog
      1000Updated Feb 17, 2024Feb 17, 2024
    • Vue
      0300Updated Feb 16, 2024Feb 16, 2024
    • Verilog
      1000Updated Feb 8, 2024Feb 8, 2024
    • Verilog
      0000Updated Nov 14, 2023Nov 14, 2023
    • Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)
      C
      MIT License
      5100Updated Sep 5, 2023Sep 5, 2023
    • The name is just cool... Might be something later
      GNU General Public License v3.0
      0000Updated Apr 23, 2023Apr 23, 2023
    • Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7
      Shell
      BSD 3-Clause "New" or "Revised" License
      5000Updated Mar 31, 2023Mar 31, 2023