From 681c30c28b3664910fb8f72893fa1b9ed38f214c Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 3 Dec 2024 12:16:31 +0500
Subject: [PATCH 01/13] Adding support for Zbkb

---
 core/alu.sv                                   | 52 +++++++++++++++++++
 core/decoder.sv                               | 11 ++++
 core/include/ariane_pkg.sv                    | 11 +++-
 core/include/build_config_pkg.sv              |  1 +
 core/include/config_pkg.sv                    |  3 ++
 core/include/cv32a60x_config_pkg.sv           |  1 +
 core/include/cv32a65x_config_pkg.sv           |  1 +
 .../cv32a6_embedded_config_pkg_deprecated.sv  |  2 +
 .../cv32a6_ima_sv32_fpga_config_pkg.sv        |  2 +
 core/include/cv32a6_imac_sv0_config_pkg.sv    |  2 +
 core/include/cv32a6_imac_sv32_config_pkg.sv   |  2 +
 core/include/cv32a6_imafc_sv32_config_pkg.sv  |  2 +
 .../cv64a6_imadfcv_sv39_polara_config_pkg.sv  |  2 +
 core/include/cv64a6_imafdc_sv39_config_pkg.sv |  2 +
 .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv |  2 +
 ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv |  2 +
 .../cv64a6_imafdc_sv39_wb_config_pkg.sv       |  2 +
 .../include/cv64a6_imafdch_sv39_config_pkg.sv |  2 +
 .../cv64a6_imafdch_sv39_wb_config_pkg.sv      |  2 +
 .../include/cv64a6_imafdcv_sv39_config_pkg.sv |  2 +
 core/include/cv64a6_mmu_config_pkg.sv         |  2 +
 verif/sim/cva6.py                             |  6 +--
 22 files changed, 110 insertions(+), 4 deletions(-)

diff --git a/core/alu.sv b/core/alu.sv
index ce19579959..65ae4e8c11 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -51,6 +51,17 @@ module alu
   logic lz_tz_empty, lz_tz_wempty;
   logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
 
+  logic [CVA6Cfg.XLEN-1:0] pack_result;
+  logic [            31:0] packh_result;
+  logic [            63:0] packw_result;
+  logic [CVA6Cfg.XLEN-1:0] brev8_reversed;
+  logic [CVA6Cfg.XLEN-1:0] brev8_result;
+  logic [            15:0] unzip_gen_hi;
+  logic [            15:0] unzip_gen_lo;
+  logic [            31:0] unzip_result;
+  logic [            31:0] zip_gen_even;
+  logic [            31:0] zip_gen_odd;
+  logic [            31:0] zip_result;
   // bit reverse operand_a for left shifts and bit counting
   generate
     genvar k;
@@ -263,6 +274,37 @@ module alu
     end
   end
 
+  // ZKN Instructions
+  if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_block
+    // Generate brev8_reversed by reversing bits within each byte
+    for (int i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen
+      for (int m = 0; m < 8; m++) begin : reverse_bits
+        // Reversing the order of bits within a single byte
+        assign brev8_reversed[(i<<3)+m] = fu_data_i.operand_a[(i<<3)+(7-m)];
+      end
+    end
+    // Generate zip and unzip results
+    for (int n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
+      // Assigning lower and upper half of operand into the even and odd positions of result
+      assign zip_gen_even[n<<1] = fu_data_i.operand_a[n];
+      assign zip_gen_odd[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2];
+      // Assigning even and odd bits of operand into lower and upper halves of result
+      assign unzip_gen_lo[n] = fu_data_i.operand_a[n<<1];
+      assign unzip_gen_hi[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1];
+    end
+    if (CVA6Cfg.IS_XLEN32) begin
+      assign pack_result = {{fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};  // 32-bit pack
+      assign packh_result = {16'b0, {fu_data_i.operand_b[7:0]}, {fu_data_i.operand_a[7:0]}};  // zero extended pack_h
+      assign brev8_result = brev8_reversed;  // 32-bit brev8
+      assign unzip_result = {{unzip_gen_hi}, {unzip_gen_lo}};  // 32-bit unzip
+      assign zip_result = {zip_gen_even} | {zip_gen_odd};  // 32-bit zip
+    end else begin
+      assign pack_result = {{fu_data_i.operand_b[31:0]}, {fu_data_i.operand_a[31:0]}};  // 64-bit pack
+      assign packw_result = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};  // sign extended pack_w
+      assign brev8_result = brev8_reversed;  // 64-bit brev8
+    end
+  end
+
   // -----------
   // Result MUX
   // -----------
@@ -358,5 +400,15 @@ module alu
         default: ;  // default case to suppress unique warning
       endcase
     end
+    if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
+      unique case (fu_data_i.operation)
+        PACK: result_o = pack_result;
+        PACK_H: result_o = packh_result;
+        BREV8: result_o = brev8_result;
+        UNZIP: result_o = unzip_result;
+        ZIP: result_o = zip_result;
+      endcase
+      if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = packw_result;
+    end
   end
 endmodule
diff --git a/core/decoder.sv b/core/decoder.sv
index 65e7c22450..2154299774 100644
--- a/core/decoder.sv
+++ b/core/decoder.sv
@@ -776,6 +776,9 @@ module decoder
                 // Bitwise Shifting
                 {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL;  // rol
                 {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR;  // ror
+                // Packing
+                {7'b000_0100, 3'b100} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; else illegal_instr_bm = 1'b1;  //pack
+                {7'b000_0100, 3'b111} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; else illegal_instr_bm = 1'b1;  //packh
                 // Zero Extend Op RV32 encoding
                 {
                   7'b000_0100, 3'b100
@@ -851,6 +854,8 @@ module decoder
                 // Bitwise Shifting
                 {7'b011_0000, 3'b001}: instruction_o.op = ariane_pkg::ROLW;     // rolw
                 {7'b011_0000, 3'b101}: instruction_o.op = ariane_pkg::RORW;     // rorw
+                // Pack_W
+                {7'b000_0100, 3'b100}: if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; else illegal_instr_bm = 1'b1;  //packw
                 // Zero Extend Op RV64 encoding
                 {7'b000_0100, 3'b100}:
                 begin
@@ -912,6 +917,8 @@ module decoder
                 end else if (instr.instr[31:26] == 6'b010010) instruction_o.op = ariane_pkg::BCLRI;
                 else if (instr.instr[31:26] == 6'b011010) instruction_o.op = ariane_pkg::BINVI;
                 else if (instr.instr[31:26] == 6'b001010) instruction_o.op = ariane_pkg::BSETI;
+                else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111)
+                  instruction_o.op = ariane_pkg::ZIP;
                 else illegal_instr_bm = 1'b1;
               end
               3'b101: begin
@@ -922,6 +929,10 @@ module decoder
                   instruction_o.op = ariane_pkg::REV8;
                 else if (instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI;
                 else if (instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI;
+                else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b011010000111)
+                  instruction_o.op = ariane_pkg::BREV8;
+                else if (CVA6Cfg.ZKN && instr.instr[31:20] == 12'b000010001111)
+                  instruction_o.op = ariane_pkg::UNZIP;
                 else illegal_instr_bm = 1'b1;
               end
               default: illegal_instr_bm = 1'b1;
diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
index e729929d3e..9e2e0aa80c 100644
--- a/core/include/ariane_pkg.sv
+++ b/core/include/ariane_pkg.sv
@@ -489,7 +489,16 @@ package ariane_pkg;
     ACCEL_OP_STORE,
     // Zicond instruction
     CZERO_EQZ,
-    CZERO_NEZ
+    CZERO_NEZ,
+    // Pack instructions
+    PACK,
+    PACK_H,
+    PACK_W,
+    // Brev8 instruction
+    BREV8,
+    // Zip instructions
+    UNZIP,
+    ZIP
   } fu_op;
 
   function automatic logic op_is_branch(input fu_op op);
diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv
index 95260fc0f6..5c42e5f305 100644
--- a/core/include/build_config_pkg.sv
+++ b/core/include/build_config_pkg.sv
@@ -65,6 +65,7 @@ package build_config_pkg;
     cfg.XF8 = CVA6Cfg.XF8;
     cfg.RVA = CVA6Cfg.RVA;
     cfg.RVB = CVA6Cfg.RVB;
+    cfg.ZKN = CVA6Cfg.ZKN;
     cfg.RVV = CVA6Cfg.RVV;
     cfg.RVC = CVA6Cfg.RVC;
     cfg.RVH = CVA6Cfg.RVH;
diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv
index d711d5f262..cd9c2bad96 100644
--- a/core/include/config_pkg.sv
+++ b/core/include/config_pkg.sv
@@ -54,6 +54,8 @@ package config_pkg;
     bit                          RVA;
     // Bit manipulation RISC-V extension
     bit                          RVB;
+    // Scalar Cryptography RISC-V entension
+    bit                          ZKN;
     // Vector RISC-V extension
     bit                          RVV;
     // Compress RISC-V extension
@@ -240,6 +242,7 @@ package config_pkg;
     bit          XF8;
     bit          RVA;
     bit          RVB;
+    bit          ZKN;
     bit          RVV;
     bit          RVC;
     bit          RVH;
diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv
index 9604b24d39..8c3cd7923b 100644
--- a/core/include/cv32a60x_config_pkg.sv
+++ b/core/include/cv32a60x_config_pkg.sv
@@ -39,6 +39,7 @@ package cva6_config_pkg;
       XF8: bit'(0),
       RVA: bit'(0),
       RVB: bit'(1),
+      ZKN: bit'(1),
       RVV: bit'(0),
       RVC: bit'(1),
       RVH: bit'(0),
diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv
index d9d028fa16..562afba8a3 100644
--- a/core/include/cv32a65x_config_pkg.sv
+++ b/core/include/cv32a65x_config_pkg.sv
@@ -39,6 +39,7 @@ package cva6_config_pkg;
       XF8: bit'(0),
       RVA: bit'(0),
       RVB: bit'(1),
+      ZKN: bit'(1),
       RVV: bit'(0),
       RVC: bit'(1),
       RVH: bit'(0),
diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
index ff6a1fcd41..f003c36495 100644
--- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv
+++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
@@ -24,6 +24,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -90,6 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
index be7ff3ee14..6f162f1296 100644
--- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
+++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
index 2687370b26..278c442ef9 100644
--- a/core/include/cv32a6_imac_sv0_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
index 9c2e622947..1b976d4064 100644
--- a/core/include/cv32a6_imac_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv
index 6ad09136e4..7f2f3fbdcc 100644
--- a/core/include/cv32a6_imafc_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
index 0422eef3bf..6a57d10d16 100644
--- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
+++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
@@ -24,6 +24,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigVExtEn = 1;
   localparam CVA6ConfigRVZiCond = 0;
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
index 8050e88f27..de18d570dd 100644
--- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigZknExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
index 36c4397ade..7347db2106 100644
--- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -31,6 +31,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigZknExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
@@ -98,6 +99,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
index 16f329c456..167dd286d9 100644
--- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
index b785da8296..0543244380 100644
--- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
@@ -24,6 +24,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigZknExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
index 6e4d755ea1..64d964f02e 100644
--- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -25,6 +25,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
 
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
index 49bc7693b2..2e9b46077d 100644
--- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
@@ -24,6 +24,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigHExtEn = 1;
   localparam CVA6ConfigRVZiCond = 1;
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
index 2c642f5345..87cb67f9b0 100644
--- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -24,6 +24,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigVExtEn = 1;
   localparam CVA6ConfigRVZiCond = 0;
@@ -91,6 +92,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv
index 8e0b686386..eafcbd27b1 100644
--- a/core/include/cv64a6_mmu_config_pkg.sv
+++ b/core/include/cv64a6_mmu_config_pkg.sv
@@ -12,6 +12,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigXlen = 64;
 
   localparam CVA6ConfigBExtEn = 1;  // UVM
+  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigRvfiTrace = 1;
 
   localparam CVA6ConfigAxiIdWidth = 4;  // axi_pkg.sv
@@ -46,6 +47,7 @@ package cva6_config_pkg;
       XF8: bit'(0),
       RVA: bit'(0),
       RVB: bit'(CVA6ConfigBExtEn),
+      ZKN: bit'(CVA6ConfigZknExtEn),
       RVV: bit'(0),
       RVC: bit'(1),
       RVH: bit'(0),
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
index d40ab0f114..12262eb666 100644
--- a/verif/sim/cva6.py
+++ b/verif/sim/cva6.py
@@ -879,14 +879,14 @@ def load_config(args, cwd):
       args.isa  = "rv64gch_zba_zbb_zbs_zbc"
     elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
       args.mabi = "lp64d"
-      args.isa  = "rv64gc_zba_zbb_zbs_zbc"
+      args.isa  = "rv64gc_zba_zbb_zbs_zbc_zbkb"
     elif base == "cv32a60x":
       args.mabi = "ilp32"
-      args.isa  = "rv32imc_zba_zbb_zbs_zbc"
+      args.isa  = "rv32imc_zba_zbb_zbs_zbc_zbkb"
       args.priv  = "m"
     elif base == "cv32a65x":
       args.mabi = "ilp32"
-      args.isa  = "rv32imc_zba_zbb_zbs_zbc"
+      args.isa  = "rv32imc_zba_zbb_zbs_zbc_zbkb"
       args.priv  = "m"
     elif base == "cv64a6_mmu":
       args.mabi = "lp64"

From 44ec340eaabf42f03b89b17f69d50be832df12de Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 3 Dec 2024 12:41:56 +0500
Subject: [PATCH 02/13] checking tests

---
 core/alu.sv | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/core/alu.sv b/core/alu.sv
index 65ae4e8c11..8faf01da93 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -276,15 +276,16 @@ module alu
 
   // ZKN Instructions
   if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_block
+    genvar i, m, n;
     // Generate brev8_reversed by reversing bits within each byte
-    for (int i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen
-      for (int m = 0; m < 8; m++) begin : reverse_bits
+    for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen
+      for (m = 0; m < 8; m++) begin : reverse_bits
         // Reversing the order of bits within a single byte
         assign brev8_reversed[(i<<3)+m] = fu_data_i.operand_a[(i<<3)+(7-m)];
       end
     end
     // Generate zip and unzip results
-    for (int n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
+    for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
       // Assigning lower and upper half of operand into the even and odd positions of result
       assign zip_gen_even[n<<1] = fu_data_i.operand_a[n];
       assign zip_gen_odd[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2];

From 8683e109549fb97ae1f4c7edb5a1a99123dfa00a Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 3 Dec 2024 17:30:04 +0500
Subject: [PATCH 03/13] changed alu logic and added tests to yaml files

---
 core/alu.sv                                   | 34 +++++--------------
 .../testlist_riscv-arch-test-cv32a60x.yaml    | 25 ++++++++++++++
 .../testlist_riscv-arch-test-cv32a65x.yaml    | 25 ++++++++++++++
 ...st_riscv-arch-test-cv64a6_imafdc_sv39.yaml | 20 +++++++++++
 4 files changed, 79 insertions(+), 25 deletions(-)

diff --git a/core/alu.sv b/core/alu.sv
index 8faf01da93..4c2e7ebdf9 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -51,17 +51,11 @@ module alu
   logic lz_tz_empty, lz_tz_wempty;
   logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
 
-  logic [CVA6Cfg.XLEN-1:0] pack_result;
-  logic [            31:0] packh_result;
-  logic [            63:0] packw_result;
   logic [CVA6Cfg.XLEN-1:0] brev8_reversed;
-  logic [CVA6Cfg.XLEN-1:0] brev8_result;
   logic [            15:0] unzip_gen_hi;
   logic [            15:0] unzip_gen_lo;
-  logic [            31:0] unzip_result;
   logic [            31:0] zip_gen_even;
   logic [            31:0] zip_gen_odd;
-  logic [            31:0] zip_result;
   // bit reverse operand_a for left shifts and bit counting
   generate
     genvar k;
@@ -274,8 +268,8 @@ module alu
     end
   end
 
-  // ZKN Instructions
-  if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_block
+  // ZKN gen block
+  if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin : zkn_gen_block
     genvar i, m, n;
     // Generate brev8_reversed by reversing bits within each byte
     for (i = 0; i < (CVA6Cfg.XLEN / 8); i++) begin : brev8_gen
@@ -293,17 +287,6 @@ module alu
       assign unzip_gen_lo[n] = fu_data_i.operand_a[n<<1];
       assign unzip_gen_hi[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1];
     end
-    if (CVA6Cfg.IS_XLEN32) begin
-      assign pack_result = {{fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};  // 32-bit pack
-      assign packh_result = {16'b0, {fu_data_i.operand_b[7:0]}, {fu_data_i.operand_a[7:0]}};  // zero extended pack_h
-      assign brev8_result = brev8_reversed;  // 32-bit brev8
-      assign unzip_result = {{unzip_gen_hi}, {unzip_gen_lo}};  // 32-bit unzip
-      assign zip_result = {zip_gen_even} | {zip_gen_odd};  // 32-bit zip
-    end else begin
-      assign pack_result = {{fu_data_i.operand_b[31:0]}, {fu_data_i.operand_a[31:0]}};  // 64-bit pack
-      assign packw_result = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};  // sign extended pack_w
-      assign brev8_result = brev8_reversed;  // 64-bit brev8
-    end
   end
 
   // -----------
@@ -401,15 +384,16 @@ module alu
         default: ;  // default case to suppress unique warning
       endcase
     end
+    // ZKN instructions
     if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
       unique case (fu_data_i.operation)
-        PACK: result_o = pack_result;
-        PACK_H: result_o = packh_result;
-        BREV8: result_o = brev8_result;
-        UNZIP: result_o = unzip_result;
-        ZIP: result_o = zip_result;
+        PACK: result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
+        PACK_H: result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
+        BREV8: result_o = brev8_reversed;
+        UNZIP: result_o = {{unzip_gen_hi}, {unzip_gen_lo}};
+        ZIP: result_o = {zip_gen_even} | {zip_gen_odd};
       endcase
-      if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = packw_result;
+      if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};
     end
   end
 endmodule
diff --git a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml
index 94dc5f7941..a7d30004ae 100644
--- a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml
@@ -608,3 +608,28 @@ testlist:
     <<: *common_test_config
     iterations: 1
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S
+
+  - test: rv32im-pack-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S
+
+  - test: rv32im-packh-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S
+
+  - test: rv32im-brev8_32-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S
+
+  - test: rv32im-unzip-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S
+
+  - test: rv32im-zip-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S
\ No newline at end of file
diff --git a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml
index 21e2b91430..9462abe4d2 100644
--- a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml
@@ -562,3 +562,28 @@ testlist:
     iterations: 1
     <<: *common_test_config
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S
+
+  - test: rv32im-pack-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S
+
+  - test: rv32im-packh-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S
+
+  - test: rv32im-brev8_32-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S
+
+  - test: rv32im-unzip-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S
+
+  - test: rv32im-zip-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S
\ No newline at end of file
diff --git a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
index 6aa4701e64..159697ae13 100644
--- a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
@@ -967,3 +967,23 @@ testlist:
     iterations: 1
     <<: *common_test_config
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
+
+  - test: rv64im-pack-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/pack-01.S
+
+  - test: rv64im-packh-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/packh-01.S
+
+  - test: rv64im-packw-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/packw-01.S
+
+  - test: rv64im-brev8-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/brev8-01.S
\ No newline at end of file

From 818ac27630672746eeeb5cb39eb22d2e2c32dddb Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Thu, 5 Dec 2024 15:10:20 +0500
Subject: [PATCH 04/13] documentation

---
 .../cv32a65x/isa/isa.adoc                     |  13 ++
 .../cv32a65x/isa/isa.rst                      |  21 +++
 core/alu.sv                                   |  27 +--
 .../RISCV_Instructions_RVZbkb.rst             | 169 ++++++++++++++++++
 4 files changed, 217 insertions(+), 13 deletions(-)
 create mode 100644 docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst

diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
index c187bcbbb6..ec9951a720 100644
--- a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
+++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
@@ -22,6 +22,7 @@
 |Zbc | RVZbc Carry-less multiplication | Carry-less multiplication is the multiplication in the polynomial ring over GF(2).clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2✕XLEN carry-less product.clmulr produces bits 2✕XLEN−2:XLEN-1 of the 2✕XLEN carry-less product.
 |Zbs | RVZbs Single bit Instructions | The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index.
 |Zicntr | Zicntr | No info found yet for extension Zicntr
+|Zbkb | RVZbkb Bitmanip instructions for Cryptography | The Zbkb extension is a part of the RISC-V Bit-Manipulation (bitmanip) extensions, specifically targeting cryptographic applications. It introduces a set of instructions designed to facilitate operations commonly used in cryptographic algorithms, such as interleaving, packing, and reordering of bits.
 |===
 
 ==== RV32I Base Integer Instructions
@@ -221,3 +222,15 @@
 | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations 
 |===
 
+==== RVZbkb Bitmanip instructions for Cryptography
+
+|===
+| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name
+
+| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions 
+| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions 
+| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions 
+| ZIP | zip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions 
+| UNZIP | unzip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions 
+| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse
+|===
diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
index 2d02548c4e..864f3b49ff 100644
--- a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
+++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
@@ -47,6 +47,8 @@ Instructions
 +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 | Zicntr        | Zicntr_                                             | No info found yet for extension Zicntr                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               |
 +---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+| Zbkb          | RVZbkb Bitmanip instructions for Cryptography_      | The Zbkb extension is a part of the RISC-V Bit-Manipulation (bitmanip) extensions, specifically targeting cryptographic applications. It introduces a set of instructions designed to facilitate operations commonly used in cryptographic algorithms, such as interleaving, packing, and reordering of bits.                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        |
++---------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
 
 RV32I Base Integer Instructions
 -------------------------------
@@ -394,3 +396,22 @@ RVZbs Single bit Instructions
 | BSETI  | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1)))   | NONE             | NONE               | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.      | Single_bit_Operations |
 +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
 
+RVZbkb Bitmanip instructions for Cryptography
+-------------------------------------
+
+
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
+| Name      | Format                 | Pseudocode                                                                                          | Invalid_values   | Exception_raised   | Description                                                                                                                                                                                                                                                     | Op Name                 |
++===========+========================+==========================================+==================+====================+===========================================================================================================================================================================================================================+==========================================================================================================================+
+| PACK      | pack rd, rs1, rs2      | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0]                                                   | NONE             | NONE               | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half.                                                                                                                                           | Pack instructions       |
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
+| PACKH     | packh rd, rs1, rs2     | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0])                                                           | NONE             | NONE               | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd.                                                                                                                      | Pack instructions       |
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
+| PACKW     | packw rd, rs1, rs2     | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0])                                                         | NONE             | NONE               | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.                                                                                                             | Pack instructions       |
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
+| ZIP       | zip rd, rs             | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];}    | NONE             | NONE               | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions        |
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
+| UNZIP     | unzip rd, rs           | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];}    | NONE             | NONE               | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.                                              | Zip instructions        |
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
+| BREV8     | brev8 rd, rs           | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE             | NONE               | This instruction reverses the order of the bits in every byte of a register.                                                                                                                                                                                    | Bits-in-Byte-reverse    |
++-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
diff --git a/core/alu.sv b/core/alu.sv
index 4c2e7ebdf9..2cd5de7624 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -52,10 +52,8 @@ module alu
   logic [CVA6Cfg.XLEN-1:0] orcbw_result, rev8w_result;
 
   logic [CVA6Cfg.XLEN-1:0] brev8_reversed;
-  logic [            15:0] unzip_gen_hi;
-  logic [            15:0] unzip_gen_lo;
-  logic [            31:0] zip_gen_even;
-  logic [            31:0] zip_gen_odd;
+  logic [            31:0] unzip_gen;
+  logic [            31:0] zip_gen;
   // bit reverse operand_a for left shifts and bit counting
   generate
     genvar k;
@@ -279,13 +277,15 @@ module alu
       end
     end
     // Generate zip and unzip results
-    for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
-      // Assigning lower and upper half of operand into the even and odd positions of result
-      assign zip_gen_even[n<<1] = fu_data_i.operand_a[n];
-      assign zip_gen_odd[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2];
-      // Assigning even and odd bits of operand into lower and upper halves of result
-      assign unzip_gen_lo[n] = fu_data_i.operand_a[n<<1];
-      assign unzip_gen_hi[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1];
+    if (CVA6Cfg.IS_XLEN32) begin
+      for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
+        // Assigning lower and upper half of operand into the even and odd positions of result
+        assign zip_gen[n<<1] = fu_data_i.operand_a[n];
+        assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2];
+        // Assigning even and odd bits of operand into lower and upper halves of result
+        assign unzip_gen[n] = fu_data_i.operand_a[n<<1];
+        assign unzip_gen[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1];
+      end
     end
   end
 
@@ -390,10 +390,11 @@ module alu
         PACK: result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
         PACK_H: result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
         BREV8: result_o = brev8_reversed;
-        UNZIP: result_o = {{unzip_gen_hi}, {unzip_gen_lo}};
-        ZIP: result_o = {zip_gen_even} | {zip_gen_odd};
+        default: ;
       endcase
       if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};
+      if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
+      if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
     end
   end
 endmodule
diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
new file mode 100644
index 0000000000..77b13f91ef
--- /dev/null
+++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
@@ -0,0 +1,169 @@
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2023 10xEngineers
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+
+.. _cva6_riscv_instructions_RV32Zbkb:
+
+*Applicability of this chapter to configurations:*
+
+.. csv-table::
+   :widths: auto
+   :align: left
+   :header: "Configuration", "Implementation"
+
+   "CV32A60AX", "Implemented extension"
+   "CV32A60X", "Implemented extension"
+   "CV64A6_MMU", "Implemented extension"
+
+=============================
+RVZbkb: Bitmanip instructions for Cryptography
+=============================
+
+The following instructions comprise the Zbkb extension:
+
+Pack instructions
+--------------------
+The Pack instructions can be implemented by packing the lower halves of both source operands into the destination register for pack and packw instructions and by packing the lower bytes of the source operands into the destination register for packh.
+
++-----------+-----------+-----------------------+
+| RV32      | RV64      | Mnemonic              |
++===========+===========+=======================+
+| ✔         | ✔         | pack rd, rs1, rs2     |
++-----------+-----------+-----------------------+
+| ✔         | ✔         | packh rd, rs1, rs2    |
++-----------+-----------+-----------------------+
+|           | ✔         | packw rd, rs1, rs2    |
++-----------+-----------+-----------------------+
+
+RV32 and RV64 Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+- **PACK**: Pack low halves of registers
+
+    **Format**: pack rd, rs1, rs2
+
+    **Description**: This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half.
+
+    **Pseudocode**: X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0];
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **PACKH**: Pack low bytes of registers
+
+    **Format**: packh rd, rs1, rs2 
+
+    **Description**: This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd.
+
+    **Pseudocode**: X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]);
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+RV64 specific instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~	
+
+- **PACKW**: Pack low 16-bits of registers
+
+    **Format**: packw rd, rs1, rs2
+
+    **Description**: This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.
+
+    **Pseudocode**: X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]);
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+
+Zip instructions
+--------------------------------
+These instructions are used to extract bits from the source registers and interleave them into the destination register.
+
++-----------+-----------+-----------------------+
+| RV32      | RV64      | Mnemonic              |
++===========+===========+=======================+
+| ✔         |           | zip rd, rs            |
++-----------+-----------+-----------------------+
+| ✔         |           | unzip rd, rs          |
++-----------+-----------+-----------------------+
+
+RV32 specific Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- **ZIP**: Zip
+
+    **Format**: zip rd, rs 
+
+    **Description**: This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction.
+
+    **Pseudocode**: foreach (i from 0 to xlen/2-1) {
+                        X(rd)[i << 1] = X(rs1)[i]
+                        X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2] 
+                    }
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+- **UNZIP**: Unzip
+
+    **Format**: unzip rd, rs 
+
+    **Description**: This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.
+
+    **Pseudocode**: foreach (i from 0 to xlen/2-1) {
+                        X(rd)[i] = X(rs1)[i << 1]
+                        X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1]
+                    }
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE
+
+
+Bits-in-Byte-reverse
+------------
+brev8 reverses the bits in each byte of the source register.
+
++-----------+-----------+-----------------------+
+| RV32      | RV64      | Mnemonic              |
++===========+===========+=======================+
+| ✔         | ✔         | brev8 rd, rs          |
++-----------+-----------+-----------------------+
+
+RV32 and RV64 Instructions
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- **BREV8**: Reverse bits in bytes
+
+    **Format**:  brev8 rd, rs
+
+    **Description**: This instruction reverses the order of the bits in every byte of a register.
+
+    **Pseudocode**: foreach (i from 0 to xlen by 8) {
+                        foreach (j from 0 to 7) {
+                            X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];
+                        }
+                    }
+
+    **Invalid values**: NONE
+
+    **Exception raised**: NONE

From 64d46f2f8d5e09bffda52d92017611d08b8f6268 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Thu, 5 Dec 2024 15:40:03 +0500
Subject: [PATCH 05/13] minor fixes

---
 config/gen_from_riscv_config/cv32a65x/isa/isa.adoc | 4 ++--
 config/gen_from_riscv_config/cv32a65x/isa/isa.rst  | 4 ++--
 core/alu.sv                                        | 6 +++---
 docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst    | 8 ++++----
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
index ec9951a720..a3c37d8035 100644
--- a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
+++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
@@ -230,7 +230,7 @@
 | PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions 
 | PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions 
 | PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions 
-| ZIP | zip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions 
-| UNZIP | unzip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions 
+| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions 
+| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions 
 | BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse
 |===
diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
index 864f3b49ff..5af067961b 100644
--- a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
+++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
@@ -409,9 +409,9 @@ RVZbkb Bitmanip instructions for Cryptography
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
 | PACKW     | packw rd, rs1, rs2     | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0])                                                         | NONE             | NONE               | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.                                                                                                             | Pack instructions       |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| ZIP       | zip rd, rs             | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];}    | NONE             | NONE               | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions        |
+| ZIP       | zip rd, rs             | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];}              | NONE             | NONE               | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions        |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| UNZIP     | unzip rd, rs           | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];}    | NONE             | NONE               | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.                                              | Zip instructions        |
+| UNZIP     | unzip rd, rs           | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];}              | NONE             | NONE               | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.                                              | Zip instructions        |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
 | BREV8     | brev8 rd, rs           | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE             | NONE               | This instruction reverses the order of the bits in every byte of a register.                                                                                                                                                                                    | Bits-in-Byte-reverse    |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
diff --git a/core/alu.sv b/core/alu.sv
index 2cd5de7624..6184534de8 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -278,13 +278,13 @@ module alu
     end
     // Generate zip and unzip results
     if (CVA6Cfg.IS_XLEN32) begin
-      for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
+      for (n = 0; n < 16; n++) begin : zip_unzip_gen
         // Assigning lower and upper half of operand into the even and odd positions of result
         assign zip_gen[n<<1] = fu_data_i.operand_a[n];
-        assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2];
+        assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+16];
         // Assigning even and odd bits of operand into lower and upper halves of result
         assign unzip_gen[n] = fu_data_i.operand_a[n<<1];
-        assign unzip_gen[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1];
+        assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1];
       end
     end
   end
diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
index 77b13f91ef..83408ff800 100644
--- a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
+++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
@@ -114,9 +114,9 @@ RV32 specific Instructions
 
     **Description**: This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction.
 
-    **Pseudocode**: foreach (i from 0 to xlen/2-1) {
+    **Pseudocode**: foreach (i from 0 to 15) {
                         X(rd)[i << 1] = X(rs1)[i]
-                        X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2] 
+                        X(rd)[i+1 << 1] = X(rs1)[i+16] 
                     }
 
     **Invalid values**: NONE
@@ -129,9 +129,9 @@ RV32 specific Instructions
 
     **Description**: This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.
 
-    **Pseudocode**: foreach (i from 0 to xlen/2-1) {
+    **Pseudocode**: foreach (i from 0 to 15) {
                         X(rd)[i] = X(rs1)[i << 1]
-                        X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1]
+                        X(rd)[i+16] = X(rs1)[i+1 << 1]
                     }
 
     **Invalid values**: NONE

From ea60efd2adc24e6201bc8ee10434da1c8908c149 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Mon, 9 Dec 2024 11:40:20 +0500
Subject: [PATCH 06/13] suggested format and config changes

---
 .../cv32a65x/isa/isa.adoc                     | 13 ----------
 .../cv32a65x/isa/isa.rst                      | 20 ---------------
 core/alu.sv                                   | 11 +++++---
 core/decoder.sv                               | 22 ++++++++++++----
 core/include/cv32a60x_config_pkg.sv           |  2 +-
 core/include/cv32a65x_config_pkg.sv           |  2 +-
 .../cv32a6_embedded_config_pkg_deprecated.sv  |  3 +--
 .../cv32a6_ima_sv32_fpga_config_pkg.sv        |  3 +--
 core/include/cv32a6_imac_sv0_config_pkg.sv    |  3 +--
 core/include/cv32a6_imac_sv32_config_pkg.sv   |  3 +--
 core/include/cv32a6_imafc_sv32_config_pkg.sv  |  3 +--
 .../cv64a6_imadfcv_sv39_polara_config_pkg.sv  |  3 +--
 core/include/cv64a6_imafdc_sv39_config_pkg.sv |  3 +--
 .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv |  3 +--
 ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv |  3 +--
 .../cv64a6_imafdc_sv39_wb_config_pkg.sv       |  3 +--
 .../include/cv64a6_imafdch_sv39_config_pkg.sv |  3 +--
 .../cv64a6_imafdch_sv39_wb_config_pkg.sv      |  3 +--
 .../include/cv64a6_imafdcv_sv39_config_pkg.sv |  3 +--
 core/include/cv64a6_mmu_config_pkg.sv         |  3 +--
 .../RISCV_Instructions_RVZbkb.rst             |  1 -
 .../testlist_riscv-arch-test-cv32a60x.yaml    | 25 -------------------
 .../testlist_riscv-arch-test-cv32a65x.yaml    | 25 -------------------
 23 files changed, 41 insertions(+), 122 deletions(-)

diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
index a3c37d8035..f7c8f5aeea 100644
--- a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
+++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
@@ -221,16 +221,3 @@
 | BSET | bset rd, rs1, rs2 | X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations 
 | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations 
 |===
-
-==== RVZbkb Bitmanip instructions for Cryptography
-
-|===
-| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name
-
-| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions 
-| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions 
-| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions 
-| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions 
-| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions 
-| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse
-|===
diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
index 5af067961b..f7fa06620c 100644
--- a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
+++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
@@ -395,23 +395,3 @@ RVZbs Single bit Instructions
 +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
 | BSETI  | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1)))   | NONE             | NONE               | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved.      | Single_bit_Operations |
 +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+
-
-RVZbkb Bitmanip instructions for Cryptography
--------------------------------------
-
-
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| Name      | Format                 | Pseudocode                                                                                          | Invalid_values   | Exception_raised   | Description                                                                                                                                                                                                                                                     | Op Name                 |
-+===========+========================+==========================================+==================+====================+===========================================================================================================================================================================================================================+==========================================================================================================================+
-| PACK      | pack rd, rs1, rs2      | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0]                                                   | NONE             | NONE               | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half.                                                                                                                                           | Pack instructions       |
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| PACKH     | packh rd, rs1, rs2     | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0])                                                           | NONE             | NONE               | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd.                                                                                                                      | Pack instructions       |
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| PACKW     | packw rd, rs1, rs2     | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0])                                                         | NONE             | NONE               | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.                                                                                                             | Pack instructions       |
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| ZIP       | zip rd, rs             | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];}              | NONE             | NONE               | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions        |
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| UNZIP     | unzip rd, rs           | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];}              | NONE             | NONE               | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.                                              | Zip instructions        |
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| BREV8     | brev8 rd, rs           | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE             | NONE               | This instruction reverses the order of the bits in every byte of a register.                                                                                                                                                                                    | Bits-in-Byte-reverse    |
-+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
diff --git a/core/alu.sv b/core/alu.sv
index 6184534de8..ce62bc7b5b 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -387,12 +387,17 @@ module alu
     // ZKN instructions
     if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
       unique case (fu_data_i.operation)
-        PACK: result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
-        PACK_H: result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
+        PACK:
+        result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]});
+        PACK_H:
+        result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]});
         BREV8: result_o = brev8_reversed;
         default: ;
       endcase
-      if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}};
+      if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64)
+       result_o = {
+        {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
+        };
       if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
       if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
     end
diff --git a/core/decoder.sv b/core/decoder.sv
index 2154299774..cd8900840f 100644
--- a/core/decoder.sv
+++ b/core/decoder.sv
@@ -777,8 +777,16 @@ module decoder
                 {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL;  // rol
                 {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR;  // ror
                 // Packing
-                {7'b000_0100, 3'b100} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; else illegal_instr_bm = 1'b1;  //pack
-                {7'b000_0100, 3'b111} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; else illegal_instr_bm = 1'b1;  //packh
+                {
+                  7'b000_0100, 3'b100
+                } : 
+                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK;
+                else illegal_instr_bm = 1'b1;  //pack
+                {
+                  7'b000_0100, 3'b111
+                } : 
+                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; 
+                else illegal_instr_bm = 1'b1;  //packh
                 // Zero Extend Op RV32 encoding
                 {
                   7'b000_0100, 3'b100
@@ -852,10 +860,14 @@ module decoder
                 // Unsigned word Op's
                 {7'b000_0100, 3'b000}: instruction_o.op = ariane_pkg::ADDUW;    // add.uw
                 // Bitwise Shifting
-                {7'b011_0000, 3'b001}: instruction_o.op = ariane_pkg::ROLW;     // rolw
-                {7'b011_0000, 3'b101}: instruction_o.op = ariane_pkg::RORW;     // rorw
+                {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW;  // rolw
+                {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW;  // rorw
                 // Pack_W
-                {7'b000_0100, 3'b100}: if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; else illegal_instr_bm = 1'b1;  //packw
+                {
+                  7'b000_0100, 3'b100
+                } : 
+                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; 
+                else illegal_instr_bm = 1'b1;  //packw
                 // Zero Extend Op RV64 encoding
                 {7'b000_0100, 3'b100}:
                 begin
diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv
index 8c3cd7923b..f3f0a3982c 100644
--- a/core/include/cv32a60x_config_pkg.sv
+++ b/core/include/cv32a60x_config_pkg.sv
@@ -39,7 +39,7 @@ package cva6_config_pkg;
       XF8: bit'(0),
       RVA: bit'(0),
       RVB: bit'(1),
-      ZKN: bit'(1),
+      ZKN: bit'(0),
       RVV: bit'(0),
       RVC: bit'(1),
       RVH: bit'(0),
diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv
index 562afba8a3..788ae83e9b 100644
--- a/core/include/cv32a65x_config_pkg.sv
+++ b/core/include/cv32a65x_config_pkg.sv
@@ -39,7 +39,7 @@ package cva6_config_pkg;
       XF8: bit'(0),
       RVA: bit'(0),
       RVB: bit'(1),
-      ZKN: bit'(1),
+      ZKN: bit'(0),
       RVV: bit'(0),
       RVC: bit'(1),
       RVH: bit'(0),
diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
index f003c36495..9168be9ed6 100644
--- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv
+++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv
@@ -24,7 +24,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 1;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,7 +90,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
index 6f162f1296..4efbdfdf52 100644
--- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
+++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv
index 278c442ef9..9d5edd3653 100644
--- a/core/include/cv32a6_imac_sv0_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv0_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
index 1b976d4064..060fee513f 100644
--- a/core/include/cv32a6_imac_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv
index 7f2f3fbdcc..c29dd93f60 100644
--- a/core/include/cv32a6_imafc_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
index 6a57d10d16..26d5819862 100644
--- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
+++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
@@ -24,7 +24,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigVExtEn = 1;
   localparam CVA6ConfigRVZiCond = 0;
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
index de18d570dd..c7a6cc5f85 100644
--- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 1;
-  localparam CVA6ConfigZknExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
index 7347db2106..8be842fa27 100644
--- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -31,7 +31,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
-  localparam CVA6ConfigZknExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
@@ -99,7 +98,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
index 167dd286d9..e36dffbdb2 100644
--- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
index 0543244380..8acc084ee2 100644
--- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
@@ -24,7 +24,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
-  localparam CVA6ConfigZknExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
index 64d964f02e..5cce0a9ec1 100644
--- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv
@@ -25,7 +25,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 1;
 
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
index 2e9b46077d..2705c7583b 100644
--- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
@@ -24,7 +24,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 1;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigHExtEn = 1;
   localparam CVA6ConfigRVZiCond = 1;
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
index 87cb67f9b0..c7a36e6d9b 100644
--- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
+++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv
@@ -24,7 +24,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigBExtEn = 0;
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigVExtEn = 1;
   localparam CVA6ConfigRVZiCond = 0;
@@ -92,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv
index eafcbd27b1..3d902c4240 100644
--- a/core/include/cv64a6_mmu_config_pkg.sv
+++ b/core/include/cv64a6_mmu_config_pkg.sv
@@ -12,7 +12,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigXlen = 64;
 
   localparam CVA6ConfigBExtEn = 1;  // UVM
-  localparam CVA6ConfigZknExtEn = 0;
   localparam CVA6ConfigRvfiTrace = 1;
 
   localparam CVA6ConfigAxiIdWidth = 4;  // axi_pkg.sv
@@ -47,7 +46,7 @@ package cva6_config_pkg;
       XF8: bit'(0),
       RVA: bit'(0),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(CVA6ConfigZknExtEn),
+      ZKN: bit'(0),
       RVV: bit'(0),
       RVC: bit'(1),
       RVH: bit'(0),
diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
index 83408ff800..149bbee44a 100644
--- a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
+++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
@@ -26,7 +26,6 @@
    :header: "Configuration", "Implementation"
 
    "CV32A60AX", "Implemented extension"
-   "CV32A60X", "Implemented extension"
    "CV64A6_MMU", "Implemented extension"
 
 =============================
diff --git a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml
index a7d30004ae..94dc5f7941 100644
--- a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml
@@ -608,28 +608,3 @@ testlist:
     <<: *common_test_config
     iterations: 1
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S
-
-  - test: rv32im-pack-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S
-
-  - test: rv32im-packh-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S
-
-  - test: rv32im-brev8_32-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S
-
-  - test: rv32im-unzip-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S
-
-  - test: rv32im-zip-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S
\ No newline at end of file
diff --git a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml
index 9462abe4d2..21e2b91430 100644
--- a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml
@@ -562,28 +562,3 @@ testlist:
     iterations: 1
     <<: *common_test_config
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S
-
-  - test: rv32im-pack-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S
-
-  - test: rv32im-packh-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S
-
-  - test: rv32im-brev8_32-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S
-
-  - test: rv32im-unzip-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S
-
-  - test: rv32im-zip-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S
\ No newline at end of file

From d6590d2ea6d3471a0418a3006177a3a4dac85aa0 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 10 Dec 2024 14:30:46 +0500
Subject: [PATCH 07/13] zbkb enabled only in 2 configs

---
 core/alu.sv                                   |  4 +--
 core/decoder.sv                               | 29 +++++++++----------
 .../cv32a6_ima_sv32_fpga_config_pkg.sv        |  2 +-
 core/include/cv32a6_imac_sv32_config_pkg.sv   |  4 +--
 .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv |  2 +-
 .../cv64a6_imafdc_sv39_wb_config_pkg.sv       |  2 +-
 verif/sim/cva6.py                             | 11 ++++---
 7 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/core/alu.sv b/core/alu.sv
index ce62bc7b5b..9f69f6ef93 100644
--- a/core/alu.sv
+++ b/core/alu.sv
@@ -395,8 +395,8 @@ module alu
         default: ;
       endcase
       if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64)
-       result_o = {
-        {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
+        result_o = {
+          {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}
         };
       if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen;
       if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen;
diff --git a/core/decoder.sv b/core/decoder.sv
index cd8900840f..615e491df3 100644
--- a/core/decoder.sv
+++ b/core/decoder.sv
@@ -779,13 +779,13 @@ module decoder
                 // Packing
                 {
                   7'b000_0100, 3'b100
-                } : 
+                } :
                 if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK;
                 else illegal_instr_bm = 1'b1;  //pack
                 {
                   7'b000_0100, 3'b111
-                } : 
-                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; 
+                } :
+                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H;
                 else illegal_instr_bm = 1'b1;  //packh
                 // Zero Extend Op RV32 encoding
                 {
@@ -854,27 +854,26 @@ module decoder
                 instr.rtype.funct7, instr.rtype.funct3
               })
                 // Shift with Add (Unsigned Word)
-                {7'b001_0000, 3'b010}: instruction_o.op = ariane_pkg::SH1ADDUW; // sh1add.uw
-                {7'b001_0000, 3'b100}: instruction_o.op = ariane_pkg::SH2ADDUW; // sh2add.uw
-                {7'b001_0000, 3'b110}: instruction_o.op = ariane_pkg::SH3ADDUW; // sh3add.uw
+                {7'b001_0000, 3'b010} : instruction_o.op = ariane_pkg::SH1ADDUW;  // sh1add.uw
+                {7'b001_0000, 3'b100} : instruction_o.op = ariane_pkg::SH2ADDUW;  // sh2add.uw
+                {7'b001_0000, 3'b110} : instruction_o.op = ariane_pkg::SH3ADDUW;  // sh3add.uw
                 // Unsigned word Op's
-                {7'b000_0100, 3'b000}: instruction_o.op = ariane_pkg::ADDUW;    // add.uw
+                {7'b000_0100, 3'b000} : instruction_o.op = ariane_pkg::ADDUW;  // add.uw
                 // Bitwise Shifting
                 {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW;  // rolw
                 {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW;  // rorw
                 // Pack_W
                 {
                   7'b000_0100, 3'b100
-                } : 
-                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; 
+                } :
+                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;
                 else illegal_instr_bm = 1'b1;  //packw
                 // Zero Extend Op RV64 encoding
-                {7'b000_0100, 3'b100}:
-                begin
-                  if (instr.instr[24:20] == 5'b00000)
-                    instruction_o.op = ariane_pkg::ZEXTH;
-                  else
-                    illegal_instr_bm = 1'b1;
+                {
+                  7'b000_0100, 3'b100
+                } : begin
+                  if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH;
+                  else illegal_instr_bm = 1'b1;
                 end
                 default: illegal_instr_bm = 1'b1;
               endcase
diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
index 4efbdfdf52..b65b0a0add 100644
--- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
+++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
@@ -91,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(1),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
index 060fee513f..09d9d24a09 100644
--- a/core/include/cv32a6_imac_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -24,7 +24,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
-  localparam CVA6ConfigBExtEn = 0;
+  localparam CVA6ConfigBExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -91,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(0),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
index 8be842fa27..24d50ba0c5 100644
--- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -98,7 +98,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(1),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
index 8acc084ee2..6f46e4127c 100644
--- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
@@ -91,7 +91,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(1),
+      ZKN: bit'(0),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
index 12262eb666..42499dd1bd 100644
--- a/verif/sim/cva6.py
+++ b/verif/sim/cva6.py
@@ -877,16 +877,19 @@ def load_config(args, cwd):
     if base in ("cv64a6_imafdch_sv39", "cv64a6_imafdch_sv39_wb"):
       args.mabi = "lp64d"
       args.isa  = "rv64gch_zba_zbb_zbs_zbc"
-    elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
+    elif base in ("cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
+      args.mabi = "lp64d"
+      args.isa  = "rv64gc_zba_zbb_zbs_zbc"
+    elif base in ("cv64a6_imafdc_sv39"):
       args.mabi = "lp64d"
       args.isa  = "rv64gc_zba_zbb_zbs_zbc_zbkb"
     elif base == "cv32a60x":
       args.mabi = "ilp32"
-      args.isa  = "rv32imc_zba_zbb_zbs_zbc_zbkb"
+      args.isa  = "rv32imc_zba_zbb_zbs_zbc"
       args.priv  = "m"
     elif base == "cv32a65x":
       args.mabi = "ilp32"
-      args.isa  = "rv32imc_zba_zbb_zbs_zbc_zbkb"
+      args.isa  = "rv32imc_zba_zbb_zbs_zbc"
       args.priv  = "m"
     elif base == "cv64a6_mmu":
       args.mabi = "lp64"
@@ -896,7 +899,7 @@ def load_config(args, cwd):
       args.isa  = "rv32imac"
     elif base == "cv32a6_imac_sv32":
       args.mabi = "ilp32"
-      args.isa  = "rv32imac"
+      args.isa  = "rv32imac_zbkb"
     elif base == "cv32a6_imafc_sv32":
       args.mabi = "ilp32f"
       args.isa  = "rv32imafc"

From c41ca7dc1684b42b0be1138e14b908f40c970973 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 10 Dec 2024 15:47:57 +0500
Subject: [PATCH 08/13] decoder issue fix

---
 core/decoder.sv | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/core/decoder.sv b/core/decoder.sv
index 615e491df3..efe8fa2a1f 100644
--- a/core/decoder.sv
+++ b/core/decoder.sv
@@ -862,17 +862,11 @@ module decoder
                 // Bitwise Shifting
                 {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW;  // rolw
                 {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW;  // rorw
-                // Pack_W
-                {
-                  7'b000_0100, 3'b100
-                } :
-                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;
-                else illegal_instr_bm = 1'b1;  //packw
-                // Zero Extend Op RV64 encoding
                 {
                   7'b000_0100, 3'b100
                 } : begin
-                  if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH;
+                  if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH;  // Zero Extend Op RV64 encoding
+                  else if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;  // packw
                   else illegal_instr_bm = 1'b1;
                 end
                 default: illegal_instr_bm = 1'b1;

From 775cdbe5e84188fc0d667deebc9684bc99964ff9 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 10 Dec 2024 16:27:26 +0500
Subject: [PATCH 09/13] test fixes

---
 core/decoder.sv | 19 ++++++++-----------
 1 file changed, 8 insertions(+), 11 deletions(-)

diff --git a/core/decoder.sv b/core/decoder.sv
index efe8fa2a1f..2d137648f0 100644
--- a/core/decoder.sv
+++ b/core/decoder.sv
@@ -776,23 +776,19 @@ module decoder
                 // Bitwise Shifting
                 {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL;  // rol
                 {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR;  // ror
-                // Packing
-                {
-                  7'b000_0100, 3'b100
-                } :
-                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK;
-                else illegal_instr_bm = 1'b1;  //pack
                 {
                   7'b000_0100, 3'b111
-                } :
-                if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H;
-                else illegal_instr_bm = 1'b1;  //packh
+                } : begin
+                  if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H;  //packh
+                  else illegal_instr_bm = 1'b1;
+                end
                 // Zero Extend Op RV32 encoding
                 {
                   7'b000_0100, 3'b100
                 } : begin
                   if (!CVA6Cfg.IS_XLEN64 && instr.instr[24:20] == 5'b00000)
-                    instruction_o.op = ariane_pkg::ZEXTH;
+                    instruction_o.op = ariane_pkg::ZEXTH;  // Zero Extend Op RV32 encoding
+                  else if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK;  // pack
                   else illegal_instr_bm = 1'b1;
                 end
                 default: begin
@@ -865,7 +861,8 @@ module decoder
                 {
                   7'b000_0100, 3'b100
                 } : begin
-                  if (instr.instr[24:20] == 5'b00000) instruction_o.op = ariane_pkg::ZEXTH;  // Zero Extend Op RV64 encoding
+                  if (instr.instr[24:20] == 5'b00000)
+                    instruction_o.op = ariane_pkg::ZEXTH;  // Zero Extend Op RV64 encoding
                   else if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W;  // packw
                   else illegal_instr_bm = 1'b1;
                 end

From 7bb15a7208f8257e35c97d5ab07ab474749c5a06 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Tue, 10 Dec 2024 21:30:53 +0500
Subject: [PATCH 10/13] removing tests from .yaml

---
 ...st_riscv-arch-test-cv64a6_imafdc_sv39.yaml | 20 -------------------
 1 file changed, 20 deletions(-)

diff --git a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
index 159697ae13..6aa4701e64 100644
--- a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
@@ -967,23 +967,3 @@ testlist:
     iterations: 1
     <<: *common_test_config
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
-
-  - test: rv64im-pack-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/pack-01.S
-
-  - test: rv64im-packh-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/packh-01.S
-
-  - test: rv64im-packw-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/packw-01.S
-
-  - test: rv64im-brev8-01
-    <<: *common_test_config
-    iterations: 1
-    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/brev8-01.S
\ No newline at end of file

From 747329e326b63c8bd44f8016894a57bbc60a29b7 Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Thu, 12 Dec 2024 12:20:10 +0500
Subject: [PATCH 11/13] adding tests for zbkb

---
 core/include/cv32a6_imac_sv32_config_pkg.sv   |  3 +--
 verif/sim/cva6.py                             |  4 ++--
 ...st_riscv-arch-test-cv64a6_imafdc_sv39.yaml | 20 +++++++++++++++++++
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv
index 09d9d24a09..f10df730ef 100644
--- a/core/include/cv32a6_imac_sv32_config_pkg.sv
+++ b/core/include/cv32a6_imac_sv32_config_pkg.sv
@@ -24,7 +24,6 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 1;
   localparam CVA6ConfigHExtEn = 0;  // always disabled
-  localparam CVA6ConfigBExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigRVZiCond = 0;
 
@@ -90,7 +89,7 @@ package cva6_config_pkg;
       XF16ALT: bit'(CVA6ConfigF16AltEn),
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
-      RVB: bit'(CVA6ConfigBExtEn),
+      RVB: bit'(1),
       ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
index 42499dd1bd..a2a37654f2 100644
--- a/verif/sim/cva6.py
+++ b/verif/sim/cva6.py
@@ -877,10 +877,10 @@ def load_config(args, cwd):
     if base in ("cv64a6_imafdch_sv39", "cv64a6_imafdch_sv39_wb"):
       args.mabi = "lp64d"
       args.isa  = "rv64gch_zba_zbb_zbs_zbc"
-    elif base in ("cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"):
+    elif base in ("cv64a6_imafdc_sv39_wb"):
       args.mabi = "lp64d"
       args.isa  = "rv64gc_zba_zbb_zbs_zbc"
-    elif base in ("cv64a6_imafdc_sv39"):
+    elif base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache"):
       args.mabi = "lp64d"
       args.isa  = "rv64gc_zba_zbb_zbs_zbc_zbkb"
     elif base == "cv32a60x":
diff --git a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
index 6aa4701e64..1550d1f22c 100644
--- a/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
+++ b/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml
@@ -967,3 +967,23 @@ testlist:
     iterations: 1
     <<: *common_test_config
     asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/A/src/amoxor.w-01.S
+
+  - test: rv64im-pack-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/pack-01.S
+
+  - test: rv64im-packh-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/packh-01.S
+
+  - test: rv64im-packw-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/packw-01.S
+
+  - test: rv64im-brev8-01
+    <<: *common_test_config
+    iterations: 1
+    asm_tests: <path_var>/riscv-arch-test/riscv-test-suite/rv64i_m/K/src/brev8-01.S

From 87f56669838daa371032b6fd885ccffb71b1649b Mon Sep 17 00:00:00 2001
From: munailwaqar <munail.waqar@10xengineers.ai>
Date: Thu, 12 Dec 2024 15:14:08 +0500
Subject: [PATCH 12/13] enabling zbkb in hpdcache_config

---
 core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
index 24d50ba0c5..8be842fa27 100644
--- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
+++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -98,7 +98,7 @@ package cva6_config_pkg;
       XF8: bit'(CVA6ConfigF8En),
       RVA: bit'(CVA6ConfigAExtEn),
       RVB: bit'(CVA6ConfigBExtEn),
-      ZKN: bit'(0),
+      ZKN: bit'(1),
       RVV: bit'(CVA6ConfigVExtEn),
       RVC: bit'(CVA6ConfigCExtEn),
       RVH: bit'(CVA6ConfigHExtEn),

From 32b98188e1b853018a27c5032128aa4cb350876c Mon Sep 17 00:00:00 2001
From: Fatima Saleem <fatima.saleem@10xengineers.ai>
Date: Wed, 18 Dec 2024 16:21:37 +0500
Subject: [PATCH 13/13] updated expected synth gate count

---
 .gitlab-ci/expected_synth.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
index 9f151284aa..d3f68f4f48 100644
--- a/.gitlab-ci/expected_synth.yml
+++ b/.gitlab-ci/expected_synth.yml
@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 187456
+  gates: 188149