From 1f0a8cc33d63c6f31dbe667f5ef20320935eb599 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Thu, 28 Nov 2024 17:04:45 +0100 Subject: [PATCH 1/2] fix size of vectors when AxiNumWords=1 --- core/cache_subsystem/wt_axi_adapter.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 6c5fe585f8..98bb1a2a98 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -82,7 +82,7 @@ module wt_axi_adapter logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy; logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay; logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr; - logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen; + logic [AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords-1:0] axi_rd_blen, axi_wr_blen; logic [2:0] axi_rd_size, axi_wr_size; logic [CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out; @@ -170,14 +170,14 @@ module wt_axi_adapter // If dcache_data.size MSB is set, we want to read as much as possible axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; if (dcache_data.size[2]) begin - axi_rd_blen = AxiRdBlenDcache[$clog2(AxiNumWords)-1:0]; + axi_rd_blen = AxiRdBlenDcache[AxiNumWords>1?$clog2(AxiNumWords) : AxiNumWords-1:0]; end end else begin // Cast to AXI address width axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr}; axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill if (!icache_data.nc) begin - axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0]; + axi_rd_blen = AxiRdBlenDcache[AxiNumWords>1?$clog2(AxiNumWords) : AxiNumWords-1:0]; end end From 43c9c3ff4ca3d6aabcd3a7de150a36576aaae573 Mon Sep 17 00:00:00 2001 From: gonzalezmarinoangela Date: Mon, 2 Dec 2024 09:32:36 +0100 Subject: [PATCH 2/2] use parameter to improve code readability --- core/cache_subsystem/wt_axi_adapter.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 98bb1a2a98..9408fb8802 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -64,6 +64,7 @@ module wt_axi_adapter localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8); localparam AxiRdBlenIcache = CVA6Cfg.ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1; localparam AxiRdBlenDcache = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1; + localparam AxiBlenWidth = AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords; /////////////////////////////////////////////////////// // request path @@ -82,7 +83,7 @@ module wt_axi_adapter logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy; logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay; logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr; - logic [AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords-1:0] axi_rd_blen, axi_wr_blen; + logic [AxiBlenWidth-1:0] axi_rd_blen, axi_wr_blen; logic [2:0] axi_rd_size, axi_wr_size; logic [CVA6Cfg.AxiIdWidth-1:0] axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out; @@ -170,14 +171,14 @@ module wt_axi_adapter // If dcache_data.size MSB is set, we want to read as much as possible axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size; if (dcache_data.size[2]) begin - axi_rd_blen = AxiRdBlenDcache[AxiNumWords>1?$clog2(AxiNumWords) : AxiNumWords-1:0]; + axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0]; end end else begin // Cast to AXI address width axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr}; axi_rd_size = MaxNumWords[2:0]; // always request max number of words in case of ifill if (!icache_data.nc) begin - axi_rd_blen = AxiRdBlenDcache[AxiNumWords>1?$clog2(AxiNumWords) : AxiNumWords-1:0]; + axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0]; end end