From c1e965f9fa0520cd658e2d97536723137bd6f243 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 15 Feb 2024 16:46:44 +0100 Subject: [PATCH 01/28] inline acc_pkg --- core/Flist.cva6 | 1 - core/acc_dispatcher.sv | 38 ++++++++++++++++++++++++++++----- core/include/acc_pkg.sv | 47 ----------------------------------------- 3 files changed, 33 insertions(+), 53 deletions(-) delete mode 100644 core/include/acc_pkg.sv diff --git a/core/Flist.cva6 b/core/Flist.cva6 index 06737a3630..c995d609ae 100644 --- a/core/Flist.cva6 +++ b/core/Flist.cva6 @@ -67,7 +67,6 @@ ${CVA6_REPO_DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv ${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv ${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv -${CVA6_REPO_DIR}/core/include/acc_pkg.sv ${CVA6_REPO_DIR}/core/include/build_config_pkg.sv //CVXIF diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 8b5998ae17..83e8678d17 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -18,8 +18,36 @@ module acc_dispatcher import riscv::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type acc_req_t = acc_pkg::accelerator_req_t, - parameter type acc_resp_t = acc_pkg::accelerator_resp_t, + localparam type accelerator_req_t = struct packed { + logic req_valid; + logic resp_ready; + riscv::instruction_t insn; + riscv::xlen_t rs1; + riscv::xlen_t rs2; + fpnew_pkg::roundmode_e frm; + logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; + logic store_pending; + // Invalidation interface + logic acc_cons_en; + logic inval_ready; + }, + parameter type acc_req_t = accelerator_req_t, + parameter type acc_resp_t = struct packed { + logic req_ready; + logic resp_valid; + riscv::xlen_t result; + logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; + logic error; + // Metadata + logic store_pending; + logic store_complete; + logic load_complete; + logic [4:0] fflags; + logic fflags_valid; + // Invalidation interface + logic inval_valid; + logic [63:0] inval_addr; + }, parameter type acc_cfg_t = logic, parameter acc_cfg_t AccCfg = '0 ) ( @@ -190,13 +218,13 @@ module acc_dispatcher * Accelerator request * *************************/ - acc_pkg::accelerator_req_t acc_req; + accelerator_req_t acc_req; logic acc_req_valid; logic acc_req_ready; - acc_pkg::accelerator_req_t acc_req_int; + accelerator_req_t acc_req_int; fall_through_register #( - .T(acc_pkg::accelerator_req_t) + .T(accelerator_req_t) ) i_accelerator_req_register ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/include/acc_pkg.sv b/core/include/acc_pkg.sv deleted file mode 100644 index bcd3c70a65..0000000000 --- a/core/include/acc_pkg.sv +++ /dev/null @@ -1,47 +0,0 @@ -// Copyright 2023 ETH Zurich and University of Bologna. -// Solderpad Hardware License, Version 0.51, see LICENSE for details. -// SPDX-License-Identifier: SHL-0.51 - -// Authors: Matheus Cavalcante -// Nils Wistoff - -// Package defining the accelerator interface as used by Ara + CVA6 - -package acc_pkg; - - // ---------------------- - // Accelerator Interface - // ---------------------- - - typedef struct packed { - logic req_valid; - logic resp_ready; - riscv::instruction_t insn; - riscv::xlen_t rs1; - riscv::xlen_t rs2; - fpnew_pkg::roundmode_e frm; - logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; - logic store_pending; - // Invalidation interface - logic acc_cons_en; - logic inval_ready; - } accelerator_req_t; - - typedef struct packed { - logic req_ready; - logic resp_valid; - riscv::xlen_t result; - logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; - logic error; - // Metadata - logic store_pending; - logic store_complete; - logic load_complete; - logic [4:0] fflags; - logic fflags_valid; - // Invalidation interface - logic inval_valid; - logic [63:0] inval_addr; - } accelerator_resp_t; - -endpackage From 303b081dddaee17d9d5d6d736dd34039c988fada Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 15 Feb 2024 19:25:32 +0100 Subject: [PATCH 02/28] add MemTidWidth to user config --- core/include/build_config_pkg.sv | 1 + core/include/config_pkg.sv | 3 +++ core/include/cv32a60x_config_pkg.sv | 1 + core/include/cv32a65x_config_pkg.sv | 1 + core/include/cv32a6_embedded_config_pkg.sv | 1 + core/include/cv32a6_ima_sv32_fpga_config_pkg.sv | 1 + core/include/cv32a6_imac_sv0_config_pkg.sv | 1 + core/include/cv32a6_imac_sv32_config_pkg.sv | 1 + core/include/cv32a6_imafc_sv32_config_pkg.sv | 1 + core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv | 1 + core/include/cv64a6_imafdc_sv39_config_pkg.sv | 1 + core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 1 + core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 1 + core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv | 1 + core/include/cv64a6_imafdcv_sv39_config_pkg.sv | 1 + corev_apu/fpga/src/ariane_xilinx.sv | 1 + 16 files changed, 18 insertions(+) diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 8c380785df..3f9acd02cc 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -28,6 +28,7 @@ package build_config_pkg; cfg.AxiDataWidth = CVA6Cfg.AxiDataWidth; cfg.AxiIdWidth = CVA6Cfg.AxiIdWidth; cfg.AxiUserWidth = CVA6Cfg.AxiUserWidth; + cfg.MEM_TID_WIDTH = CVA6Cfg.MemTidWidth; cfg.NrLoadBufEntries = CVA6Cfg.NrLoadBufEntries; cfg.FpuEn = CVA6Cfg.FpuEn; cfg.XF16 = CVA6Cfg.XF16; diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index dde3882413..d2d4e60757 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -46,6 +46,8 @@ package config_pkg; int unsigned AxiIdWidth; // AXI User width int unsigned AxiUserWidth; + // TODO + int unsigned MemTidWidth; // Load buffer entry buffer int unsigned NrLoadBufEntries; // Floating Point @@ -137,6 +139,7 @@ package config_pkg; int unsigned AxiDataWidth; int unsigned AxiIdWidth; int unsigned AxiUserWidth; + int unsigned MEM_TID_WIDTH; int unsigned NrLoadBufEntries; bit FpuEn; bit XF16; diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index dd14da87df..cbb0afb888 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index 024453acde..1bc8c8ba27 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -79,6 +79,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index b19d6c070e..09fc3daadd 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -79,6 +79,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 24c0246692..fa4e4af07a 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 5d4832be6b..4443a9e3a1 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 3b79897b09..3dcce61aec 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index df14c5bc3b..484611d3da 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index e114b2c105..4d0e3ab5da 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index c856af0f65..e09501aa78 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 6dbf24c775..c3d557b638 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -87,6 +87,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 0c766149f0..8ce332d9fa 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index e61d54c142..302e6cdca4 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index e811d47c6c..8e26632dc2 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -80,6 +80,7 @@ package cva6_config_pkg; AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), FpuEn: bit'(CVA6ConfigFpuEn), XF16: bit'(CVA6ConfigF16En), diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index 70aed05ec9..8e7d061062 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -161,6 +161,7 @@ localparam config_pkg::cva6_user_cfg_t CVA6UserCfg = '{ AxiDataWidth: cva6_config_pkg::CVA6ConfigAxiDataWidth, AxiIdWidth: cva6_config_pkg::CVA6ConfigAxiIdWidth, AxiUserWidth: cva6_config_pkg::CVA6ConfigDataUserWidth, + MemTidWidth: cva6_config_pkg::CVA6ConfigMemTidWidth, NrLoadBufEntries: cva6_config_pkg::CVA6ConfigNrLoadBufEntries, RASDepth: cva6_config_pkg::CVA6ConfigRASDepth, BTBEntries: cva6_config_pkg::CVA6ConfigBTBEntries, From df6fe39bfda98cdafe6d6250f6765562b7f5e68b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 15 Feb 2024 19:29:40 +0100 Subject: [PATCH 03/28] move DCACHE_MAX_TX --- core/cache_subsystem/wt_axi_adapter.sv | 2 +- core/cache_subsystem/wt_dcache.sv | 4 ++-- core/cache_subsystem/wt_dcache_missunit.sv | 8 ++++---- core/cache_subsystem/wt_dcache_wbuffer.sv | 14 +++++++------- core/include/build_config_pkg.sv | 2 ++ core/include/config_pkg.sv | 2 ++ core/include/wt_cache_pkg.sv | 1 - 7 files changed, 18 insertions(+), 15 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 1647f1d072..e86fe02a9d 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -20,7 +20,7 @@ module wt_axi_adapter #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned ReqFifoDepth = 2, - parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX, + parameter int unsigned MetaFifoDepth = CVA6Cfg.DCACHE_MAX_TX, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index af672d888e..e1aa193cf1 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -101,8 +101,8 @@ module wt_dcache logic [ DCACHE_SET_ASSOC-1:0] rd_hit_oh; // miss unit <-> wbuffer - logic [ DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr; - logic [ DCACHE_MAX_TX-1:0] tx_vld; + logic [ CVA6Cfg.DCACHE_MAX_TX-1:0][ riscv::PLEN-1:0] tx_paddr; + logic [ CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld; // wbuffer <-> memory wbuffer_t [ DCACHE_WBUF_DEPTH-1:0] wbuffer_data; diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 3e06a92e04..2301fea454 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -52,8 +52,8 @@ module wt_dcache_missunit output logic [NumPorts-1:0] miss_rtrn_vld_o, output logic [CACHE_ID_WIDTH-1:0] miss_rtrn_id_o, // only used for writes, set to zero fro reads // from writebuffer - input logic [DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations - input logic [DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations + input logic [CVA6Cfg.DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_i, // used to check for address collisions with read operations + input logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_i, // used to check for address collisions with read operations // write interface to cache memory output logic wr_cl_vld_o, // writes a full cacheline output logic wr_cl_nc_o, // writes a full cacheline @@ -232,7 +232,7 @@ module wt_dcache_missunit // read collides with inflight TX always_comb begin : p_tx_coll tx_rdwr_collision = 1'b0; - for (int k = 0; k < DCACHE_MAX_TX; k++) begin + for (int k = 0; k < CVA6Cfg.DCACHE_MAX_TX; k++) begin tx_rdwr_collision |= (miss_paddr_i[miss_port_idx][riscv::PLEN-1:DCACHE_OFFSET_WIDTH] == tx_paddr_i[k][riscv::PLEN-1:DCACHE_OFFSET_WIDTH]) && tx_vld_i[k]; end end @@ -325,7 +325,7 @@ module wt_dcache_missunit // keep track of pending stores logic store_sent; - logic [$clog2(wt_cache_pkg::DCACHE_MAX_TX + 1)-1:0] stores_inflight_d, stores_inflight_q; + logic [$clog2(CVA6Cfg.DCACHE_MAX_TX + 1)-1:0] stores_inflight_d, stores_inflight_q; assign store_sent = mem_data_req_o & mem_data_ack_i & (mem_data_o.rtype == DCACHE_STORE_REQ); assign stores_inflight_d = (store_ack && store_sent) ? stores_inflight_q : diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index 8e9c39d485..c46abf0590 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -101,11 +101,11 @@ module wt_dcache_wbuffer output logic [DCACHE_USER_WIDTH-1:0] wr_user_o, // to forwarding logic and miss unit output wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_data_o, - output logic [DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_o, // used to check for address collisions with read operations - output logic [DCACHE_MAX_TX-1:0] tx_vld_o + output logic [CVA6Cfg.DCACHE_MAX_TX-1:0][riscv::PLEN-1:0] tx_paddr_o, // used to check for address collisions with read operations + output logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_o ); - tx_stat_t [DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q; + tx_stat_t [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q; wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_d, wbuffer_q; logic [DCACHE_WBUF_DEPTH-1:0] valid; logic [DCACHE_WBUF_DEPTH-1:0] dirty; @@ -165,7 +165,7 @@ module wt_dcache_wbuffer assign miss_vld_bits_o = '0; assign wbuffer_data_o = wbuffer_q; - for (genvar k = 0; k < DCACHE_MAX_TX; k++) begin : gen_tx_vld + for (genvar k = 0; k < CVA6Cfg.DCACHE_MAX_TX; k++) begin : gen_tx_vld assign tx_vld_o[k] = tx_stat_q[k].vld; assign tx_paddr_o[k] = { {riscv::XLEN_ALIGN_BYTES{1'b0}}, wbuffer_q[tx_stat_q[k].ptr].wtag << riscv::XLEN_ALIGN_BYTES @@ -238,8 +238,8 @@ module wt_dcache_wbuffer // TODO: todo: make this fall through if timing permits it fifo_v3 #( .FALL_THROUGH(1'b0), - .DATA_WIDTH ($clog2(DCACHE_MAX_TX)), - .DEPTH (DCACHE_MAX_TX) + .DATA_WIDTH ($clog2(CVA6Cfg.DCACHE_MAX_TX)), + .DEPTH (CVA6Cfg.DCACHE_MAX_TX) ) i_rtrn_id_fifo ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -287,7 +287,7 @@ module wt_dcache_wbuffer // next word to lookup in the cache rr_arb_tree #( - .NumIn (DCACHE_MAX_TX), + .NumIn (CVA6Cfg.DCACHE_MAX_TX), .LockIn (1'b1), .DataWidth(1) ) i_tx_id_rr ( diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 3f9acd02cc..96610de7ff 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -84,6 +84,8 @@ package build_config_pkg; cfg.NonIdemPotenceEn = CVA6Cfg.NrNonIdempotentRules && CVA6Cfg.NonIdempotentLength; cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; + cfg.DCACHE_MAX_TX = unsigned'(2 ** CVA6Cfg.MemTidWidth); + return cfg; endfunction diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index d2d4e60757..14f6b9f0df 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -194,6 +194,8 @@ package config_pkg; bit DebugEn; bit NonIdemPotenceEn; // Currently only used by V extension (Ara) bit AxiBurstWriteEn; + + int unsigned DCACHE_MAX_TX; } cva6_cfg_t; /// Empty configuration to sanity check proper parameter passing. Whenever diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 9a8c0ce034..ddc7efd3c3 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -64,7 +64,6 @@ package wt_cache_pkg; // write buffer parameterization localparam DCACHE_WBUF_DEPTH = ariane_pkg::WT_DCACHE_WBUF_DEPTH; - localparam DCACHE_MAX_TX = 2 ** L15_TID_WIDTH; localparam CACHE_ID_WIDTH = L15_TID_WIDTH; From 48953efade785356212646ddd735cdec43a87d90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Tue, 28 Nov 2023 08:55:25 +0100 Subject: [PATCH 04/28] propagate CVA6Cfg --- common/local/util/ex_trace_item.svh | 5 ++++- common/local/util/instr_trace_item.svh | 4 +++- common/local/util/instr_tracer.sv | 14 ++++++++++---- common/local/util/instr_tracer_if.sv | 4 +++- core/cva6.sv | 6 ++++-- 5 files changed, 24 insertions(+), 9 deletions(-) diff --git a/common/local/util/ex_trace_item.svh b/common/local/util/ex_trace_item.svh index 91b090c625..5705e59ced 100644 --- a/common/local/util/ex_trace_item.svh +++ b/common/local/util/ex_trace_item.svh @@ -13,7 +13,10 @@ // Description: Instruction tracer single exception item `ifndef VERILATOR -class ex_trace_item; +class ex_trace_item #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +); + // contains a human readable form of the cause value string cause_s; logic [63:0] cause; diff --git a/common/local/util/instr_trace_item.svh b/common/local/util/instr_trace_item.svh index b9b1bbbdd3..9d28b028a7 100644 --- a/common/local/util/instr_trace_item.svh +++ b/common/local/util/instr_trace_item.svh @@ -22,7 +22,9 @@ function string printPCexpr(input logic [63:0] imm); end endfunction -class instr_trace_item; +class instr_trace_item #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +); // keep a couple of general purpose information inside this instruction item time simtime; longint unsigned cycle; diff --git a/common/local/util/instr_tracer.sv b/common/local/util/instr_tracer.sv index 17c11e5f14..a697f88de0 100644 --- a/common/local/util/instr_tracer.sv +++ b/common/local/util/instr_tracer.sv @@ -17,8 +17,10 @@ `include "ex_trace_item.svh" `include "instr_trace_item.svh" -module instr_tracer ( - instr_tracer_if tracer_if, +module instr_tracer #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +)( + instr_tracer_if tracer_if, input logic[riscv::XLEN-1:0] hart_id_i ); @@ -187,7 +189,9 @@ module instr_tracer ( endfunction function void printInstr(ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); - automatic instr_trace_item iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); + automatic instr_trace_item #( + .CVA6Cfg(CVA6Cfg) + ) iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); // print instruction to console automatic string print_instr = iti.printInstr(); if (ariane_pkg::ENABLE_SPIKE_COMMIT_LOG && !debug_mode) begin @@ -197,7 +201,9 @@ module instr_tracer ( endfunction function void printException(logic [riscv::VLEN-1:0] pc, logic [63:0] cause, logic [63:0] tval); - automatic ex_trace_item eti = new (pc, cause, tval); + automatic ex_trace_item #( + .CVA6Cfg(CVA6Cfg) + ) eti = new (pc, cause, tval); automatic string print_ex = eti.printException(); $fwrite(f, {print_ex, "\n"}); endfunction diff --git a/common/local/util/instr_tracer_if.sv b/common/local/util/instr_tracer_if.sv index 5015cfd7d0..17cefc7425 100644 --- a/common/local/util/instr_tracer_if.sv +++ b/common/local/util/instr_tracer_if.sv @@ -15,7 +15,9 @@ `ifndef VERILATOR `ifndef INSTR_TRACER_IF_SV `define INSTR_TRACER_IF_SV -interface instr_tracer_if ( +interface instr_tracer_if #( + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty +)( input clk ); diff --git a/core/cva6.sv b/core/cva6.sv index 8147074fc9..47400e8064 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1167,7 +1167,7 @@ module cva6 `endif // PITON_ARIANE `ifndef VERILATOR - instr_tracer_if tracer_if (clk_i); + instr_tracer_if #(.CVA6Cfg(CVA6Cfg)) tracer_if (clk_i); // assign instruction tracer interface // control signals assign tracer_if.rstn = rst_ni; @@ -1204,7 +1204,9 @@ module cva6 assign tracer_if.priv_lvl = priv_lvl; assign tracer_if.debug_mode = debug_mode; - instr_tracer instr_tracer_i ( + instr_tracer #( + .CVA6Cfg(CVA6Cfg) + ) instr_tracer_i ( .tracer_if(tracer_if), .hart_id_i ); From 1924b2a76f2ef3e1d2f44610970d84076f88eeb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 18:23:48 +0100 Subject: [PATCH 05/28] move scoreboard_entry_t --- common/local/util/instr_trace_item.svh | 7 ++- common/local/util/instr_tracer.sv | 18 +++--- common/local/util/instr_tracer_if.sv | 7 ++- core/acc_dispatcher.sv | 11 ++-- core/commit_stage.sv | 3 +- core/csr_regfile.sv | 7 ++- core/cva6.sv | 66 +++++++++++++++++----- core/cva6_accel_first_pass_decoder_stub.sv | 4 +- core/cva6_rvfi_probes.sv | 1 + core/decoder.sv | 7 ++- core/id_stage.sv | 28 ++++----- core/include/ariane_pkg.sv | 28 --------- core/issue_read_operands.sv | 1 + core/issue_stage.sv | 11 ++-- core/perf_counters.sv | 5 +- core/scoreboard.sv | 25 ++++---- 16 files changed, 130 insertions(+), 99 deletions(-) diff --git a/common/local/util/instr_trace_item.svh b/common/local/util/instr_trace_item.svh index 9d28b028a7..e4819a1c9c 100644 --- a/common/local/util/instr_trace_item.svh +++ b/common/local/util/instr_trace_item.svh @@ -23,12 +23,13 @@ function string printPCexpr(input logic [63:0] imm); endfunction class instr_trace_item #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic ); // keep a couple of general purpose information inside this instruction item time simtime; longint unsigned cycle; - ariane_pkg::scoreboard_entry_t sbe; + scoreboard_entry_t sbe; logic [31:0] pc; logic [31:0] instr; logic [63:0] gp_reg_file [32]; @@ -46,7 +47,7 @@ class instr_trace_item #( logic [4:0] rs1, rs2, rs3, rd; // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information - function new (time simtime, longint unsigned cycle, ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32], + function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32], logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); this.simtime = simtime; this.cycle = cycle; diff --git a/common/local/util/instr_tracer.sv b/common/local/util/instr_tracer.sv index a697f88de0..218f87e223 100644 --- a/common/local/util/instr_tracer.sv +++ b/common/local/util/instr_tracer.sv @@ -18,7 +18,8 @@ `include "instr_trace_item.svh" module instr_tracer #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic )( instr_tracer_if tracer_if, input logic[riscv::XLEN-1:0] hart_id_i @@ -29,8 +30,8 @@ module instr_tracer #( // keep the issued instructions in a queue logic [31:0] issue_queue [$]; // issue scoreboard entries - ariane_pkg::scoreboard_entry_t issue_sbe_queue [$]; - ariane_pkg::scoreboard_entry_t issue_sbe; + scoreboard_entry_t issue_sbe_queue [$]; + scoreboard_entry_t issue_sbe; // store resolved branches, get (mis-)predictions ariane_pkg::bp_resolve_t bp [$]; // shadow copy of the register files @@ -57,7 +58,7 @@ module instr_tracer #( task trace(); automatic logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction; - automatic ariane_pkg::scoreboard_entry_t commit_instruction; + automatic scoreboard_entry_t commit_instruction; // initialize register 0 gp_reg_file = '{default:0}; fp_reg_file = '{default:0}; @@ -90,7 +91,7 @@ module instr_tracer #( issue_instruction = decode_queue.pop_front(); issue_queue.push_back(issue_instruction); // also save the scoreboard entry to a separate issue queue - issue_sbe_queue.push_back(ariane_pkg::scoreboard_entry_t'(tracer_if.pck.issue_sbe)); + issue_sbe_queue.push_back(scoreboard_entry_t'(tracer_if.pck.issue_sbe)); end // -------------------- @@ -115,7 +116,7 @@ module instr_tracer #( // we are committing an instruction for (int i = 0; i < 2; i++) begin if (tracer_if.pck.commit_ack[i]) begin - commit_instruction = ariane_pkg::scoreboard_entry_t'(tracer_if.pck.commit_instr[i]); + commit_instruction = scoreboard_entry_t'(tracer_if.pck.commit_instr[i]); issue_commit_instruction = issue_queue.pop_front(); issue_sbe = issue_sbe_queue.pop_front(); // check if the instruction retiring is a load or store, get the physical address accordingly @@ -188,9 +189,10 @@ module instr_tracer #( bp = {}; endfunction - function void printInstr(ariane_pkg::scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); + function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); automatic instr_trace_item #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) ) iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); // print instruction to console automatic string print_instr = iti.printInstr(); diff --git a/common/local/util/instr_tracer_if.sv b/common/local/util/instr_tracer_if.sv index 17cefc7425..c5557ad898 100644 --- a/common/local/util/instr_tracer_if.sv +++ b/common/local/util/instr_tracer_if.sv @@ -16,7 +16,8 @@ `ifndef INSTR_TRACER_IF_SV `define INSTR_TRACER_IF_SV interface instr_tracer_if #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic )( input clk ); @@ -30,14 +31,14 @@ interface instr_tracer_if #( logic fetch_ack; // Issue stage logic issue_ack; // issue acknowledged - ariane_pkg::scoreboard_entry_t issue_sbe; // issue scoreboard entry + scoreboard_entry_t issue_sbe; // issue scoreboard entry // WB stage logic [1:0][4:0] waddr; logic [1:0][63:0] wdata; logic [1:0] we_gpr; logic [1:0] we_fpr; // commit stage - ariane_pkg::scoreboard_entry_t [1:0] commit_instr; // commit instruction + scoreboard_entry_t [1:0] commit_instr; // commit instruction logic [1:0] commit_ack; // address translation // stores diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 83e8678d17..840e63493f 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -17,7 +17,8 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic, localparam type accelerator_req_t = struct packed { logic req_valid; logic resp_ready; @@ -48,8 +49,8 @@ module acc_dispatcher logic inval_valid; logic [63:0] inval_addr; }, - parameter type acc_cfg_t = logic, - parameter acc_cfg_t AccCfg = '0 + parameter type acc_cfg_t = logic, + parameter acc_cfg_t AccCfg = '0 ) ( input logic clk_i, input logic rst_ni, @@ -219,8 +220,8 @@ module acc_dispatcher *************************/ accelerator_req_t acc_req; - logic acc_req_valid; - logic acc_req_ready; + logic acc_req_valid; + logic acc_req_ready; accelerator_req_t acc_req_int; fall_through_register #( diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 112641266b..96a0860dde 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -16,7 +16,8 @@ module commit_stage import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 8a1f78bfdd..ca7b0acb26 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -16,9 +16,10 @@ module csr_regfile import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int AsidWidth = 1, - parameter int unsigned MHPMCounterNum = 6 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic, + parameter int AsidWidth = 1, + parameter int unsigned MHPMCounterNum = 6 ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/cva6.sv b/core/cva6.sv index 47400e8064..bdf0b16aa8 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -21,6 +21,31 @@ module cva6 cva6_config_pkg::cva6_cfg ), + // ID/EX/WB Stage + parameter type scoreboard_entry_t = struct packed { + logic [riscv::VLEN-1:0] pc; // PC of instruction + logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry + // with the transaction id in any case make the width more generic + fu_t fu; // functional unit to use + fu_op op; // operation to perform in each functional unit + logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1 + logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2 + logic [REG_ADDR_SIZE-1:0] rd; // register destination address + riscv::xlen_t result; // for unfinished instructions this field also holds the immediate, + // for unfinished floating-point that are partly encoded in rs2, this field also holds rs2 + // for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB) + // this field holds the address of the third operand from the floating-point register file + logic valid; // is the result valid + logic use_imm; // should we use the immediate as operand b? + logic use_zimm; // use zimm as operand a + logic use_pc; // set if we need to use the PC as operand a, PC from exception + exception_t ex; // exception has occurred + branchpredict_sbe_t bp; // branch predict scoreboard data structure + logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if + // we want jump accordingly e.g.: +4, +2 + logic vfp; // is this a vector floating-point instruction? + }, + parameter type rvfi_probes_t = struct packed { logic csr; //disabled rvfi_probes_instr_t instr; @@ -392,7 +417,8 @@ module cva6 // ID // --------- id_stage #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) ) id_stage_i ( .clk_i, .rst_ni, @@ -491,7 +517,8 @@ module cva6 // Issue // --------- issue_stage #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) ) issue_stage_i ( .clk_i, .rst_ni, @@ -678,7 +705,8 @@ module cva6 assign no_st_pending_commit = no_st_pending_ex & dcache_commit_wbuffer_empty; commit_stage #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) ) commit_stage_i ( .clk_i, .rst_ni, @@ -717,9 +745,10 @@ module cva6 // CSR // --------- csr_regfile #( - .CVA6Cfg (CVA6Cfg), - .AsidWidth (ASID_WIDTH), - .MHPMCounterNum(MHPMCounterNum) + .CVA6Cfg (CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t), + .AsidWidth (ASID_WIDTH), + .MHPMCounterNum (MHPMCounterNum) ) csr_regfile_i ( .flush_o (flush_csr_ctrl), .halt_csr_o (halt_csr_ctrl), @@ -786,7 +815,8 @@ module cva6 // ------------------------ if (PERF_COUNTER_EN) begin : gen_perf_counter perf_counters #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t), .NumPorts(NumPorts) ) perf_counters_i ( .clk_i (clk_i), @@ -1036,11 +1066,12 @@ module cva6 if (CVA6Cfg.EnableAccelerator) begin : gen_accelerator acc_dispatcher #( - .CVA6Cfg (CVA6Cfg), - .acc_cfg_t (acc_cfg_t), - .AccCfg (AccCfg), - .acc_req_t (cvxif_req_t), - .acc_resp_t(cvxif_resp_t) + .CVA6Cfg (CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t), + .acc_cfg_t (acc_cfg_t), + .AccCfg (AccCfg), + .acc_req_t (cvxif_req_t), + .acc_resp_t (cvxif_resp_t) ) i_acc_dispatcher ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -1167,7 +1198,12 @@ module cva6 `endif // PITON_ARIANE `ifndef VERILATOR - instr_tracer_if #(.CVA6Cfg(CVA6Cfg)) tracer_if (clk_i); + instr_tracer_if #( + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) + ) tracer_if ( + clk_i + ); // assign instruction tracer interface // control signals assign tracer_if.rstn = rst_ni; @@ -1205,7 +1241,8 @@ module cva6 assign tracer_if.debug_mode = debug_mode; instr_tracer #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) ) instr_tracer_i ( .tracer_if(tracer_if), .hart_id_i @@ -1273,6 +1310,7 @@ module cva6 cva6_rvfi_probes #( .CVA6Cfg (CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t), .rvfi_probes_t(rvfi_probes_t) ) i_cva6_rvfi_probes ( diff --git a/core/cva6_accel_first_pass_decoder_stub.sv b/core/cva6_accel_first_pass_decoder_stub.sv index 20ffb1e965..00c9ec1deb 100644 --- a/core/cva6_accel_first_pass_decoder_stub.sv +++ b/core/cva6_accel_first_pass_decoder_stub.sv @@ -9,7 +9,9 @@ module cva6_accel_first_pass_decoder import ariane_pkg::*; -( +#( + parameter type scoreboard_entry_t = logic +) ( input logic [31:0] instruction_i, // instruction from IF input riscv::xs_t fs_i, // floating point extension status input riscv::xs_t vs_i, // vector extension status diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index db7d9e4555..6b6883b58d 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -13,6 +13,7 @@ module cva6_rvfi_probes import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic, parameter type rvfi_probes_t = logic ) ( diff --git a/core/decoder.sv b/core/decoder.sv index 4961e9523d..9fdf806622 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -22,7 +22,8 @@ module decoder import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic ) ( // Debug (async) request - SUBSYSTEM input logic debug_req_i, @@ -103,7 +104,9 @@ module decoder // This module is responsible for a light-weight decoding of accelerator instructions, // identifying them, but also whether they read/write scalar registers. // Accelerators are supposed to define this module. - cva6_accel_first_pass_decoder i_accel_decoder ( + cva6_accel_first_pass_decoder #( + .scoreboard_entry_t(scoreboard_entry_t) + ) i_accel_decoder ( .instruction_i(instruction_i), .fs_i(fs_i), .vs_i(vs_i), diff --git a/core/id_stage.sv b/core/id_stage.sv index 7dfda5a8b2..cae5b293d6 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -14,7 +14,8 @@ // issue and read operands. module id_stage #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -31,7 +32,7 @@ module id_stage #( // Handshake's ready between fetch and decode - FRONTEND output logic fetch_entry_ready_o, // Handshake's data between decode and issue - ISSUE - output ariane_pkg::scoreboard_entry_t issue_entry_o, + output scoreboard_entry_t issue_entry_o, // Instruction value - ISSUE output logic [31:0] orig_instr_o, // Handshake's valid between decode and issue - ISSUE @@ -65,20 +66,20 @@ module id_stage #( ); // ID/ISSUE register stage typedef struct packed { - logic valid; - ariane_pkg::scoreboard_entry_t sbe; - logic [31:0] orig_instr; - logic is_ctrl_flow; + logic valid; + scoreboard_entry_t sbe; + logic [31:0] orig_instr; + logic is_ctrl_flow; } issue_struct_t; issue_struct_t issue_n, issue_q; - logic is_control_flow_instr; - ariane_pkg::scoreboard_entry_t decoded_instruction; - logic [31:0] orig_instr; + logic is_control_flow_instr; + scoreboard_entry_t decoded_instruction; + logic [31:0] orig_instr; - logic is_illegal; - logic [31:0] instruction; - logic is_compressed; + logic is_illegal; + logic [31:0] instruction; + logic is_compressed; if (CVA6Cfg.RVC) begin // --------------------------------------------------------- @@ -103,7 +104,8 @@ module id_stage #( // 2. Decode and emit instruction to issue stage // --------------------------------------------------------- decoder #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t) ) decoder_i ( .debug_req_i, .irq_ctrl_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index cd242c5fb5..9d230868c0 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -669,34 +669,6 @@ package ariane_pkg; exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions } fetch_entry_t; - // --------------- - // ID/EX/WB Stage - // --------------- - - typedef struct packed { - logic [riscv::VLEN-1:0] pc; // PC of instruction - logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry - // with the transaction id in any case make the width more generic - fu_t fu; // functional unit to use - fu_op op; // operation to perform in each functional unit - logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1 - logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2 - logic [REG_ADDR_SIZE-1:0] rd; // register destination address - riscv::xlen_t result; // for unfinished instructions this field also holds the immediate, - // for unfinished floating-point that are partly encoded in rs2, this field also holds rs2 - // for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB) - // this field holds the address of the third operand from the floating-point register file - logic valid; // is the result valid - logic use_imm; // should we use the immediate as operand b? - logic use_zimm; // use zimm as operand a - logic use_pc; // set if we need to use the PC as operand a, PC from exception - exception_t ex; // exception has occurred - branchpredict_sbe_t bp; // branch predict scoreboard data structure - logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if - // we want jump accordingly e.g.: +4, +2 - logic vfp; // is this a vector floating-point instruction? - } scoreboard_entry_t; - // --------------- // MMU instanciation // --------------- diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index a46bc81fe5..34c5ed93b7 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -18,6 +18,7 @@ module issue_read_operands import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic, parameter type rs3_len_t = logic ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/issue_stage.sv b/core/issue_stage.sv index e5dfa3b51b..66a03eb543 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -17,7 +17,8 @@ module issue_stage import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -157,8 +158,9 @@ module issue_stage // 2. Manage instructions in a scoreboard // --------------------------------------------------------- scoreboard #( - .CVA6Cfg (CVA6Cfg), - .rs3_len_t(rs3_len_t) + .CVA6Cfg (CVA6Cfg), + .rs3_len_t (rs3_len_t), + .scoreboard_entry_t(scoreboard_entry_t) ) i_scoreboard ( .sb_full_o (sb_full_o), .unresolved_branch_i(1'b0), @@ -193,7 +195,8 @@ module issue_stage // 3. Issue instruction and read operand, also commit // --------------------------------------------------------- issue_read_operands #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), + .scoreboard_entry_t(scoreboard_entry_t), .rs3_len_t(rs3_len_t) ) i_issue_read_operands ( .flush_i (flush_unissued_instr_i), diff --git a/core/perf_counters.sv b/core/perf_counters.sv index e78eebe22b..fe1c1de043 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -16,8 +16,9 @@ module perf_counters import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned NumPorts = 3 // number of miss ports + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic, + parameter int unsigned NumPorts = 3 // number of miss ports ) ( input logic clk_i, input logic rst_ni, diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 568a4aa7ef..51437a9417 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -14,6 +14,7 @@ module scoreboard #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type scoreboard_entry_t = logic, parameter type rs3_len_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -56,30 +57,30 @@ module scoreboard #( // advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer // TO_BE_COMPLETED - TO_BE_COMPLETED - output ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, + output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, // TO_BE_COMPLETED - TO_BE_COMPLETED - input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // instruction to put on top of scoreboard e.g.: top pointer // we can always put this instruction to the top unless we signal with asserted full_o // TO_BE_COMPLETED - TO_BE_COMPLETED - input ariane_pkg::scoreboard_entry_t decoded_instr_i, + input scoreboard_entry_t decoded_instr_i, // TO_BE_COMPLETED - TO_BE_COMPLETED - input logic [31:0] orig_instr_i, + input logic [31:0] orig_instr_i, // TO_BE_COMPLETED - TO_BE_COMPLETED - input logic decoded_instr_valid_i, + input logic decoded_instr_valid_i, // TO_BE_COMPLETED - TO_BE_COMPLETED - output logic decoded_instr_ack_o, + output logic decoded_instr_ack_o, // instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer // Issue scoreboard entry - ACC_DISPATCHER - output ariane_pkg::scoreboard_entry_t issue_instr_o, + output scoreboard_entry_t issue_instr_o, // TO_BE_COMPLETED - TO_BE_COMPLETED - output logic [31:0] orig_instr_o, + output logic [31:0] orig_instr_o, // TO_BE_COMPLETED - TO_BE_COMPLETED - output logic issue_instr_valid_o, + output logic issue_instr_valid_o, // TO_BE_COMPLETED - TO_BE_COMPLETED - input logic issue_ack_i, + input logic issue_ack_i, // TO_BE_COMPLETED - TO_BE_COMPLETED input ariane_pkg::bp_resolve_t resolved_branch_i, @@ -104,7 +105,7 @@ module scoreboard #( typedef struct packed { logic issued; // this bit indicates whether we issued this instruction e.g.: if it is valid logic is_rd_fpr_flag; // redundant meta info, added for speed - ariane_pkg::scoreboard_entry_t sbe; // this is the score board entry we will send to ex + scoreboard_entry_t sbe; // this is the score board entry we will send to ex } sb_mem_t; sb_mem_t [ariane_pkg::NR_SB_ENTRIES-1:0] mem_q, mem_n; @@ -121,7 +122,7 @@ module scoreboard #( assign sb_full_o = issue_full; - ariane_pkg::scoreboard_entry_t decoded_instr; + scoreboard_entry_t decoded_instr; always_comb begin decoded_instr = decoded_instr_i; end From b1f856a0fcd65e4b93655a61a222057f17e661ee Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 17:54:41 +0100 Subject: [PATCH 06/28] move fetch_entry_t --- core/cva6.sv | 13 ++++++++++++- core/frontend/frontend.sv | 6 ++++-- core/frontend/instr_queue.sv | 5 +++-- core/id_stage.sv | 3 ++- core/include/ariane_pkg.sv | 11 ----------- 5 files changed, 21 insertions(+), 17 deletions(-) diff --git a/core/cva6.sv b/core/cva6.sv index bdf0b16aa8..2a781c5372 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -46,6 +46,15 @@ module cva6 logic vfp; // is this a vector floating-point instruction? }, + // IF/ID Stage + // store the decompressed instruction + parameter type fetch_entry_t = struct packed { + logic [riscv::VLEN-1:0] address; // the address of the instructions from below + logic [31:0] instruction; // instruction word + branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path + exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions + }, + parameter type rvfi_probes_t = struct packed { logic csr; //disabled rvfi_probes_instr_t instr; @@ -390,7 +399,8 @@ module cva6 // Frontend // -------------- frontend #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .fetch_entry_t(fetch_entry_t) ) i_frontend ( .flush_i (flush_ctrl_if), // not entirely correct .flush_bp_i (1'b0), @@ -418,6 +428,7 @@ module cva6 // --------- id_stage #( .CVA6Cfg(CVA6Cfg), + .fetch_entry_t(fetch_entry_t), .scoreboard_entry_t(scoreboard_entry_t) ) id_stage_i ( .clk_i, diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 68891c5be7..7e3994da6b 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -18,7 +18,8 @@ module frontend import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fetch_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -497,7 +498,8 @@ module frontend end instr_queue #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .fetch_entry_t(fetch_entry_t) ) i_instr_queue ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index ec80657e68..0394841997 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -46,7 +46,8 @@ module instr_queue import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fetch_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -77,7 +78,7 @@ module instr_queue // Address at which to replay the fetch - FRONTEND output logic [riscv::VLEN-1:0] replay_addr_o, // Handshake’s data with ID_STAGE - ID_STAGE - output ariane_pkg::fetch_entry_t fetch_entry_o, + output fetch_entry_t fetch_entry_o, // Handshake’s valid with ID_STAGE - ID_STAGE output logic fetch_entry_valid_o, // Handshake’s ready with ID_STAGE - ID_STAGE diff --git a/core/id_stage.sv b/core/id_stage.sv index cae5b293d6..de303bc07d 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -15,6 +15,7 @@ module id_stage #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fetch_entry_t = logic, parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -26,7 +27,7 @@ module id_stage #( // Debug (async) request - SUBSYSTEM input logic debug_req_i, // Handshake's data between fetch and decode - FRONTEND - input ariane_pkg::fetch_entry_t fetch_entry_i, + input fetch_entry_t fetch_entry_i, // Handshake's valid between fetch and decode - FRONTEND input logic fetch_entry_valid_i, // Handshake's ready between fetch and decode - FRONTEND diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 9d230868c0..7dfedd1710 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -658,17 +658,6 @@ package ariane_pkg; logic [TRANS_ID_BITS-1:0] trans_id; } lsu_ctrl_t; - // --------------- - // IF/ID Stage - // --------------- - // store the decompressed instruction - typedef struct packed { - logic [riscv::VLEN-1:0] address; // the address of the instructions from below - logic [31:0] instruction; // instruction word - branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path - exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions - } fetch_entry_t; - // --------------- // MMU instanciation // --------------- From e4fb3335d41d5a652abe29ccf04c3fd92e5df483 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Mon, 27 Nov 2023 10:44:29 +0100 Subject: [PATCH 07/28] move bp_resolve_t & branchpredict_sbe_t --- common/local/util/instr_trace_item.svh | 5 +-- common/local/util/instr_tracer.sv | 8 +++-- common/local/util/instr_tracer_if.sv | 3 +- core/branch_unit.sv | 8 +++-- core/controller.sv | 3 +- core/cva6.sv | 47 +++++++++++++++++++++----- core/decoder.sv | 1 + core/ex_stage.sv | 6 +++- core/frontend/frontend.sv | 1 + core/id_stage.sv | 2 ++ core/include/ariane_pkg.sv | 21 ------------ core/issue_read_operands.sv | 1 + core/issue_stage.sv | 4 +++ core/perf_counters.sv | 1 + core/scoreboard.sv | 3 +- 15 files changed, 73 insertions(+), 41 deletions(-) diff --git a/common/local/util/instr_trace_item.svh b/common/local/util/instr_trace_item.svh index e4819a1c9c..c941968459 100644 --- a/common/local/util/instr_trace_item.svh +++ b/common/local/util/instr_trace_item.svh @@ -24,6 +24,7 @@ endfunction class instr_trace_item #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, parameter type scoreboard_entry_t = logic ); // keep a couple of general purpose information inside this instruction item @@ -42,13 +43,13 @@ class instr_trace_item #( logic [63:0] result; logic [riscv::PLEN-1:0] paddr; string priv_lvl; - ariane_pkg::bp_resolve_t bp; + bp_resolve_t bp; logic [4:0] rs1, rs2, rs3, rd; // constructor creating a new instruction trace item, e.g.: a single instruction with all relevant information function new (time simtime, longint unsigned cycle, scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] gp_reg_file [32], - logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); + logic [63:0] fp_reg_file [32], logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); this.simtime = simtime; this.cycle = cycle; this.pc = sbe.pc; diff --git a/common/local/util/instr_tracer.sv b/common/local/util/instr_tracer.sv index 218f87e223..e7c6eb5eee 100644 --- a/common/local/util/instr_tracer.sv +++ b/common/local/util/instr_tracer.sv @@ -19,6 +19,7 @@ module instr_tracer #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, parameter type scoreboard_entry_t = logic )( instr_tracer_if tracer_if, @@ -33,7 +34,7 @@ module instr_tracer #( scoreboard_entry_t issue_sbe_queue [$]; scoreboard_entry_t issue_sbe; // store resolved branches, get (mis-)predictions - ariane_pkg::bp_resolve_t bp [$]; + bp_resolve_t bp [$]; // shadow copy of the register files logic [63:0] gp_reg_file [32]; logic [63:0] fp_reg_file [32]; @@ -64,7 +65,7 @@ module instr_tracer #( fp_reg_file = '{default:0}; forever begin - automatic ariane_pkg::bp_resolve_t bp_instruction = '0; + automatic bp_resolve_t bp_instruction = '0; // new cycle, we are only interested if reset is de-asserted @(tracer_if.pck) if (tracer_if.pck.rstn !== 1'b1) begin flush(); @@ -189,9 +190,10 @@ module instr_tracer #( bp = {}; endfunction - function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, ariane_pkg::bp_resolve_t bp); + function void printInstr(scoreboard_entry_t sbe, logic [31:0] instr, logic [63:0] result, logic [riscv::PLEN-1:0] paddr, riscv::priv_lvl_t priv_lvl, logic debug_mode, bp_resolve_t bp); automatic instr_trace_item #( .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t) ) iti = new ($time, clk_ticks, sbe, instr, gp_reg_file, fp_reg_file, result, paddr, priv_lvl, debug_mode, bp); // print instruction to console diff --git a/common/local/util/instr_tracer_if.sv b/common/local/util/instr_tracer_if.sv index c5557ad898..42b2ff23c3 100644 --- a/common/local/util/instr_tracer_if.sv +++ b/common/local/util/instr_tracer_if.sv @@ -17,6 +17,7 @@ `define INSTR_TRACER_IF_SV interface instr_tracer_if #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, parameter type scoreboard_entry_t = logic )( input clk @@ -49,7 +50,7 @@ interface instr_tracer_if #( logic ld_kill; logic [riscv::PLEN-1:0] ld_paddr; // misprediction - ariane_pkg::bp_resolve_t resolve_branch; + bp_resolve_t resolve_branch; // exceptions ariane_pkg::exception_t exception; // current privilege level diff --git a/core/branch_unit.sv b/core/branch_unit.sv index f7070e100b..d6d93d6696 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -13,7 +13,9 @@ // Description: Branch target calculation and comparison module branch_unit #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type branchpredict_sbe_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -36,9 +38,9 @@ module branch_unit #( // Brach unit result - ISSUE_STAGE output logic [riscv::VLEN-1:0] branch_result_o, // Information of branch prediction - ISSUE_STAGE - input ariane_pkg::branchpredict_sbe_t branch_predict_i, + input branchpredict_sbe_t branch_predict_i, // Signaling that we resolved the branch - ISSUE_STAGE - output ariane_pkg::bp_resolve_t resolved_branch_o, + output bp_resolve_t resolved_branch_o, // Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE output logic resolve_branch_o, // Branch exception out - TO_BE_COMPLETED diff --git a/core/controller.sv b/core/controller.sv index c678613bb5..b59b99716a 100644 --- a/core/controller.sv +++ b/core/controller.sv @@ -16,7 +16,8 @@ module controller import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/cva6.sv b/core/cva6.sv index 2a781c5372..f9d2d812d5 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -21,6 +21,23 @@ module cva6 cva6_config_pkg::cva6_cfg ), + // branchpredict scoreboard entry + // this is the struct which we will inject into the pipeline to guide the various + // units towards the correct branch decision and resolve + parameter type branchpredict_sbe_t = struct packed { + cf_t cf; // type of control flow prediction + logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not + }, + + // IF/ID Stage + // store the decompressed instruction + parameter type fetch_entry_t = struct packed { + logic [riscv::VLEN-1:0] address; // the address of the instructions from below + logic [31:0] instruction; // instruction word + branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path + exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions + }, + // ID/EX/WB Stage parameter type scoreboard_entry_t = struct packed { logic [riscv::VLEN-1:0] pc; // PC of instruction @@ -46,13 +63,17 @@ module cva6 logic vfp; // is this a vector floating-point instruction? }, - // IF/ID Stage - // store the decompressed instruction - parameter type fetch_entry_t = struct packed { - logic [riscv::VLEN-1:0] address; // the address of the instructions from below - logic [31:0] instruction; // instruction word - branchpredict_sbe_t branch_predict; // this field contains branch prediction information regarding the forward branch path - exception_t ex; // this field contains exceptions which might have happened earlier, e.g.: fetch exceptions + // branch-predict + // this is the struct we get back from ex stage and we will use it to update + // all the necessary data structures + // bp_resolve_t + parameter type bp_resolve_t = struct packed { + logic valid; // prediction with all its values is valid + logic [riscv::VLEN-1:0] pc; // PC of predict or mis-predict + logic [riscv::VLEN-1:0] target_address; // target address at which to jump, or not + logic is_mispredict; // set if this was a mis-predict + logic is_taken; // branch is taken + cf_t cf_type; // Type of control flow change }, parameter type rvfi_probes_t = struct packed { @@ -400,6 +421,7 @@ module cva6 // -------------- frontend #( .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), .fetch_entry_t(fetch_entry_t) ) i_frontend ( .flush_i (flush_ctrl_if), // not entirely correct @@ -428,6 +450,7 @@ module cva6 // --------- id_stage #( .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), .fetch_entry_t(fetch_entry_t), .scoreboard_entry_t(scoreboard_entry_t) ) id_stage_i ( @@ -529,6 +552,8 @@ module cva6 // --------- issue_stage #( .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .branchpredict_sbe_t(branchpredict_sbe_t), .scoreboard_entry_t(scoreboard_entry_t) ) issue_stage_i ( .clk_i, @@ -603,6 +628,8 @@ module cva6 // --------- ex_stage #( .CVA6Cfg (CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .branchpredict_sbe_t(branchpredict_sbe_t), .ASID_WIDTH(ASID_WIDTH) ) ex_stage_i ( .clk_i (clk_i), @@ -827,6 +854,7 @@ module cva6 if (PERF_COUNTER_EN) begin : gen_perf_counter perf_counters #( .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t), .NumPorts(NumPorts) ) perf_counters_i ( @@ -866,7 +894,8 @@ module cva6 // Controller // ------------ controller #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t) ) controller_i ( // flush ports .set_pc_commit_o (set_pc_ctrl_pcgen), @@ -1211,6 +1240,7 @@ module cva6 `ifndef VERILATOR instr_tracer_if #( .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t) ) tracer_if ( clk_i @@ -1253,6 +1283,7 @@ module cva6 instr_tracer #( .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t) ) instr_tracer_i ( .tracer_if(tracer_if), diff --git a/core/decoder.sv b/core/decoder.sv index 9fdf806622..92369d4641 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -23,6 +23,7 @@ module decoder import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type branchpredict_sbe_t = logic, parameter type scoreboard_entry_t = logic ) ( // Debug (async) request - SUBSYSTEM diff --git a/core/ex_stage.sv b/core/ex_stage.sv index d6237dcc24..75910d912f 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -18,6 +18,8 @@ module ex_stage import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type branchpredict_sbe_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( // Subsystem Clock - SUBSYSTEM @@ -242,7 +244,9 @@ module ex_stage // we don't silence the branch unit as this is already critical and we do // not want to add another layer of logic branch_unit #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .bp_resolve_t(bp_resolve_t), + .branchpredict_sbe_t(branchpredict_sbe_t) ) branch_unit_i ( .clk_i, .rst_ni, diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 7e3994da6b..c6d18c79d6 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -19,6 +19,7 @@ module frontend import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, parameter type fetch_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/id_stage.sv b/core/id_stage.sv index de303bc07d..b5d72ff820 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -15,6 +15,7 @@ module id_stage #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type branchpredict_sbe_t = logic, parameter type fetch_entry_t = logic, parameter type scoreboard_entry_t = logic ) ( @@ -106,6 +107,7 @@ module id_stage #( // --------------------------------------------------------- decoder #( .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), .scoreboard_entry_t(scoreboard_entry_t) ) decoder_i ( .debug_req_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 7dfedd1710..8cb0ae19e4 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -184,27 +184,6 @@ package ariane_pkg; Return // Return Address Prediction } cf_t; - // branch-predict - // this is the struct we get back from ex stage and we will use it to update - // all the necessary data structures - // bp_resolve_t - typedef struct packed { - logic valid; // prediction with all its values is valid - logic [riscv::VLEN-1:0] pc; // PC of predict or mis-predict - logic [riscv::VLEN-1:0] target_address; // target address at which to jump, or not - logic is_mispredict; // set if this was a mis-predict - logic is_taken; // branch is taken - cf_t cf_type; // Type of control flow change - } bp_resolve_t; - - // branchpredict scoreboard entry - // this is the struct which we will inject into the pipeline to guide the various - // units towards the correct branch decision and resolve - typedef struct packed { - cf_t cf; // type of control flow prediction - logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not - } branchpredict_sbe_t; - typedef struct packed { logic valid; logic [riscv::VLEN-1:0] pc; // update at PC diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 34c5ed93b7..7a87b31fb3 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -18,6 +18,7 @@ module issue_read_operands import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type branchpredict_sbe_t = logic, parameter type scoreboard_entry_t = logic, parameter type rs3_len_t = logic ) ( diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 66a03eb543..a17a8c785d 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -18,6 +18,8 @@ module issue_stage import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, + parameter type branchpredict_sbe_t = logic, parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -160,6 +162,7 @@ module issue_stage scoreboard #( .CVA6Cfg (CVA6Cfg), .rs3_len_t (rs3_len_t), + .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t) ) i_scoreboard ( .sb_full_o (sb_full_o), @@ -196,6 +199,7 @@ module issue_stage // --------------------------------------------------------- issue_read_operands #( .CVA6Cfg(CVA6Cfg), + .branchpredict_sbe_t(branchpredict_sbe_t), .scoreboard_entry_t(scoreboard_entry_t), .rs3_len_t(rs3_len_t) ) i_issue_read_operands ( diff --git a/core/perf_counters.sv b/core/perf_counters.sv index fe1c1de043..f62de00188 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -17,6 +17,7 @@ module perf_counters import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, parameter type scoreboard_entry_t = logic, parameter int unsigned NumPorts = 3 // number of miss ports ) ( diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 51437a9417..9f5120bf44 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -14,6 +14,7 @@ module scoreboard #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bp_resolve_t = logic, parameter type scoreboard_entry_t = logic, parameter type rs3_len_t = logic ) ( @@ -83,7 +84,7 @@ module scoreboard #( input logic issue_ack_i, // TO_BE_COMPLETED - TO_BE_COMPLETED - input ariane_pkg::bp_resolve_t resolved_branch_i, + input bp_resolve_t resolved_branch_i, // Transaction ID at which to write the result back - TO_BE_COMPLETED input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, // Results to write back - TO_BE_COMPLETED From 13861e98d9a7069c7f38fa89b2f7fee381bddcdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Tue, 28 Nov 2023 10:13:01 +0100 Subject: [PATCH 08/28] move satp_t --- core/csr_regfile.sv | 12 +++++++++--- core/include/ariane_pkg.sv | 4 ++-- core/include/riscv_pkg.sv | 6 ------ 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index ca7b0acb26..f06b5aec95 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -141,6 +141,12 @@ module csr_regfile output rvfi_probes_csr_t rvfi_csr_o ); + typedef struct packed { + logic [riscv::ModeW-1:0] mode; + logic [riscv::ASIDW-1:0] asid; + logic [riscv::PPNW-1:0] ppn; + } satp_t; + // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; logic csr_we, csr_read; @@ -156,7 +162,7 @@ module csr_regfile logic dirty_fp_state_csr; riscv::mstatus_rv_t mstatus_q, mstatus_d; riscv::xlen_t mstatus_extended; - riscv::satp_t satp_q, satp_d; + satp_t satp_q, satp_d; riscv::dcsr_t dcsr_q, dcsr_d; riscv::csr_t csr_addr; // privilege level register @@ -597,7 +603,7 @@ module csr_regfile // --------------------------- riscv::xlen_t mask; always_comb begin : csr_update - automatic riscv::satp_t satp; + automatic satp_t satp; automatic logic [63:0] instret; @@ -818,7 +824,7 @@ module csr_regfile // intercept SATP writes if in S-Mode and TVM is enabled if (priv_lvl_o == riscv::PRIV_LVL_S && mstatus_q.tvm) update_access_exception = 1'b1; else begin - satp = riscv::satp_t'(csr_wdata); + satp = satp_t'(csr_wdata); // only make ASID_LEN - 1 bit stick, that way software can figure out how many ASID bits are supported satp.asid = satp.asid & {{(riscv::ASIDW - AsidWidth) {1'b0}}, {AsidWidth{1'b1}}}; // only update if we actually support this mode diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 8cb0ae19e4..4693bf718e 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -830,7 +830,7 @@ package ariane_pkg; riscv::xlen_t sepc_q; riscv::xlen_t scause_q; riscv::xlen_t stval_q; - riscv::satp_t satp_q; + riscv::xlen_t satp_q; riscv::xlen_t mstatus_extended; riscv::xlen_t medeleg_q; riscv::xlen_t mideleg_q; @@ -849,7 +849,7 @@ package ariane_pkg; riscv::xlen_t acc_cons_q; riscv::pmpcfg_t [15:0] pmpcfg_q; logic [15:0][riscv::PLEN-3:0] pmpaddr_q; - } rvfi_probes_csr_t; + } rvfi_probes_csr_t; // RVFI CSR structure typedef struct packed { diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv index 18ae2cfc23..695b34c30c 100644 --- a/core/include/riscv_pkg.sv +++ b/core/include/riscv_pkg.sv @@ -123,12 +123,6 @@ package riscv; logic wpri0; // writes preserved reads ignored } mstatus_rv_t; - typedef struct packed { - logic [ModeW-1:0] mode; - logic [ASIDW-1:0] asid; - logic [PPNW-1:0] ppn; - } satp_t; - // -------------------- // Instruction Types // -------------------- From 076dd3dcb713c0ea8966b09836a9c75dcc41878f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 15:20:09 +0100 Subject: [PATCH 09/28] move btb_update_t --- core/frontend/btb.sv | 3 ++- core/frontend/frontend.sv | 8 ++++++++ core/include/ariane_pkg.sv | 6 ------ 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/core/frontend/btb.sv b/core/frontend/btb.sv index 3f0001f746..1c9185f3db 100644 --- a/core/frontend/btb.sv +++ b/core/frontend/btb.sv @@ -27,6 +27,7 @@ // branch target buffer module btb #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type btb_update_t = logic, parameter int NR_ENTRIES = 8 ) ( // Subsystem Clock - SUBSYSTEM @@ -40,7 +41,7 @@ module btb #( // Virtual PC - CACHE input logic [riscv::VLEN-1:0] vpc_i, // Update BTB with resolved address - EXECUTE - input ariane_pkg::btb_update_t btb_update_i, + input btb_update_t btb_update_i, // BTB Prediction - FRONTEND output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o ); diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index c6d18c79d6..181617e620 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -63,6 +63,13 @@ module frontend // Handshake's ready between fetch and decode - ID_STAGE input logic fetch_entry_ready_i ); + + localparam type btb_update_t = struct packed { + logic valid; + logic [riscv::VLEN-1:0] pc; // update at PC + logic [riscv::VLEN-1:0] target_address; + }; + // Instruction Cache Registers, from I$ logic [ FETCH_WIDTH-1:0] icache_data_q; logic icache_valid_q; @@ -446,6 +453,7 @@ module frontend end else begin : btb_gen btb #( .CVA6Cfg (CVA6Cfg), + .btb_update_t(btb_update_t), .NR_ENTRIES(CVA6Cfg.BTBEntries) ) i_btb ( .clk_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 4693bf718e..83cc26c6d2 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -184,12 +184,6 @@ package ariane_pkg; Return // Return Address Prediction } cf_t; - typedef struct packed { - logic valid; - logic [riscv::VLEN-1:0] pc; // update at PC - logic [riscv::VLEN-1:0] target_address; - } btb_update_t; - typedef struct packed { logic valid; logic [riscv::VLEN-1:0] target_address; From f2a44b1c31541b332f9f0795d0e29c2d488ca8cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 15:25:03 +0100 Subject: [PATCH 10/28] move btb_prediction_t --- core/frontend/btb.sv | 7 ++++--- core/frontend/frontend.sv | 6 ++++++ core/include/ariane_pkg.sv | 5 ----- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/core/frontend/btb.sv b/core/frontend/btb.sv index 1c9185f3db..f561a881ad 100644 --- a/core/frontend/btb.sv +++ b/core/frontend/btb.sv @@ -28,6 +28,7 @@ module btb #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type btb_update_t = logic, + parameter type btb_prediction_t = logic, parameter int NR_ENTRIES = 8 ) ( // Subsystem Clock - SUBSYSTEM @@ -43,7 +44,7 @@ module btb #( // Update BTB with resolved address - EXECUTE input btb_update_t btb_update_i, // BTB Prediction - FRONTEND - output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o + output btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o ); // the last bit is always zero, we don't need it for indexing localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; @@ -57,7 +58,7 @@ module btb #( // prevent aliasing to degrade performance localparam ANTIALIAS_BITS = 8; // number of bits par word in the bram - localparam BRAM_WORD_BITS = $bits(ariane_pkg::btb_prediction_t); + localparam BRAM_WORD_BITS = $bits(btb_prediction_t); // we are not interested in all bits of the address unread i_unread (.d_i(|vpc_i)); @@ -147,7 +148,7 @@ module btb #( // typedef for all branch target entries // we may want to try to put a tag field that fills the rest of the PC in-order to mitigate aliasing effects - ariane_pkg::btb_prediction_t + btb_prediction_t btb_d[NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0], btb_q[NR_ROWS-1:0][ariane_pkg::INSTR_PER_FETCH-1:0]; diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 181617e620..801fefce2f 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -64,6 +64,11 @@ module frontend input logic fetch_entry_ready_i ); + localparam type btb_prediction_t = struct packed { + logic valid; + logic [riscv::VLEN-1:0] target_address; + }; + localparam type btb_update_t = struct packed { logic valid; logic [riscv::VLEN-1:0] pc; // update at PC @@ -454,6 +459,7 @@ module frontend btb #( .CVA6Cfg (CVA6Cfg), .btb_update_t(btb_update_t), + .btb_prediction_t(btb_prediction_t), .NR_ENTRIES(CVA6Cfg.BTBEntries) ) i_btb ( .clk_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 83cc26c6d2..bce8554336 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -184,11 +184,6 @@ package ariane_pkg; Return // Return Address Prediction } cf_t; - typedef struct packed { - logic valid; - logic [riscv::VLEN-1:0] target_address; - } btb_prediction_t; - typedef struct packed { logic valid; logic [riscv::VLEN-1:0] ra; From fcd38f3aac01122f8a3178852f4df0236c22c7c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 15:29:47 +0100 Subject: [PATCH 11/28] move ras_t --- core/frontend/frontend.sv | 6 ++++++ core/frontend/ras.sv | 5 +++-- core/include/ariane_pkg.sv | 5 ----- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 801fefce2f..a151ff1802 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -75,6 +75,11 @@ module frontend logic [riscv::VLEN-1:0] target_address; }; + localparam type ras_t = struct packed { + logic valid; + logic [riscv::VLEN-1:0] ra; + }; + // Instruction Cache Registers, from I$ logic [ FETCH_WIDTH-1:0] icache_data_q; logic icache_valid_q; @@ -436,6 +441,7 @@ module frontend end else begin : ras_gen ras #( .CVA6Cfg(CVA6Cfg), + .ras_t (ras_t), .DEPTH (CVA6Cfg.RASDepth) ) i_ras ( .clk_i, diff --git a/core/frontend/ras.sv b/core/frontend/ras.sv index 8ee0ec16f2..73f2da2860 100644 --- a/core/frontend/ras.sv +++ b/core/frontend/ras.sv @@ -16,6 +16,7 @@ // return address stack module ras #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type ras_t = logic, parameter int unsigned DEPTH = 2 ) ( // Subsystem Clock - SUBSYSTEM @@ -31,10 +32,10 @@ module ras #( // Data to be pushed - FRONTEND input logic [riscv::VLEN-1:0] data_i, // Popped data - FRONTEND - output ariane_pkg::ras_t data_o + output ras_t data_o ); - ariane_pkg::ras_t [DEPTH-1:0] stack_d, stack_q; + ras_t [DEPTH-1:0] stack_d, stack_q; assign data_o = stack_q[0]; diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index bce8554336..0773afea84 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -184,11 +184,6 @@ package ariane_pkg; Return // Return Address Prediction } cf_t; - typedef struct packed { - logic valid; - logic [riscv::VLEN-1:0] ra; - } ras_t; - typedef struct packed { logic valid; logic [riscv::VLEN-1:0] pc; // update at PC From ba5648acbf7e33a45c87008d00e1a4bb9e72b46f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 15:32:41 +0100 Subject: [PATCH 12/28] move bht_update_t --- core/frontend/bht.sv | 3 ++- core/frontend/frontend.sv | 7 +++++++ core/include/ariane_pkg.sv | 6 ------ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv index 7390939a6d..5e738c44b5 100644 --- a/core/frontend/bht.sv +++ b/core/frontend/bht.sv @@ -20,6 +20,7 @@ module bht #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type bht_update_t = logic, parameter int unsigned NR_ENTRIES = 1024 ) ( // Subsystem Clock - SUBSYSTEM @@ -33,7 +34,7 @@ module bht #( // Virtual PC - CACHE input logic [riscv::VLEN-1:0] vpc_i, // Update bht with resolved address - EXECUTE - input ariane_pkg::bht_update_t bht_update_i, + input bht_update_t bht_update_i, // Prediction from bht - FRONTEND output ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] bht_prediction_o ); diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index a151ff1802..c13226660e 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -64,6 +64,12 @@ module frontend input logic fetch_entry_ready_i ); + localparam type bht_update_t = struct packed { + logic valid; + logic [riscv::VLEN-1:0] pc; // update at PC + logic taken; + }; + localparam type btb_prediction_t = struct packed { logic valid; logic [riscv::VLEN-1:0] target_address; @@ -483,6 +489,7 @@ module frontend end else begin : bht_gen bht #( .CVA6Cfg (CVA6Cfg), + .bht_update_t(bht_update_t), .NR_ENTRIES(CVA6Cfg.BHTEntries) ) i_bht ( .clk_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 0773afea84..c5b4d9885c 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -184,12 +184,6 @@ package ariane_pkg; Return // Return Address Prediction } cf_t; - typedef struct packed { - logic valid; - logic [riscv::VLEN-1:0] pc; // update at PC - logic taken; - } bht_update_t; - typedef struct packed { logic valid; logic taken; From f869054f512e98eec69d1dab7d20467d827d4432 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 15:41:07 +0100 Subject: [PATCH 13/28] move irq_ctrl_t --- core/csr_regfile.sv | 1 + core/cva6.sv | 12 ++++++++++++ core/decoder.sv | 1 + core/id_stage.sv | 4 +++- core/include/ariane_pkg.sv | 10 ---------- 5 files changed, 17 insertions(+), 11 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index f06b5aec95..fe679feef8 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -17,6 +17,7 @@ module csr_regfile import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type irq_ctrl_t = logic, parameter type scoreboard_entry_t = logic, parameter int AsidWidth = 1, parameter int unsigned MHPMCounterNum = 6 diff --git a/core/cva6.sv b/core/cva6.sv index f9d2d812d5..e423a6205b 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -76,6 +76,16 @@ module cva6 cf_t cf_type; // Type of control flow change }, + // All information needed to determine whether we need to associate an interrupt + // with the corresponding instruction or not. + parameter type irq_ctrl_t = struct packed { + logic [riscv::XLEN-1:0] mie; + logic [riscv::XLEN-1:0] mip; + logic [riscv::XLEN-1:0] mideleg; + logic sie; + logic global_enable; + }, + parameter type rvfi_probes_t = struct packed { logic csr; //disabled rvfi_probes_instr_t instr; @@ -452,6 +462,7 @@ module cva6 .CVA6Cfg(CVA6Cfg), .branchpredict_sbe_t(branchpredict_sbe_t), .fetch_entry_t(fetch_entry_t), + .irq_ctrl_t(irq_ctrl_t), .scoreboard_entry_t(scoreboard_entry_t) ) id_stage_i ( .clk_i, @@ -784,6 +795,7 @@ module cva6 // --------- csr_regfile #( .CVA6Cfg (CVA6Cfg), + .irq_ctrl_t (irq_ctrl_t), .scoreboard_entry_t(scoreboard_entry_t), .AsidWidth (ASID_WIDTH), .MHPMCounterNum (MHPMCounterNum) diff --git a/core/decoder.sv b/core/decoder.sv index 92369d4641..ee67957cd0 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -24,6 +24,7 @@ module decoder #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type branchpredict_sbe_t = logic, + parameter type irq_ctrl_t = logic, parameter type scoreboard_entry_t = logic ) ( // Debug (async) request - SUBSYSTEM diff --git a/core/id_stage.sv b/core/id_stage.sv index b5d72ff820..597f6147cd 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -17,6 +17,7 @@ module id_stage #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type branchpredict_sbe_t = logic, parameter type fetch_entry_t = logic, + parameter type irq_ctrl_t = logic, parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -56,7 +57,7 @@ module id_stage #( // Level sensitive (async) interrupts - SUBSYSTEM input logic [1:0] irq_i, // Interrupt control status - CSR_REGFILE - input ariane_pkg::irq_ctrl_t irq_ctrl_i, + input irq_ctrl_t irq_ctrl_i, // Is current mode debug ? - CSR_REGFILE input logic debug_mode_i, // Trap virtual memory - CSR_REGFILE @@ -108,6 +109,7 @@ module id_stage #( decoder #( .CVA6Cfg(CVA6Cfg), .branchpredict_sbe_t(branchpredict_sbe_t), + .irq_ctrl_t(irq_ctrl_t), .scoreboard_entry_t(scoreboard_entry_t) ) decoder_i ( .debug_req_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index c5b4d9885c..a689a26bfc 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -213,16 +213,6 @@ package ariane_pkg; localparam SupervisorIrq = 1; localparam MachineIrq = 0; - // All information needed to determine whether we need to associate an interrupt - // with the corresponding instruction or not. - typedef struct packed { - riscv::xlen_t mie; - riscv::xlen_t mip; - riscv::xlen_t mideleg; - logic sie; - logic global_enable; - } irq_ctrl_t; - // --------------- // Cache config // --------------- From 177f86e57f91e5d71ca87589bbef13b64b490b24 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 17:18:10 +0100 Subject: [PATCH 14/28] move fu_data_t --- core/acc_dispatcher.sv | 1 + core/alu.sv | 3 ++- core/branch_unit.sv | 5 +++-- core/csr_buffer.sv | 3 ++- core/cva6.sv | 12 ++++++++++++ core/cvxif_fu.sv | 3 ++- core/ex_stage.sv | 20 ++++++++++++++------ core/fpu_wrap.sv | 3 ++- core/include/ariane_pkg.sv | 9 --------- core/issue_read_operands.sv | 1 + core/issue_stage.sv | 2 ++ core/load_store_unit.sv | 1 + core/mult.sv | 3 ++- 13 files changed, 44 insertions(+), 22 deletions(-) diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 840e63493f..0aeef88364 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -18,6 +18,7 @@ module acc_dispatcher import riscv::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic, localparam type accelerator_req_t = struct packed { logic req_valid; diff --git a/core/alu.sv b/core/alu.sv index e57e0d1fd5..4432299beb 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -21,7 +21,8 @@ module alu import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/branch_unit.sv b/core/branch_unit.sv index d6d93d6696..2c5bb3f103 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -15,7 +15,8 @@ module branch_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, - parameter type branchpredict_sbe_t = logic + parameter type branchpredict_sbe_t = logic, + parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, @@ -24,7 +25,7 @@ module branch_unit #( // Debug mode state - CSR_REGFILE input logic debug_mode_i, // FU data needed to execute instruction - ISSUE_STAGE - input ariane_pkg::fu_data_t fu_data_i, + input fu_data_t fu_data_i, // Instruction PC - ISSUE_STAGE input logic [riscv::VLEN-1:0] pc_i, // Instruction is compressed - ISSUE_STAGE diff --git a/core/csr_buffer.sv b/core/csr_buffer.sv index 8c93052b69..1d01b7efcd 100644 --- a/core/csr_buffer.sv +++ b/core/csr_buffer.sv @@ -17,7 +17,8 @@ module csr_buffer import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/cva6.sv b/core/cva6.sv index e423a6205b..23055d1f70 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -86,6 +86,15 @@ module cva6 logic global_enable; }, + parameter type fu_data_t = struct packed { + fu_t fu; + fu_op operation; + logic [riscv::XLEN-1:0] operand_a; + logic [riscv::XLEN-1:0] operand_b; + logic [riscv::XLEN-1:0] imm; + logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; + }, + parameter type rvfi_probes_t = struct packed { logic csr; //disabled rvfi_probes_instr_t instr; @@ -565,6 +574,7 @@ module cva6 .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), + .fu_data_t(fu_data_t), .scoreboard_entry_t(scoreboard_entry_t) ) issue_stage_i ( .clk_i, @@ -641,6 +651,7 @@ module cva6 .CVA6Cfg (CVA6Cfg), .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), + .fu_data_t(fu_data_t), .ASID_WIDTH(ASID_WIDTH) ) ex_stage_i ( .clk_i (clk_i), @@ -1119,6 +1130,7 @@ module cva6 if (CVA6Cfg.EnableAccelerator) begin : gen_accelerator acc_dispatcher #( .CVA6Cfg (CVA6Cfg), + .fu_data_t (fu_data_t), .scoreboard_entry_t(scoreboard_entry_t), .acc_cfg_t (acc_cfg_t), .AccCfg (AccCfg), diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index b1dabfcd0c..f111282708 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -13,7 +13,8 @@ module cvxif_fu import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 75910d912f..c3f73a6342 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -20,6 +20,7 @@ module ex_stage parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, + parameter type fu_data_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( // Subsystem Clock - SUBSYSTEM @@ -231,7 +232,8 @@ module ex_stage assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0; alu #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .fu_data_t(fu_data_t) ) alu_i ( .clk_i, .rst_ni, @@ -246,7 +248,8 @@ module ex_stage branch_unit #( .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), - .branchpredict_sbe_t(branchpredict_sbe_t) + .branchpredict_sbe_t(branchpredict_sbe_t), + .fu_data_t(fu_data_t) ) branch_unit_i ( .clk_i, .rst_ni, @@ -267,7 +270,8 @@ module ex_stage // 3. CSR (sequential) csr_buffer #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg (CVA6Cfg), + .fu_data_t(fu_data_t) ) csr_buffer_i ( .clk_i, .rst_ni, @@ -310,7 +314,8 @@ module ex_stage assign mult_data = mult_valid_i ? fu_data_i : '0; mult #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg (CVA6Cfg), + .fu_data_t(fu_data_t) ) i_mult ( .clk_i, .rst_ni, @@ -332,7 +337,8 @@ module ex_stage assign fpu_data = fpu_valid_i ? fu_data_i : '0; fpu_wrap #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg (CVA6Cfg), + .fu_data_t(fu_data_t) ) fpu_i ( .clk_i, .rst_ni, @@ -367,6 +373,7 @@ module ex_stage load_store_unit #( .CVA6Cfg (CVA6Cfg), + .fu_data_t (fu_data_t), .ASID_WIDTH(ASID_WIDTH) ) lsu_i ( .clk_i, @@ -420,7 +427,8 @@ module ex_stage fu_data_t cvxif_data; assign cvxif_data = x_valid_i ? fu_data_i : '0; cvxif_fu #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .fu_data_t(fu_data_t) ) cvxif_fu_i ( .clk_i, .rst_ni, diff --git a/core/fpu_wrap.sv b/core/fpu_wrap.sv index 1cc0260d3a..efc0871893 100644 --- a/core/fpu_wrap.sv +++ b/core/fpu_wrap.sv @@ -16,7 +16,8 @@ module fpu_wrap import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index a689a26bfc..15701140a3 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -501,15 +501,6 @@ package ariane_pkg; CZERO_NEZ } fu_op; - typedef struct packed { - fu_t fu; - fu_op operation; - riscv::xlen_t operand_a; - riscv::xlen_t operand_b; - riscv::xlen_t imm; - logic [TRANS_ID_BITS-1:0] trans_id; - } fu_data_t; - function automatic logic op_is_branch(input fu_op op); unique case (op) inside EQ, NE, LTS, GES, LTU, GEU: return 1'b1; diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 7a87b31fb3..ea9a358f28 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -19,6 +19,7 @@ module issue_read_operands #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type branchpredict_sbe_t = logic, + parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic, parameter type rs3_len_t = logic ) ( diff --git a/core/issue_stage.sv b/core/issue_stage.sv index a17a8c785d..2162e4389a 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -20,6 +20,7 @@ module issue_stage parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, + parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -200,6 +201,7 @@ module issue_stage issue_read_operands #( .CVA6Cfg(CVA6Cfg), .branchpredict_sbe_t(branchpredict_sbe_t), + .fu_data_t(fu_data_t), .scoreboard_entry_t(scoreboard_entry_t), .rs3_len_t(rs3_len_t) ) i_issue_read_operands ( diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index cb899c6c05..52ee8f3326 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -17,6 +17,7 @@ module load_store_unit import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/mult.sv b/core/mult.sv index dcb0fa6a3c..07993af41e 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -3,7 +3,8 @@ module mult import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, From 9aa4e22ec141723375230ae97db988912449ace9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 9 Nov 2023 17:22:31 +0100 Subject: [PATCH 15/28] move lsu_ctrl_t --- core/cva6.sv | 13 +++++++++++++ core/cva6_rvfi_probes.sv | 1 + core/ex_stage.sv | 2 ++ core/include/ariane_pkg.sv | 11 ----------- core/load_store_unit.sv | 11 ++++++++--- core/load_unit.sv | 3 ++- core/lsu_bypass.sv | 3 ++- core/store_unit.sv | 3 ++- 8 files changed, 30 insertions(+), 17 deletions(-) diff --git a/core/cva6.sv b/core/cva6.sv index 23055d1f70..caf706ab84 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -86,6 +86,17 @@ module cva6 logic global_enable; }, + parameter type lsu_ctrl_t = struct packed { + logic valid; + logic [riscv::VLEN-1:0] vaddr; + logic overflow; + logic [riscv::XLEN-1:0] data; + logic [(riscv::XLEN/8)-1:0] be; + fu_t fu; + fu_op operation; + logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; + }, + parameter type fu_data_t = struct packed { fu_t fu; fu_op operation; @@ -652,6 +663,7 @@ module cva6 .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), .fu_data_t(fu_data_t), + .lsu_ctrl_t(lsu_ctrl_t), .ASID_WIDTH(ASID_WIDTH) ) ex_stage_i ( .clk_i (clk_i), @@ -1377,6 +1389,7 @@ module cva6 cva6_rvfi_probes #( .CVA6Cfg (CVA6Cfg), .scoreboard_entry_t(scoreboard_entry_t), + .lsu_ctrl_t (lsu_ctrl_t), .rvfi_probes_t(rvfi_probes_t) ) i_cva6_rvfi_probes ( diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 6b6883b58d..1daa5c2e64 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -14,6 +14,7 @@ module cva6_rvfi_probes #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type scoreboard_entry_t = logic, + parameter type lsu_ctrl_t = logic, parameter type rvfi_probes_t = logic ) ( diff --git a/core/ex_stage.sv b/core/ex_stage.sv index c3f73a6342..b0b50a438e 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -21,6 +21,7 @@ module ex_stage parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, parameter type fu_data_t = logic, + parameter type lsu_ctrl_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( // Subsystem Clock - SUBSYSTEM @@ -374,6 +375,7 @@ module ex_stage load_store_unit #( .CVA6Cfg (CVA6Cfg), .fu_data_t (fu_data_t), + .lsu_ctrl_t(lsu_ctrl_t), .ASID_WIDTH(ASID_WIDTH) ) lsu_i ( .clk_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 15701140a3..a710633e3c 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -585,17 +585,6 @@ package ariane_pkg; endcase endfunction - typedef struct packed { - logic valid; - logic [riscv::VLEN-1:0] vaddr; - logic overflow; - riscv::xlen_t data; - logic [(riscv::XLEN/8)-1:0] be; - fu_t fu; - fu_op operation; - logic [TRANS_ID_BITS-1:0] trans_id; - } lsu_ctrl_t; - // --------------- // MMU instanciation // --------------- diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 52ee8f3326..50d3db8f7b 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -18,6 +18,7 @@ module load_store_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type fu_data_t = logic, + parameter type lsu_ctrl_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( // Subsystem Clock - SUBSYSTEM @@ -119,6 +120,7 @@ module load_store_unit // RVFI information - RVFI output [riscv::PLEN-1:0] rvfi_mem_paddr_o ); + // data is misaligned logic data_misaligned; // -------------------------------------- @@ -282,7 +284,8 @@ module load_store_unit // Store Unit // ------------------ store_unit #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .lsu_ctrl_t(lsu_ctrl_t) ) i_store_unit ( .clk_i, .rst_ni, @@ -324,7 +327,8 @@ module load_store_unit // Load Unit // ------------------ load_unit #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .lsu_ctrl_t(lsu_ctrl_t) ) i_load_unit ( .valid_i (ld_valid_i), .lsu_ctrl_i(lsu_ctrl), @@ -518,7 +522,8 @@ module load_store_unit }; lsu_bypass #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .lsu_ctrl_t(lsu_ctrl_t) ) lsu_bypass_i ( .lsu_req_i (lsu_req_i), .lsu_req_valid_i(lsu_valid_i), diff --git a/core/load_unit.sv b/core/load_unit.sv index 2b5bec9446..ec2963d477 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -21,7 +21,8 @@ module load_unit import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/lsu_bypass.sv b/core/lsu_bypass.sv index 5790c73a95..2b9f2aaa6f 100644 --- a/core/lsu_bypass.sv +++ b/core/lsu_bypass.sv @@ -26,7 +26,8 @@ module lsu_bypass import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/store_unit.sv b/core/store_unit.sv index 0c0a75de8b..618e12b470 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -16,7 +16,8 @@ module store_unit import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, From 3bb1fe41f8a478c0e1890cd7213743e0e1b1cb84 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Fri, 10 Nov 2023 11:40:50 +0100 Subject: [PATCH 16/28] move icache_arsp_t --- core/cache_subsystem/cva6_hpdcache_subsystem.sv | 4 +++- core/cache_subsystem/cva6_icache.sv | 1 + core/cache_subsystem/cva6_icache_axi_wrapper.sv | 4 +++- core/cache_subsystem/std_cache_subsystem.sv | 2 ++ core/cache_subsystem/wt_cache_subsystem.sv | 4 +++- core/cva6.sv | 10 ++++++++++ core/ex_stage.sv | 2 ++ core/include/ariane_pkg.sv | 5 ----- core/load_store_unit.sv | 3 +++ core/mmu_sv32/cva6_mmu_sv32.sv | 1 + core/mmu_sv39/mmu.sv | 1 + 11 files changed, 29 insertions(+), 8 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index d439b2c300..870165ef62 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -17,6 +17,7 @@ module cva6_hpdcache_subsystem // {{{ #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, parameter int NumPorts = 4, parameter int NrHwPrefetchers = 4, // AXI types @@ -45,7 +46,7 @@ module cva6_hpdcache_subsystem output logic icache_miss_o, // to performance counter // address translation requests input ariane_pkg::icache_areq_t icache_areq_i, // to/from frontend - output ariane_pkg::icache_arsp_t icache_areq_o, + output icache_arsp_t icache_areq_o, // data requests input ariane_pkg::icache_dreq_t icache_dreq_i, // to/from frontend output ariane_pkg::icache_drsp_t icache_dreq_o, @@ -105,6 +106,7 @@ module cva6_hpdcache_subsystem cva6_icache #( .CVA6Cfg(CVA6Cfg), + .icache_arsp_t(icache_arsp_t), .RdTxId (ICACHE_RDTXID) ) i_cva6_icache ( .clk_i (clk_i), diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 37dd8d1dff..982554bfd0 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -30,6 +30,7 @@ module cva6_icache import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, /// ID to be used for read transactions parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0 ) ( diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index 7579fe4b67..ce4f38ecd8 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -18,6 +18,7 @@ module cva6_icache_axi_wrapper import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( @@ -102,7 +103,8 @@ module cva6_icache_axi_wrapper cva6_icache #( // use ID 0 for icache reads .CVA6Cfg(CVA6Cfg), - .RdTxId (0) + .icache_arsp_t(icache_arsp_t), + .RdTxId(0) ) i_cva6_icache ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 45ba8bd3c1..0bb0a559be 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -20,6 +20,7 @@ module std_cache_subsystem import std_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, parameter int unsigned NumPorts = 4, parameter type axi_ar_chan_t = logic, parameter type axi_aw_chan_t = logic, @@ -69,6 +70,7 @@ module std_cache_subsystem cva6_icache_axi_wrapper #( .CVA6Cfg (CVA6Cfg), + .icache_arsp_t(icache_arsp_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t) ) i_cva6_icache_axi_wrapper ( diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index ec094671c4..29aeba07df 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -24,6 +24,7 @@ module wt_cache_subsystem import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, parameter int unsigned NumPorts = 4, parameter type noc_req_t = logic, parameter type noc_resp_t = logic @@ -79,7 +80,8 @@ module wt_cache_subsystem cva6_icache #( // use ID 0 for icache reads .CVA6Cfg(CVA6Cfg), - .RdTxId (0) + .icache_arsp_t(icache_arsp_t), + .RdTxId(0) ) i_cva6_icache ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/cva6.sv b/core/cva6.sv index caf706ab84..d41265e028 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -29,6 +29,12 @@ module cva6 logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not }, + // cache request ports + parameter type icache_arsp_t = struct packed { + logic fetch_req; // address translation request + logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out + }, + // IF/ID Stage // store the decompressed instruction parameter type fetch_entry_t = struct packed { @@ -663,6 +669,7 @@ module cva6 .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), .fu_data_t(fu_data_t), + .icache_arsp_t(icache_arsp_t), .lsu_ctrl_t(lsu_ctrl_t), .ASID_WIDTH(ASID_WIDTH) ) ex_stage_i ( @@ -995,6 +1002,7 @@ module cva6 // this is a cache subsystem that is compatible with OpenPiton wt_cache_subsystem #( .CVA6Cfg (CVA6Cfg), + .icache_arsp_t(icache_arsp_t), .NumPorts (NumPorts), .noc_req_t (noc_req_t), .noc_resp_t(noc_resp_t) @@ -1035,6 +1043,7 @@ module cva6 end else if (DCACHE_TYPE == int'(config_pkg::HPDCACHE)) begin : gen_cache_hpd cva6_hpdcache_subsystem #( .CVA6Cfg (CVA6Cfg), + .icache_arsp_t(icache_arsp_t), .NumPorts (NumPorts), .axi_ar_chan_t(axi_ar_chan_t), .axi_aw_chan_t(axi_aw_chan_t), @@ -1095,6 +1104,7 @@ module cva6 // not as important since this cache subsystem is about to be // deprecated .CVA6Cfg (CVA6Cfg), + .icache_arsp_t(icache_arsp_t), .NumPorts (NumPorts), .axi_ar_chan_t(axi_ar_chan_t), .axi_aw_chan_t(axi_aw_chan_t), diff --git a/core/ex_stage.sv b/core/ex_stage.sv index b0b50a438e..b83a92979d 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -21,6 +21,7 @@ module ex_stage parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, parameter type fu_data_t = logic, + parameter type icache_arsp_t = logic, parameter type lsu_ctrl_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( @@ -375,6 +376,7 @@ module ex_stage load_store_unit #( .CVA6Cfg (CVA6Cfg), .fu_data_t (fu_data_t), + .icache_arsp_t(icache_arsp_t), .lsu_ctrl_t(lsu_ctrl_t), .ASID_WIDTH(ASID_WIDTH) ) lsu_i ( diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index a710633e3c..eef14b90d6 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -656,11 +656,6 @@ package ariane_pkg; exception_t fetch_exception; // exception occurred during fetch } icache_areq_t; - typedef struct packed { - logic fetch_req; // address translation request - logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out - } icache_arsp_t; - // I$ data requests typedef struct packed { logic req; // we request a new word diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 50d3db8f7b..86fa6cf6af 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -18,6 +18,7 @@ module load_store_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type fu_data_t = logic, + parameter type icache_arsp_t = logic, parameter type lsu_ctrl_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( @@ -181,6 +182,7 @@ module load_store_unit if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39 mmu #( .CVA6Cfg (CVA6Cfg), + .icache_arsp_t (icache_arsp_t), .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES), .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) @@ -210,6 +212,7 @@ module load_store_unit end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32 cva6_mmu_sv32 #( .CVA6Cfg (CVA6Cfg), + .icache_arsp_t (icache_arsp_t), .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES), .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 9c98793da4..757f44ec73 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -30,6 +30,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 2, parameter int unsigned DATA_TLB_ENTRIES = 2, parameter int unsigned ASID_WIDTH = 1 diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index 56994f260d..fbb57a15d5 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -19,6 +19,7 @@ module mmu import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_arsp_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 From 2be559b88caeb928df166e28e220f72d9b4910c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Mon, 13 Nov 2023 14:37:17 +0100 Subject: [PATCH 17/28] move icache_dreq_t & icache_drsp_t --- .../cva6_hpdcache_subsystem.sv | 8 +++-- core/cache_subsystem/cva6_icache.sv | 2 ++ .../cva6_icache_axi_wrapper.sv | 4 +++ core/cache_subsystem/std_cache_subsystem.sv | 4 +++ core/cache_subsystem/wt_cache_subsystem.sv | 4 +++ core/cva6.sv | 30 ++++++++++++++++++- core/ex_stage.sv | 4 +++ core/frontend/frontend.sv | 4 ++- core/include/ariane_pkg.sv | 18 ----------- core/load_store_unit.sv | 6 ++++ core/mmu_sv32/cva6_mmu_sv32.sv | 2 ++ core/mmu_sv39/mmu.sv | 2 ++ core/perf_counters.sv | 1 + 13 files changed, 67 insertions(+), 22 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 870165ef62..ee432f29f0 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -18,6 +18,8 @@ module cva6_hpdcache_subsystem #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter int NumPorts = 4, parameter int NrHwPrefetchers = 4, // AXI types @@ -48,8 +50,8 @@ module cva6_hpdcache_subsystem input ariane_pkg::icache_areq_t icache_areq_i, // to/from frontend output icache_arsp_t icache_areq_o, // data requests - input ariane_pkg::icache_dreq_t icache_dreq_i, // to/from frontend - output ariane_pkg::icache_drsp_t icache_dreq_o, + input icache_dreq_t icache_dreq_i, // to/from frontend + output icache_drsp_t icache_dreq_o, // }}} // D$ @@ -107,6 +109,8 @@ module cva6_hpdcache_subsystem cva6_icache #( .CVA6Cfg(CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .RdTxId (ICACHE_RDTXID) ) i_cva6_icache ( .clk_i (clk_i), diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 982554bfd0..02ddf89876 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -31,6 +31,8 @@ module cva6_icache #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, /// ID to be used for read transactions parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0 ) ( diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index ce4f38ecd8..bd024159d6 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -19,6 +19,8 @@ module cva6_icache_axi_wrapper #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( @@ -104,6 +106,8 @@ module cva6_icache_axi_wrapper // use ID 0 for icache reads .CVA6Cfg(CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .RdTxId(0) ) i_cva6_icache ( .clk_i (clk_i), diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 0bb0a559be..f910c9c782 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -21,6 +21,8 @@ module std_cache_subsystem #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter int unsigned NumPorts = 4, parameter type axi_ar_chan_t = logic, parameter type axi_aw_chan_t = logic, @@ -71,6 +73,8 @@ module std_cache_subsystem cva6_icache_axi_wrapper #( .CVA6Cfg (CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t) ) i_cva6_icache_axi_wrapper ( diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index 29aeba07df..44dfa2ccfc 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -25,6 +25,8 @@ module wt_cache_subsystem #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter int unsigned NumPorts = 4, parameter type noc_req_t = logic, parameter type noc_resp_t = logic @@ -81,6 +83,8 @@ module wt_cache_subsystem // use ID 0 for icache reads .CVA6Cfg(CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .RdTxId(0) ) i_cva6_icache ( .clk_i (clk_i), diff --git a/core/cva6.sv b/core/cva6.sv index d41265e028..c19824f835 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -35,6 +35,23 @@ module cva6 logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out }, + // I$ data requests + parameter type icache_dreq_t = struct packed { + logic req; // we request a new word + logic kill_s1; // kill the current request + logic kill_s2; // kill the last request + logic spec; // request is speculative + logic [riscv::VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup + }, + parameter type icache_drsp_t = struct packed { + logic ready; // icache is ready + logic valid; // signals a valid read + logic [ariane_pkg::FETCH_WIDTH-1:0] data; // 2+ cycle out: tag + logic [ariane_pkg::FETCH_USER_WIDTH-1:0] user; // User bits + logic [riscv::VLEN-1:0] vaddr; // virtual address out + exception_t ex; // we've encountered an exception + }, + // IF/ID Stage // store the decompressed instruction parameter type fetch_entry_t = struct packed { @@ -458,7 +475,9 @@ module cva6 frontend #( .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), - .fetch_entry_t(fetch_entry_t) + .fetch_entry_t(fetch_entry_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t) ) i_frontend ( .flush_i (flush_ctrl_if), // not entirely correct .flush_bp_i (1'b0), @@ -670,6 +689,8 @@ module cva6 .branchpredict_sbe_t(branchpredict_sbe_t), .fu_data_t(fu_data_t), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .lsu_ctrl_t(lsu_ctrl_t), .ASID_WIDTH(ASID_WIDTH) ) ex_stage_i ( @@ -898,6 +919,7 @@ module cva6 .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t), + .icache_dreq_t(icache_dreq_t), .NumPorts(NumPorts) ) perf_counters_i ( .clk_i (clk_i), @@ -1003,6 +1025,8 @@ module cva6 wt_cache_subsystem #( .CVA6Cfg (CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .NumPorts (NumPorts), .noc_req_t (noc_req_t), .noc_resp_t(noc_resp_t) @@ -1044,6 +1068,8 @@ module cva6 cva6_hpdcache_subsystem #( .CVA6Cfg (CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .NumPorts (NumPorts), .axi_ar_chan_t(axi_ar_chan_t), .axi_aw_chan_t(axi_aw_chan_t), @@ -1105,6 +1131,8 @@ module cva6 // deprecated .CVA6Cfg (CVA6Cfg), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .NumPorts (NumPorts), .axi_ar_chan_t(axi_ar_chan_t), .axi_aw_chan_t(axi_aw_chan_t), diff --git a/core/ex_stage.sv b/core/ex_stage.sv index b83a92979d..939e440bd7 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -22,6 +22,8 @@ module ex_stage parameter type branchpredict_sbe_t = logic, parameter type fu_data_t = logic, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter type lsu_ctrl_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( @@ -377,6 +379,8 @@ module ex_stage .CVA6Cfg (CVA6Cfg), .fu_data_t (fu_data_t), .icache_arsp_t(icache_arsp_t), + .icache_dreq_t(icache_dreq_t), + .icache_drsp_t(icache_drsp_t), .lsu_ctrl_t(lsu_ctrl_t), .ASID_WIDTH(ASID_WIDTH) ) lsu_i ( diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index c13226660e..8e0f822792 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -20,7 +20,9 @@ module frontend #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, - parameter type fetch_entry_t = logic + parameter type fetch_entry_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic ) ( // Subsystem Clock - SUBSYSTEM input logic clk_i, diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index eef14b90d6..2a72796309 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -656,24 +656,6 @@ package ariane_pkg; exception_t fetch_exception; // exception occurred during fetch } icache_areq_t; - // I$ data requests - typedef struct packed { - logic req; // we request a new word - logic kill_s1; // kill the current request - logic kill_s2; // kill the last request - logic spec; // request is speculative - logic [riscv::VLEN-1:0] vaddr; // 1st cycle: 12 bit index is taken for lookup - } icache_dreq_t; - - typedef struct packed { - logic ready; // icache is ready - logic valid; // signals a valid read - logic [FETCH_WIDTH-1:0] data; // 2+ cycle out: tag - logic [FETCH_USER_WIDTH-1:0] user; // User bits - logic [riscv::VLEN-1:0] vaddr; // virtual address out - exception_t ex; // we've encountered an exception - } icache_drsp_t; - // AMO request going to cache. this request is unconditionally valid as soon // as request goes high. // Furthermore, those signals are kept stable until the response indicates diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 86fa6cf6af..94be59a09f 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -19,6 +19,8 @@ module load_store_unit parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type fu_data_t = logic, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter type lsu_ctrl_t = logic, parameter int unsigned ASID_WIDTH = 1 ) ( @@ -183,6 +185,8 @@ module load_store_unit mmu #( .CVA6Cfg (CVA6Cfg), .icache_arsp_t (icache_arsp_t), + .icache_dreq_t (icache_dreq_t), + .icache_drsp_t (icache_drsp_t), .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES), .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) @@ -213,6 +217,8 @@ module load_store_unit cva6_mmu_sv32 #( .CVA6Cfg (CVA6Cfg), .icache_arsp_t (icache_arsp_t), + .icache_dreq_t (icache_dreq_t), + .icache_drsp_t (icache_drsp_t), .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES), .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 757f44ec73..1447b9dd53 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -31,6 +31,8 @@ module cva6_mmu_sv32 #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 2, parameter int unsigned DATA_TLB_ENTRIES = 2, parameter int unsigned ASID_WIDTH = 1 diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index fbb57a15d5..6ffe8f4022 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -20,6 +20,8 @@ module mmu #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 diff --git a/core/perf_counters.sv b/core/perf_counters.sv index f62de00188..18e624d817 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -18,6 +18,7 @@ module perf_counters #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, + parameter type icache_dreq_t = logic, parameter type scoreboard_entry_t = logic, parameter int unsigned NumPorts = 3 // number of miss ports ) ( From 5f120defd3e6b131bda408f8ebfca8545da2bdbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Mon, 13 Nov 2023 15:58:40 +0100 Subject: [PATCH 18/28] move dcache_req_i_t & dcache_req_o_t --- core/acc_dispatcher.sv | 2 ++ core/cache_subsystem/cache_ctrl.sv | 4 ++- .../cva6_hpdcache_if_adapter.sv | 6 ++-- .../cva6_hpdcache_subsystem.sv | 12 +++++-- core/cache_subsystem/std_cache_subsystem.sv | 4 +++ core/cache_subsystem/std_nbdcache.sv | 6 +++- core/cache_subsystem/wt_cache_subsystem.sv | 4 +++ core/cache_subsystem/wt_dcache.sv | 8 ++++- core/cache_subsystem/wt_dcache_ctrl.sv | 2 ++ core/cache_subsystem/wt_dcache_wbuffer.sv | 4 ++- core/cva6.sv | 35 +++++++++++++++++++ core/ex_stage.sv | 4 +++ core/include/ariane_pkg.sv | 23 ------------ core/load_store_unit.sv | 10 ++++++ core/load_unit.sv | 2 ++ core/mmu_sv32/cva6_mmu_sv32.sv | 4 +++ core/mmu_sv32/cva6_ptw_sv32.sv | 2 ++ core/mmu_sv39/mmu.sv | 4 +++ core/mmu_sv39/ptw.sv | 2 ++ core/perf_counters.sv | 2 ++ core/store_buffer.sv | 4 ++- core/store_unit.sv | 6 +++- 22 files changed, 116 insertions(+), 34 deletions(-) diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 0aeef88364..66972dcd64 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -18,6 +18,8 @@ module acc_dispatcher import riscv::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic, localparam type accelerator_req_t = struct packed { diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv index e8770d2046..c3e2eee009 100644 --- a/core/cache_subsystem/cache_ctrl.sv +++ b/core/cache_subsystem/cache_ctrl.sv @@ -22,7 +22,9 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index f3a1d2e040..fc8d1ce93d 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -16,6 +16,8 @@ module cva6_hpdcache_if_adapter // {{{ #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter bit is_load_port = 1'b1 ) // }}} @@ -31,8 +33,8 @@ module cva6_hpdcache_if_adapter input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i, // Request/response ports from/to the CVA6 core - input ariane_pkg::dcache_req_i_t cva6_req_i, - output ariane_pkg::dcache_req_o_t cva6_req_o, + input dcache_req_i_t cva6_req_i, + output dcache_req_o_t cva6_req_o, input ariane_pkg::amo_req_t cva6_amo_req_i, output ariane_pkg::amo_resp_t cva6_amo_resp_o, diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index ee432f29f0..5170a8b687 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -20,6 +20,8 @@ module cva6_hpdcache_subsystem parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int NumPorts = 4, parameter int NrHwPrefetchers = 4, // AXI types @@ -69,8 +71,8 @@ module cva6_hpdcache_subsystem input cmo_req_t dcache_cmo_req_i, // from CMO FU output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU // Request ports - input ariane_pkg::dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU - output ariane_pkg::dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU // Write Buffer status output logic wbuffer_empty_o, output logic wbuffer_not_ni_o, @@ -218,13 +220,15 @@ module cva6_hpdcache_subsystem hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_out; generate - ariane_pkg::dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0]; + dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0]; for (genvar r = 0; r < (NumPorts - 1); r++) begin : cva6_hpdcache_load_if_adapter_gen assign dcache_req_ports[r] = dcache_req_ports_i[r]; cva6_hpdcache_if_adapter #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .is_load_port(1'b1) ) i_cva6_hpdcache_load_if_adapter ( .clk_i, @@ -251,6 +255,8 @@ module cva6_hpdcache_subsystem cva6_hpdcache_if_adapter #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .is_load_port(1'b0) ) i_cva6_hpdcache_store_if_adapter ( .clk_i, diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index f910c9c782..c43a49d221 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -23,6 +23,8 @@ module std_cache_subsystem parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int unsigned NumPorts = 4, parameter type axi_ar_chan_t = logic, parameter type axi_aw_chan_t = logic, @@ -99,6 +101,8 @@ module std_cache_subsystem // Port 3: Store Unit std_nbdcache #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t) diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index 367c67cb5d..f5de333708 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -18,6 +18,8 @@ module std_nbdcache import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int unsigned NumPorts = 4, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic @@ -95,7 +97,9 @@ module std_nbdcache generate for (genvar i = 0; i < NumPorts; i++) begin : master_ports cache_ctrl #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t) ) i_cache_ctrl ( .bypass_i (~enable_i), .busy_o (busy[i]), diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index 44dfa2ccfc..e5123c2919 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -27,6 +27,8 @@ module wt_cache_subsystem parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int unsigned NumPorts = 4, parameter type noc_req_t = logic, parameter type noc_resp_t = logic @@ -110,6 +112,8 @@ module wt_cache_subsystem // Port 2 is write only and goes into the merging write buffer wt_dcache #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), // use ID 1 for dcache reads and amos. note that the writebuffer // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. .RdAmoTxId(1) diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index e1aa193cf1..1ff99cb2f9 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -18,6 +18,8 @@ module wt_dcache import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int unsigned NumPorts = 4, // number of miss ports // ID to be used for read and AMO transactions. // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions @@ -175,6 +177,8 @@ module wt_dcache assign rd_prio[k] = 1'b1; wt_dcache_ctrl #( .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .RdTxId (RdAmoTxId) ) i_wt_dcache_ctrl ( .clk_i (clk_i), @@ -238,7 +242,9 @@ module wt_dcache assign rd_prio[NumPorts-1] = 1'b0; wt_dcache_wbuffer #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t) ) i_wt_dcache_wbuffer ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/cache_subsystem/wt_dcache_ctrl.sv b/core/cache_subsystem/wt_dcache_ctrl.sv index b5973df195..ad76083d67 100644 --- a/core/cache_subsystem/wt_dcache_ctrl.sv +++ b/core/cache_subsystem/wt_dcache_ctrl.sv @@ -18,6 +18,8 @@ module wt_dcache_ctrl import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1 ) ( input logic clk_i, // Clock diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index c46abf0590..5597de1192 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -53,7 +53,9 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/cva6.sv b/core/cva6.sv index c19824f835..4691a9f2de 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -129,6 +129,29 @@ module cva6 logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; }, + // D$ data requests + parameter type dcache_req_i_t = struct packed { + logic [DCACHE_INDEX_WIDTH-1:0] address_index; + logic [DCACHE_TAG_WIDTH-1:0] address_tag; + logic [riscv::XLEN-1:0] data_wdata; + logic [DCACHE_USER_WIDTH-1:0] data_wuser; + logic data_req; + logic data_we; + logic [(riscv::XLEN/8)-1:0] data_be; + logic [1:0] data_size; + logic [DCACHE_TID_WIDTH-1:0] data_id; + logic kill_req; + logic tag_valid; + }, + + parameter type dcache_req_o_t = struct packed { + logic data_gnt; + logic data_rvalid; + logic [DCACHE_TID_WIDTH-1:0] data_rid; + logic [riscv::XLEN-1:0] data_rdata; + logic [DCACHE_USER_WIDTH-1:0] data_ruser; + }, + parameter type rvfi_probes_t = struct packed { logic csr; //disabled rvfi_probes_instr_t instr; @@ -687,6 +710,8 @@ module cva6 .CVA6Cfg (CVA6Cfg), .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .fu_data_t(fu_data_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), @@ -920,6 +945,8 @@ module cva6 .bp_resolve_t(bp_resolve_t), .scoreboard_entry_t(scoreboard_entry_t), .icache_dreq_t(icache_dreq_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .NumPorts(NumPorts) ) perf_counters_i ( .clk_i (clk_i), @@ -1027,6 +1054,8 @@ module cva6 .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), .noc_req_t (noc_req_t), .noc_resp_t(noc_resp_t) @@ -1070,6 +1099,8 @@ module cva6 .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), .axi_ar_chan_t(axi_ar_chan_t), .axi_aw_chan_t(axi_aw_chan_t), @@ -1133,6 +1164,8 @@ module cva6 .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), .axi_ar_chan_t(axi_ar_chan_t), .axi_aw_chan_t(axi_aw_chan_t), @@ -1181,6 +1214,8 @@ module cva6 acc_dispatcher #( .CVA6Cfg (CVA6Cfg), .fu_data_t (fu_data_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), .scoreboard_entry_t(scoreboard_entry_t), .acc_cfg_t (acc_cfg_t), .AccCfg (AccCfg), diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 939e440bd7..887d574d2f 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -20,6 +20,8 @@ module ex_stage parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter type fu_data_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, @@ -377,6 +379,8 @@ module ex_stage load_store_unit #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .fu_data_t (fu_data_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 2a72796309..367066f7c0 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -674,29 +674,6 @@ package ariane_pkg; logic [63:0] result; // sign-extended, result } amo_resp_t; - // D$ data requests - typedef struct packed { - logic [DCACHE_INDEX_WIDTH-1:0] address_index; - logic [DCACHE_TAG_WIDTH-1:0] address_tag; - riscv::xlen_t data_wdata; - logic [DCACHE_USER_WIDTH-1:0] data_wuser; - logic data_req; - logic data_we; - logic [(riscv::XLEN/8)-1:0] data_be; - logic [1:0] data_size; - logic [DCACHE_TID_WIDTH-1:0] data_id; - logic kill_req; - logic tag_valid; - } dcache_req_i_t; - - typedef struct packed { - logic data_gnt; - logic data_rvalid; - logic [DCACHE_TID_WIDTH-1:0] data_rid; - riscv::xlen_t data_rdata; - logic [DCACHE_USER_WIDTH-1:0] data_ruser; - } dcache_req_o_t; - // RVFI instr typedef struct packed { logic [TRANS_ID_BITS-1:0] issue_pointer; diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 94be59a09f..d40d288bdd 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -17,6 +17,8 @@ module load_store_unit import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter type fu_data_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, @@ -187,6 +189,8 @@ module load_store_unit .icache_arsp_t (icache_arsp_t), .icache_dreq_t (icache_dreq_t), .icache_drsp_t (icache_drsp_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES), .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) @@ -219,6 +223,8 @@ module load_store_unit .icache_arsp_t (icache_arsp_t), .icache_dreq_t (icache_dreq_t), .icache_drsp_t (icache_drsp_t), + .dcache_req_i_t (dcache_req_i_t), + .dcache_req_o_t (dcache_req_o_t), .INSTR_TLB_ENTRIES(ariane_pkg::INSTR_TLB_ENTRIES), .DATA_TLB_ENTRIES (ariane_pkg::DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) @@ -294,6 +300,8 @@ module load_store_unit // ------------------ store_unit #( .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .lsu_ctrl_t(lsu_ctrl_t) ) i_store_unit ( .clk_i, @@ -337,6 +345,8 @@ module load_store_unit // ------------------ load_unit #( .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .lsu_ctrl_t(lsu_ctrl_t) ) i_load_unit ( .valid_i (ld_valid_i), diff --git a/core/load_unit.sv b/core/load_unit.sv index ec2963d477..0814c71fab 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -22,6 +22,8 @@ module load_unit import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 1447b9dd53..49f5d9411b 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -33,6 +33,8 @@ module cva6_mmu_sv32 parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 2, parameter int unsigned DATA_TLB_ENTRIES = 2, parameter int unsigned ASID_WIDTH = 1 @@ -202,6 +204,8 @@ module cva6_mmu_sv32 cva6_ptw_sv32 #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .ASID_WIDTH(ASID_WIDTH) ) i_ptw ( .clk_i (clk_i), diff --git a/core/mmu_sv32/cva6_ptw_sv32.sv b/core/mmu_sv32/cva6_ptw_sv32.sv index 4bd736bd30..6b6ed41b3c 100644 --- a/core/mmu_sv32/cva6_ptw_sv32.sv +++ b/core/mmu_sv32/cva6_ptw_sv32.sv @@ -30,6 +30,8 @@ module cva6_ptw_sv32 import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int ASID_WIDTH = 1 ) ( input logic clk_i, // Clock diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index 6ffe8f4022..fd489c1793 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -22,6 +22,8 @@ module mmu parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 @@ -149,6 +151,8 @@ module mmu ptw #( .CVA6Cfg (CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t), .ASID_WIDTH(ASID_WIDTH) ) i_ptw ( .clk_i (clk_i), diff --git a/core/mmu_sv39/ptw.sv b/core/mmu_sv39/ptw.sv index 2d0e3780ac..730e723835 100644 --- a/core/mmu_sv39/ptw.sv +++ b/core/mmu_sv39/ptw.sv @@ -19,6 +19,8 @@ module ptw import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter int ASID_WIDTH = 1 ) ( input logic clk_i, // Clock diff --git a/core/perf_counters.sv b/core/perf_counters.sv index 18e624d817..abef4c36bf 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -18,6 +18,8 @@ module perf_counters #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter type icache_dreq_t = logic, parameter type scoreboard_entry_t = logic, parameter int unsigned NumPorts = 3 // number of miss ports diff --git a/core/store_buffer.sv b/core/store_buffer.sv index d41551d555..f2cd09f70c 100644 --- a/core/store_buffer.sv +++ b/core/store_buffer.sv @@ -17,7 +17,9 @@ module store_buffer import ariane_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/store_unit.sv b/core/store_unit.sv index 618e12b470..b6d3342256 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -17,6 +17,8 @@ module store_unit import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -248,7 +250,9 @@ module store_unit // Store Queue // --------------- store_buffer #( - .CVA6Cfg(CVA6Cfg) + .CVA6Cfg(CVA6Cfg), + .dcache_req_i_t(dcache_req_i_t), + .dcache_req_o_t(dcache_req_o_t) ) store_buffer_i ( .clk_i, .rst_ni, From 54f9c39772b989addcad66f6acf152f8e14d46e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Tue, 14 Nov 2023 10:35:45 +0100 Subject: [PATCH 19/28] move icache_areq_t --- core/cache_subsystem/cva6_hpdcache_subsystem.sv | 4 +++- core/cache_subsystem/cva6_icache.sv | 1 + core/cache_subsystem/cva6_icache_axi_wrapper.sv | 2 ++ core/cache_subsystem/std_cache_subsystem.sv | 2 ++ core/cache_subsystem/wt_cache_subsystem.sv | 2 ++ core/cva6.sv | 10 ++++++++++ core/ex_stage.sv | 2 ++ core/include/ariane_pkg.sv | 10 ---------- core/load_store_unit.sv | 3 +++ core/mmu_sv32/cva6_mmu_sv32.sv | 1 + core/mmu_sv39/mmu.sv | 1 + 11 files changed, 27 insertions(+), 11 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 5170a8b687..d222e2e986 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -17,6 +17,7 @@ module cva6_hpdcache_subsystem // {{{ #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, @@ -49,7 +50,7 @@ module cva6_hpdcache_subsystem input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together output logic icache_miss_o, // to performance counter // address translation requests - input ariane_pkg::icache_areq_t icache_areq_i, // to/from frontend + input icache_areq_t icache_areq_i, // to/from frontend output icache_arsp_t icache_areq_o, // data requests input icache_dreq_t icache_dreq_i, // to/from frontend @@ -110,6 +111,7 @@ module cva6_hpdcache_subsystem cva6_icache #( .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 02ddf89876..2b2a1d465c 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -30,6 +30,7 @@ module cva6_icache import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index bd024159d6..cb2d799cdc 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -18,6 +18,7 @@ module cva6_icache_axi_wrapper import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, @@ -105,6 +106,7 @@ module cva6_icache_axi_wrapper cva6_icache #( // use ID 0 for icache reads .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index c43a49d221..e756366f2a 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -20,6 +20,7 @@ module std_cache_subsystem import std_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, @@ -74,6 +75,7 @@ module std_cache_subsystem cva6_icache_axi_wrapper #( .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index e5123c2919..b89ad6bb73 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -24,6 +24,7 @@ module wt_cache_subsystem import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, @@ -84,6 +85,7 @@ module wt_cache_subsystem cva6_icache #( // use ID 0 for icache reads .CVA6Cfg(CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), diff --git a/core/cva6.sv b/core/cva6.sv index 4691a9f2de..f03c681f08 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -30,6 +30,12 @@ module cva6 }, // cache request ports + // I$ address translation requests + parameter type icache_areq_t = struct packed { + logic fetch_valid; // address translation valid + logic [riscv::PLEN-1:0] fetch_paddr; // physical address in + exception_t fetch_exception; // exception occurred during fetch + }, parameter type icache_arsp_t = struct packed { logic fetch_req; // address translation request logic [riscv::VLEN-1:0] fetch_vaddr; // virtual address out @@ -713,6 +719,7 @@ module cva6 .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .fu_data_t(fu_data_t), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), @@ -1051,6 +1058,7 @@ module cva6 // this is a cache subsystem that is compatible with OpenPiton wt_cache_subsystem #( .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), @@ -1096,6 +1104,7 @@ module cva6 end else if (DCACHE_TYPE == int'(config_pkg::HPDCACHE)) begin : gen_cache_hpd cva6_hpdcache_subsystem #( .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), @@ -1161,6 +1170,7 @@ module cva6 // not as important since this cache subsystem is about to be // deprecated .CVA6Cfg (CVA6Cfg), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 887d574d2f..38a984b24d 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -23,6 +23,7 @@ module ex_stage parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter type fu_data_t = logic, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, @@ -382,6 +383,7 @@ module ex_stage .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .fu_data_t (fu_data_t), + .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 367066f7c0..01b6367a49 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -646,16 +646,6 @@ package ariane_pkg; FE_INSTR_PAGE_FAULT } frontend_exception_t; - // ---------------------- - // cache request ports - // ---------------------- - // I$ address translation requests - typedef struct packed { - logic fetch_valid; // address translation valid - logic [riscv::PLEN-1:0] fetch_paddr; // physical address in - exception_t fetch_exception; // exception occurred during fetch - } icache_areq_t; - // AMO request going to cache. this request is unconditionally valid as soon // as request goes high. // Furthermore, those signals are kept stable until the response indicates diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index d40d288bdd..0a100b658e 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -20,6 +20,7 @@ module load_store_unit parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter type fu_data_t = logic, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, @@ -186,6 +187,7 @@ module load_store_unit if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39 mmu #( .CVA6Cfg (CVA6Cfg), + .icache_areq_t (icache_areq_t), .icache_arsp_t (icache_arsp_t), .icache_dreq_t (icache_dreq_t), .icache_drsp_t (icache_drsp_t), @@ -220,6 +222,7 @@ module load_store_unit end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32 cva6_mmu_sv32 #( .CVA6Cfg (CVA6Cfg), + .icache_areq_t (icache_areq_t), .icache_arsp_t (icache_arsp_t), .icache_dreq_t (icache_dreq_t), .icache_drsp_t (icache_drsp_t), diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 49f5d9411b..4a0518bf67 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -30,6 +30,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index fd489c1793..b3dcb8f795 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -19,6 +19,7 @@ module mmu import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, From 25aa1957d801d9c2cb77849aab566dced9dad0f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Tue, 14 Nov 2023 15:06:26 +0100 Subject: [PATCH 20/28] move tlb_update_t --- core/include/ariane_pkg.sv | 9 --------- core/mmu_sv39/mmu.sv | 12 ++++++++++++ core/mmu_sv39/ptw.sv | 1 + core/mmu_sv39/tlb.sv | 1 + 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 01b6367a49..8895f59137 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -619,15 +619,6 @@ package ariane_pkg; AMO_CAS2 = 4'b1101 // unused, not part of riscv spec, but provided in OpenPiton } amo_t; - typedef struct packed { - logic valid; // valid flag - logic is_2M; // - logic is_1G; // - logic [27-1:0] vpn; // VPN (39bits) = 27bits + 12bits offset - logic [ASID_WIDTH-1:0] asid; - riscv::pte_t content; - } tlb_update_t; - // Bits required for representation of physical address space as 4K pages // (e.g. 27*4K == 39bit address space). localparam PPN4K_WIDTH = 38; diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index b3dcb8f795..515e2e7341 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -74,6 +74,15 @@ module mmu input logic [15:0][riscv::PLEN-3:0] pmpaddr_i ); + localparam type tlb_update_t = struct packed { + logic valid; // valid flag + logic is_2M; // + logic is_1G; // + logic [27-1:0] vpn; // VPN (39bits) = 27bits + 12bits offset + logic [ASID_WIDTH-1:0] asid; + riscv::pte_t content; + }; + logic iaccess_err; // insufficient privilege to access this instruction page logic daccess_err; // insufficient privilege to access this data page logic ptw_active; // PTW is currently walking a page table @@ -105,6 +114,7 @@ module mmu tlb #( .CVA6Cfg (CVA6Cfg), + .tlb_update_t(tlb_update_t), .TLB_ENTRIES(INSTR_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) ) i_itlb ( @@ -128,6 +138,7 @@ module mmu tlb #( .CVA6Cfg (CVA6Cfg), + .tlb_update_t(tlb_update_t), .TLB_ENTRIES(DATA_TLB_ENTRIES), .ASID_WIDTH (ASID_WIDTH) ) i_dtlb ( @@ -154,6 +165,7 @@ module mmu .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), + .tlb_update_t(tlb_update_t), .ASID_WIDTH(ASID_WIDTH) ) i_ptw ( .clk_i (clk_i), diff --git a/core/mmu_sv39/ptw.sv b/core/mmu_sv39/ptw.sv index 730e723835..27c1346f21 100644 --- a/core/mmu_sv39/ptw.sv +++ b/core/mmu_sv39/ptw.sv @@ -21,6 +21,7 @@ module ptw parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type tlb_update_t = logic, parameter int ASID_WIDTH = 1 ) ( input logic clk_i, // Clock diff --git a/core/mmu_sv39/tlb.sv b/core/mmu_sv39/tlb.sv index 3df2cb0173..06d10d81ef 100644 --- a/core/mmu_sv39/tlb.sv +++ b/core/mmu_sv39/tlb.sv @@ -19,6 +19,7 @@ module tlb import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type tlb_update_t = logic, parameter int unsigned TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 ) ( From 457acefff63e7aaede4a1d36887dcee4e9199ae5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 23 Nov 2023 11:45:48 +0100 Subject: [PATCH 21/28] move cache_line_t & cl_be_t --- core/cache_subsystem/cache_ctrl.sv | 2 ++ core/cache_subsystem/miss_handler.sv | 4 +++- core/cache_subsystem/std_nbdcache.sv | 20 +++++++++++++++++++- core/cache_subsystem/tag_cmp.sv | 4 ++-- core/include/std_cache_pkg.sv | 14 -------------- 5 files changed, 26 insertions(+), 18 deletions(-) diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv index c3e2eee009..70ff5c3da6 100644 --- a/core/cache_subsystem/cache_ctrl.sv +++ b/core/cache_subsystem/cache_ctrl.sv @@ -23,6 +23,8 @@ module cache_ctrl import std_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type cache_line_t = logic, + parameter type cl_be_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic ) ( diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index b78cd395d0..ff977b8e15 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -23,7 +23,9 @@ module miss_handler parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_PORTS = 4, parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic + parameter type axi_rsp_t = logic, + parameter type cache_line_t = logic, + parameter type cl_be_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index f5de333708..f2e71fdaf8 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -46,6 +46,18 @@ module std_nbdcache import std_cache_pkg::*; + localparam type cache_line_t = struct packed { + logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag; // tag array + logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // data array + logic valid; // state array + logic dirty; // state array + }; + localparam type cl_be_t = struct packed { + logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array + logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array + logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits) + }; + // ------------------------------- // Controller <-> Arbiter // ------------------------------- @@ -98,6 +110,8 @@ module std_nbdcache for (genvar i = 0; i < NumPorts; i++) begin : master_ports cache_ctrl #( .CVA6Cfg(CVA6Cfg), + .cache_line_t(cache_line_t), + .cl_be_t(cl_be_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t) ) i_cache_ctrl ( @@ -141,7 +155,9 @@ module std_nbdcache .CVA6Cfg (CVA6Cfg), .NR_PORTS (NumPorts), .axi_req_t(axi_req_t), - .axi_rsp_t(axi_rsp_t) + .axi_rsp_t(axi_rsp_t), + .cache_line_t(cache_line_t), + .cl_be_t(cl_be_t) ) i_miss_handler ( .flush_i (flush_i), .busy_i (|busy), @@ -252,6 +268,8 @@ module std_nbdcache .CVA6Cfg (CVA6Cfg), .NR_PORTS (NumPorts + 1), .ADDR_WIDTH (DCACHE_INDEX_WIDTH), + .l_data_t (cache_line_t), + .l_be_t (cl_be_t), .DCACHE_SET_ASSOC(DCACHE_SET_ASSOC) ) i_tag_cmp ( .req_i (req), diff --git a/core/cache_subsystem/tag_cmp.sv b/core/cache_subsystem/tag_cmp.sv index a378c13b11..f5d2d9e816 100644 --- a/core/cache_subsystem/tag_cmp.sv +++ b/core/cache_subsystem/tag_cmp.sv @@ -19,8 +19,8 @@ module tag_cmp #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_PORTS = 3, parameter int unsigned ADDR_WIDTH = 64, - parameter type l_data_t = std_cache_pkg::cache_line_t, - parameter type l_be_t = std_cache_pkg::cl_be_t, + parameter type l_data_t = logic, + parameter type l_be_t = logic, parameter int unsigned DCACHE_SET_ASSOC = 8 ) ( input logic clk_i, diff --git a/core/include/std_cache_pkg.sv b/core/include/std_cache_pkg.sv index ae812c9974..de1338fd2f 100644 --- a/core/include/std_cache_pkg.sv +++ b/core/include/std_cache_pkg.sv @@ -61,20 +61,6 @@ package std_cache_pkg; logic [63:0] rdata; } bypass_rsp_t; - typedef struct packed { - logic [ariane_pkg::DCACHE_TAG_WIDTH-1:0] tag; // tag array - logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // data array - logic valid; // state array - logic dirty; // state array - } cache_line_t; - - // cache line byte enable - typedef struct packed { - logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array - logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array - logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits) - } cl_be_t; - // convert one hot to bin for -> needed for cache replacement function automatic logic [DCACHE_SET_ASSOC_WIDTH-1:0] one_hot_to_bin( input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] in); From ea5e8cde012d8192e4fd00c7235a8f1f854aabab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Thu, 23 Nov 2023 15:55:52 +0100 Subject: [PATCH 22/28] move icache_{req,rtrn}_t, inline icache_inval_t --- .../cva6_hpdcache_subsystem.sv | 10 ++++++-- .../cva6_hpdcache_subsystem_axi_arbiter.sv | 6 +++-- core/cache_subsystem/cva6_icache.sv | 2 ++ .../cva6_icache_axi_wrapper.sv | 4 +++ core/cache_subsystem/std_cache_subsystem.sv | 4 +++ core/cache_subsystem/wt_axi_adapter.sv | 4 ++- core/cache_subsystem/wt_cache_subsystem.sv | 14 ++++++++--- core/cache_subsystem/wt_l15_adapter.sv | 4 ++- core/cva6.sv | 25 +++++++++++++++++++ core/include/wt_cache_pkg.sv | 23 ----------------- 10 files changed, 64 insertions(+), 32 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index d222e2e986..0802ba88ca 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -21,6 +21,8 @@ module cva6_hpdcache_subsystem parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter int NumPorts = 4, @@ -102,10 +104,10 @@ module cva6_hpdcache_subsystem // I$ instantiation // {{{ logic icache_miss_valid, icache_miss_ready; - wt_cache_pkg::icache_req_t icache_miss; + icache_req_t icache_miss; logic icache_miss_resp_valid; - wt_cache_pkg::icache_rtrn_t icache_miss_resp; + icache_rtrn_t icache_miss_resp; localparam int ICACHE_RDTXID = 1 << (ariane_pkg::MEM_TID_WIDTH - 1); @@ -115,6 +117,8 @@ module cva6_hpdcache_subsystem .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), .RdTxId (ICACHE_RDTXID) ) i_cva6_icache ( .clk_i (clk_i), @@ -494,6 +498,8 @@ module cva6_hpdcache_subsystem .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t), .hpdcache_mem_resp_w_t(hpdcache_mem_resp_w_t), + .icache_req_t (icache_req_t), + .icache_rtrn_t (icache_rtrn_t), .AxiAddrWidth (CVA6Cfg.AxiAddrWidth), .AxiDataWidth (CVA6Cfg.AxiDataWidth), diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv index 5a185c40db..88728a0e0d 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv @@ -22,6 +22,8 @@ module cva6_hpdcache_subsystem_axi_arbiter parameter type hpdcache_mem_req_w_t = logic, parameter type hpdcache_mem_resp_r_t = logic, parameter type hpdcache_mem_resp_w_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, parameter int unsigned AxiAddrWidth = 1, parameter int unsigned AxiDataWidth = 1, @@ -49,11 +51,11 @@ module cva6_hpdcache_subsystem_axi_arbiter // {{{ input logic icache_miss_valid_i, output logic icache_miss_ready_o, - input wt_cache_pkg::icache_req_t icache_miss_i, + input icache_req_t icache_miss_i, input hpdcache_mem_id_t icache_miss_id_i, output logic icache_miss_resp_valid_o, - output wt_cache_pkg::icache_rtrn_t icache_miss_resp_o, + output icache_rtrn_t icache_miss_resp_o, // }}} // Interfaces from/to D$ diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index 2b2a1d465c..3c7021a8fa 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -34,6 +34,8 @@ module cva6_icache parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, /// ID to be used for read transactions parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0 ) ( diff --git a/core/cache_subsystem/cva6_icache_axi_wrapper.sv b/core/cache_subsystem/cva6_icache_axi_wrapper.sv index cb2d799cdc..3557390cf5 100644 --- a/core/cache_subsystem/cva6_icache_axi_wrapper.sv +++ b/core/cache_subsystem/cva6_icache_axi_wrapper.sv @@ -22,6 +22,8 @@ module cva6_icache_axi_wrapper parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic ) ( @@ -110,6 +112,8 @@ module cva6_icache_axi_wrapper .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), .RdTxId(0) ) i_cva6_icache ( .clk_i (clk_i), diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index e756366f2a..3dbcf43075 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -24,6 +24,8 @@ module std_cache_subsystem parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter int unsigned NumPorts = 4, @@ -79,6 +81,8 @@ module std_cache_subsystem .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t) ) i_cva6_icache_axi_wrapper ( diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index e86fe02a9d..f167779577 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -22,7 +22,9 @@ module wt_axi_adapter parameter int unsigned ReqFifoDepth = 2, parameter int unsigned MetaFifoDepth = CVA6Cfg.DCACHE_MAX_TX, parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic + parameter type axi_rsp_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index b89ad6bb73..527356a3c2 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -30,6 +30,8 @@ module wt_cache_subsystem parameter type icache_drsp_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic, parameter int unsigned NumPorts = 4, parameter type noc_req_t = logic, parameter type noc_resp_t = logic @@ -74,8 +76,8 @@ module wt_cache_subsystem ); logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld; - wt_cache_pkg::icache_req_t icache_adapter; - wt_cache_pkg::icache_rtrn_t adapter_icache; + icache_req_t icache_adapter; + icache_rtrn_t adapter_icache; logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld; @@ -89,6 +91,8 @@ module wt_cache_subsystem .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), .RdTxId(0) ) i_cva6_icache ( .clk_i (clk_i), @@ -149,6 +153,8 @@ module wt_cache_subsystem `ifdef PITON_ARIANE wt_l15_adapter #( .CVA6Cfg(CVA6Cfg), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t) ) i_adapter ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -169,7 +175,9 @@ module wt_cache_subsystem wt_axi_adapter #( .CVA6Cfg (CVA6Cfg), .axi_req_t(noc_req_t), - .axi_rsp_t(noc_resp_t) + .axi_rsp_t(noc_resp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t) ) i_adapter ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/cache_subsystem/wt_l15_adapter.sv b/core/cache_subsystem/wt_l15_adapter.sv index 7634bf302a..2201985da6 100644 --- a/core/cache_subsystem/wt_l15_adapter.sv +++ b/core/cache_subsystem/wt_l15_adapter.sv @@ -53,7 +53,9 @@ module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_req_t = logic, + parameter type icache_rtrn_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cva6.sv b/core/cva6.sv index f03c681f08..10e2316eee 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -135,6 +135,25 @@ module cva6 logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id; }, + parameter type icache_req_t = struct packed { + logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace + logic [riscv::PLEN-1:0] paddr; // physical address + logic nc; // noncacheable + logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + }, + parameter type icache_rtrn_t = struct packed { + wt_cache_pkg::icache_in_t rtype; // see definitions above + logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width + logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user; // user bits + struct packed { + logic vld; // invalidate only affected way + logic all; // invalidate all ways + logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate + logic [wt_cache_pkg::L1I_WAY_WIDTH-1:0] way; // way to invalidate + } inv; // invalidation vector + logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + }, + // D$ data requests parameter type dcache_req_i_t = struct packed { logic [DCACHE_INDEX_WIDTH-1:0] address_index; @@ -1062,6 +1081,8 @@ module cva6 .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), @@ -1108,6 +1129,8 @@ module cva6 .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t(icache_req_t), + .icache_rtrn_t(icache_rtrn_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), @@ -1174,6 +1197,8 @@ module cva6 .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), .icache_drsp_t(icache_drsp_t), + .icache_req_t (icache_req_t), + .icache_rtrn_t (icache_rtrn_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .NumPorts (NumPorts), diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index ddc7efd3c3..7fa99fee43 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -109,29 +109,6 @@ package wt_cache_pkg; ICACHE_IFILL_ACK } icache_in_t; - // icache interface - typedef struct packed { - logic vld; // invalidate only affected way - logic all; // invalidate all ways - logic [ariane_pkg::ICACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate - logic [L1I_WAY_WIDTH-1:0] way; // way to invalidate - } icache_inval_t; - - typedef struct packed { - logic [$clog2(ariane_pkg::ICACHE_SET_ASSOC)-1:0] way; // way to replace - logic [riscv::PLEN-1:0] paddr; // physical address - logic nc; // noncacheable - logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) - } icache_req_t; - - typedef struct packed { - icache_in_t rtype; // see definitions above - logic [ariane_pkg::ICACHE_LINE_WIDTH-1:0] data; // full cache line width - logic [ariane_pkg::ICACHE_USER_LINE_WIDTH-1:0] user; // user bits - icache_inval_t inv; // invalidation vector - logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) - } icache_rtrn_t; - // dcache interface typedef struct packed { logic vld; // invalidate only affected way From f43a599556c2a4c9874ac6a27465c3af744d4215 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Mon, 4 Dec 2023 09:57:54 +0100 Subject: [PATCH 23/28] move exception_t --- common/local/util/instr_tracer_if.sv | 3 ++- core/acc_dispatcher.sv | 1 + core/branch_unit.sv | 3 ++- core/commit_stage.sv | 1 + core/csr_regfile.sv | 1 + core/cva6.sv | 16 ++++++++++++++++ core/cva6_rvfi_probes.sv | 1 + core/cvxif_fu.sv | 1 + core/decoder.sv | 1 + core/ex_stage.sv | 5 +++++ core/fpu_wrap.sv | 1 + core/id_stage.sv | 2 ++ core/include/ariane_pkg.sv | 9 --------- core/issue_stage.sv | 2 ++ core/load_store_unit.sv | 5 +++++ core/load_unit.sv | 1 + core/mmu_sv32/cva6_mmu_sv32.sv | 1 + core/mmu_sv39/mmu.sv | 1 + core/perf_counters.sv | 1 + core/scoreboard.sv | 3 ++- core/store_unit.sv | 1 + 21 files changed, 48 insertions(+), 12 deletions(-) diff --git a/common/local/util/instr_tracer_if.sv b/common/local/util/instr_tracer_if.sv index 42b2ff23c3..e7d7b4270c 100644 --- a/common/local/util/instr_tracer_if.sv +++ b/common/local/util/instr_tracer_if.sv @@ -18,6 +18,7 @@ interface instr_tracer_if #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, + parameter type exception_t = logic, parameter type scoreboard_entry_t = logic )( input clk @@ -52,7 +53,7 @@ interface instr_tracer_if #( // misprediction bp_resolve_t resolve_branch; // exceptions - ariane_pkg::exception_t exception; + exception_t exception; // current privilege level riscv::priv_lvl_t priv_lvl; logic debug_mode; diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 66972dcd64..bbc9ccc570 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -20,6 +20,7 @@ module acc_dispatcher parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic, localparam type accelerator_req_t = struct packed { diff --git a/core/branch_unit.sv b/core/branch_unit.sv index 2c5bb3f103..d839da1ef0 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -16,6 +16,7 @@ module branch_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -45,7 +46,7 @@ module branch_unit #( // Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE output logic resolve_branch_o, // Branch exception out - TO_BE_COMPLETED - output ariane_pkg::exception_t branch_exception_o + output exception_t branch_exception_o ); logic [riscv::VLEN-1:0] target_address; logic [riscv::VLEN-1:0] next_pc; diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 96a0860dde..29b5bb59bd 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -17,6 +17,7 @@ module commit_stage import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, parameter type scoreboard_entry_t = logic ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index fe679feef8..f8ee2598da 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -17,6 +17,7 @@ module csr_regfile import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, parameter type irq_ctrl_t = logic, parameter type scoreboard_entry_t = logic, parameter int AsidWidth = 1, diff --git a/core/cva6.sv b/core/cva6.sv index 10e2316eee..3ca2a0a18c 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -29,6 +29,13 @@ module cva6 logic [riscv::VLEN-1:0] predict_address; // target address at which to jump, or not }, + parameter type exception_t = struct packed { + logic [riscv::XLEN-1:0] cause; // cause of exception + logic [riscv::XLEN-1:0] tval; // additional information of causing exception (e.g.: instruction causing it), + // address of LD/ST fault + logic valid; + }, + // cache request ports // I$ address translation requests parameter type icache_areq_t = struct packed { @@ -554,6 +561,7 @@ module cva6 id_stage #( .CVA6Cfg(CVA6Cfg), .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), .fetch_entry_t(fetch_entry_t), .irq_ctrl_t(irq_ctrl_t), .scoreboard_entry_t(scoreboard_entry_t) @@ -658,6 +666,7 @@ module cva6 .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), .fu_data_t(fu_data_t), .scoreboard_entry_t(scoreboard_entry_t) ) issue_stage_i ( @@ -737,6 +746,7 @@ module cva6 .branchpredict_sbe_t(branchpredict_sbe_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), .fu_data_t(fu_data_t), .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), @@ -857,6 +867,7 @@ module cva6 commit_stage #( .CVA6Cfg(CVA6Cfg), + .exception_t(exception_t), .scoreboard_entry_t(scoreboard_entry_t) ) commit_stage_i ( .clk_i, @@ -897,6 +908,7 @@ module cva6 // --------- csr_regfile #( .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), .irq_ctrl_t (irq_ctrl_t), .scoreboard_entry_t(scoreboard_entry_t), .AsidWidth (ASID_WIDTH), @@ -969,6 +981,7 @@ module cva6 perf_counters #( .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), + .exception_t(exception_t), .scoreboard_entry_t(scoreboard_entry_t), .icache_dreq_t(icache_dreq_t), .dcache_req_i_t(dcache_req_i_t), @@ -1251,6 +1264,7 @@ module cva6 .fu_data_t (fu_data_t), .dcache_req_i_t (dcache_req_i_t), .dcache_req_o_t (dcache_req_o_t), + .exception_t (exception_t), .scoreboard_entry_t(scoreboard_entry_t), .acc_cfg_t (acc_cfg_t), .AccCfg (AccCfg), @@ -1385,6 +1399,7 @@ module cva6 instr_tracer_if #( .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), + .exception_t(exception_t), .scoreboard_entry_t(scoreboard_entry_t) ) tracer_if ( clk_i @@ -1496,6 +1511,7 @@ module cva6 cva6_rvfi_probes #( .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), .scoreboard_entry_t(scoreboard_entry_t), .lsu_ctrl_t (lsu_ctrl_t), .rvfi_probes_t(rvfi_probes_t) diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 1daa5c2e64..29e271eae5 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -13,6 +13,7 @@ module cva6_rvfi_probes import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, parameter type scoreboard_entry_t = logic, parameter type lsu_ctrl_t = logic, parameter type rvfi_probes_t = logic diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index f111282708..bbe2416e3e 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -14,6 +14,7 @@ module cvxif_fu import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, parameter type fu_data_t = logic ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/decoder.sv b/core/decoder.sv index ee67957cd0..2b8381e814 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -24,6 +24,7 @@ module decoder #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, parameter type irq_ctrl_t = logic, parameter type scoreboard_entry_t = logic ) ( diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 38a984b24d..6340f2b186 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -22,6 +22,7 @@ module ex_stage parameter type branchpredict_sbe_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter type fu_data_t = logic, parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, @@ -256,6 +257,7 @@ module ex_stage .CVA6Cfg(CVA6Cfg), .bp_resolve_t(bp_resolve_t), .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), .fu_data_t(fu_data_t) ) branch_unit_i ( .clk_i, @@ -345,6 +347,7 @@ module ex_stage fpu_wrap #( .CVA6Cfg (CVA6Cfg), + .exception_t(exception_t), .fu_data_t(fu_data_t) ) fpu_i ( .clk_i, @@ -382,6 +385,7 @@ module ex_stage .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), .fu_data_t (fu_data_t), .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), @@ -442,6 +446,7 @@ module ex_stage assign cvxif_data = x_valid_i ? fu_data_i : '0; cvxif_fu #( .CVA6Cfg(CVA6Cfg), + .exception_t(exception_t), .fu_data_t(fu_data_t) ) cvxif_fu_i ( .clk_i, diff --git a/core/fpu_wrap.sv b/core/fpu_wrap.sv index efc0871893..671ce177a1 100644 --- a/core/fpu_wrap.sv +++ b/core/fpu_wrap.sv @@ -17,6 +17,7 @@ module fpu_wrap import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, parameter type fu_data_t = logic ) ( input logic clk_i, diff --git a/core/id_stage.sv b/core/id_stage.sv index 597f6147cd..d892b82eb4 100644 --- a/core/id_stage.sv +++ b/core/id_stage.sv @@ -16,6 +16,7 @@ module id_stage #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, parameter type fetch_entry_t = logic, parameter type irq_ctrl_t = logic, parameter type scoreboard_entry_t = logic @@ -109,6 +110,7 @@ module id_stage #( decoder #( .CVA6Cfg(CVA6Cfg), .branchpredict_sbe_t(branchpredict_sbe_t), + .exception_t(exception_t), .irq_ctrl_t(irq_ctrl_t), .scoreboard_entry_t(scoreboard_entry_t) ) decoder_i ( diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 8895f59137..4b3a0a3553 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -167,15 +167,6 @@ package ariane_pkg; localparam int unsigned INSTR_PER_FETCH = RVC == 1'b1 ? (FETCH_WIDTH / 16) : 1; localparam int unsigned LOG2_INSTR_PER_FETCH = RVC == 1'b1 ? $clog2(INSTR_PER_FETCH) : 1; - // Only use struct when signals have same direction - // exception - typedef struct packed { - riscv::xlen_t cause; // cause of exception - riscv::xlen_t tval; // additional information of causing exception (e.g.: instruction causing it), - // address of LD/ST fault - logic valid; - } exception_t; - typedef enum logic [2:0] { NoCF, // No control flow prediction Branch, // Branch diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 2162e4389a..35c231e134 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -20,6 +20,7 @@ module issue_stage parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, parameter type branchpredict_sbe_t = logic, + parameter type exception_t = logic, parameter type fu_data_t = logic, parameter type scoreboard_entry_t = logic ) ( @@ -164,6 +165,7 @@ module issue_stage .CVA6Cfg (CVA6Cfg), .rs3_len_t (rs3_len_t), .bp_resolve_t(bp_resolve_t), + .exception_t(exception_t), .scoreboard_entry_t(scoreboard_entry_t) ) i_scoreboard ( .sb_full_o (sb_full_o), diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 0a100b658e..57fbadb34e 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -19,6 +19,7 @@ module load_store_unit parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter type fu_data_t = logic, parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, @@ -187,6 +188,7 @@ module load_store_unit if (MMU_PRESENT && (riscv::XLEN == 64)) begin : gen_mmu_sv39 mmu #( .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), .icache_areq_t (icache_areq_t), .icache_arsp_t (icache_arsp_t), .icache_dreq_t (icache_dreq_t), @@ -222,6 +224,7 @@ module load_store_unit end else if (MMU_PRESENT && (riscv::XLEN == 32)) begin : gen_mmu_sv32 cva6_mmu_sv32 #( .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), .icache_areq_t (icache_areq_t), .icache_arsp_t (icache_arsp_t), .icache_dreq_t (icache_dreq_t), @@ -305,6 +308,7 @@ module load_store_unit .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), .lsu_ctrl_t(lsu_ctrl_t) ) i_store_unit ( .clk_i, @@ -350,6 +354,7 @@ module load_store_unit .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), + .exception_t(exception_t), .lsu_ctrl_t(lsu_ctrl_t) ) i_load_unit ( .valid_i (ld_valid_i), diff --git a/core/load_unit.sv b/core/load_unit.sv index 0814c71fab..70b1f484d6 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -24,6 +24,7 @@ module load_unit parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM diff --git a/core/mmu_sv32/cva6_mmu_sv32.sv b/core/mmu_sv32/cva6_mmu_sv32.sv index 4a0518bf67..1f452423f0 100644 --- a/core/mmu_sv32/cva6_mmu_sv32.sv +++ b/core/mmu_sv32/cva6_mmu_sv32.sv @@ -30,6 +30,7 @@ module cva6_mmu_sv32 import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type exception_t = logic, parameter type icache_areq_t = logic, parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index 515e2e7341..1fdb3f528e 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -25,6 +25,7 @@ module mmu parameter type icache_drsp_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 diff --git a/core/perf_counters.sv b/core/perf_counters.sv index abef4c36bf..90867e871f 100644 --- a/core/perf_counters.sv +++ b/core/perf_counters.sv @@ -20,6 +20,7 @@ module perf_counters parameter type bp_resolve_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter type icache_dreq_t = logic, parameter type scoreboard_entry_t = logic, parameter int unsigned NumPorts = 3 // number of miss ports diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 9f5120bf44..c6bd62a8e9 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -15,6 +15,7 @@ module scoreboard #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type bp_resolve_t = logic, + parameter type exception_t = logic, parameter type scoreboard_entry_t = logic, parameter type rs3_len_t = logic ) ( @@ -90,7 +91,7 @@ module scoreboard #( // Results to write back - TO_BE_COMPLETED input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, // Exception from a functional unit (e.g.: ld/st exception) - TO_BE_COMPLETED - input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, + input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, // Indicates valid results - TO_BE_COMPLETED input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, // Cvxif we for writeback - TO_BE_COMPLETED diff --git a/core/store_unit.sv b/core/store_unit.sv index b6d3342256..9d09f2b174 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -19,6 +19,7 @@ module store_unit parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter type lsu_ctrl_t = logic ) ( // Subsystem Clock - SUBSYSTEM From 228499cbfea71036971d39fdc80a14842cd38eb7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Wed, 6 Dec 2023 15:14:56 +0100 Subject: [PATCH 24/28] move wbuffer_t --- core/cache_subsystem/wt_dcache.sv | 15 ++++++++++++++- core/cache_subsystem/wt_dcache_mem.sv | 1 + core/cache_subsystem/wt_dcache_wbuffer.sv | 3 ++- core/include/wt_cache_pkg.sv | 12 ------------ 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index 1ff99cb2f9..7a86ecba62 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -53,6 +53,17 @@ module wt_dcache output dcache_req_t mem_data_o ); + localparam type wbuffer_t = struct packed { + logic [ariane_pkg::DCACHE_TAG_WIDTH+(ariane_pkg::DCACHE_INDEX_WIDTH-riscv::XLEN_ALIGN_BYTES)-1:0] wtag; + riscv::xlen_t data; + logic [ariane_pkg::DCACHE_USER_WIDTH-1:0] user; + logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty + logic [(riscv::XLEN/8)-1:0] valid; // byte is valid + logic [(riscv::XLEN/8)-1:0] txblock; // byte is part of transaction in-flight + logic checked; // if cache state of this word has been checked + logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache + }; + // miss unit <-> read controllers logic cache_en; @@ -244,7 +255,8 @@ module wt_dcache wt_dcache_wbuffer #( .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), - .dcache_req_o_t(dcache_req_o_t) + .dcache_req_o_t(dcache_req_o_t), + .wbuffer_t(wbuffer_t) ) i_wt_dcache_wbuffer ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -302,6 +314,7 @@ module wt_dcache wt_dcache_mem #( .CVA6Cfg (CVA6Cfg), + .wbuffer_t(wbuffer_t), .NumPorts(NumPorts) ) i_wt_dcache_mem ( .clk_i (clk_i), diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv index b2b41c3c73..c8b55463fa 100644 --- a/core/cache_subsystem/wt_dcache_mem.sv +++ b/core/cache_subsystem/wt_dcache_mem.sv @@ -31,6 +31,7 @@ module wt_dcache_mem import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type wbuffer_t = logic, parameter int unsigned NumPorts = 3 ) ( input logic clk_i, diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index 5597de1192..29d136edce 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -55,7 +55,8 @@ module wt_dcache_wbuffer #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, - parameter type dcache_req_o_t = logic + parameter type dcache_req_o_t = logic, + parameter type wbuffer_t = logic ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 7fa99fee43..d77d9b797b 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -66,18 +66,6 @@ package wt_cache_pkg; localparam DCACHE_WBUF_DEPTH = ariane_pkg::WT_DCACHE_WBUF_DEPTH; localparam CACHE_ID_WIDTH = L15_TID_WIDTH; - - typedef struct packed { - logic [ariane_pkg::DCACHE_TAG_WIDTH+(ariane_pkg::DCACHE_INDEX_WIDTH-riscv::XLEN_ALIGN_BYTES)-1:0] wtag; - riscv::xlen_t data; - logic [ariane_pkg::DCACHE_USER_WIDTH-1:0] user; - logic [(riscv::XLEN/8)-1:0] dirty; // byte is dirty - logic [(riscv::XLEN/8)-1:0] valid; // byte is valid - logic [(riscv::XLEN/8)-1:0] txblock; // byte is part of transaction in-flight - logic checked; // if cache state of this word has been checked - logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] hit_oh; // valid way in the cache - } wbuffer_t; - // TX status registers are indexed with the transaction ID // they basically store which bytes from which buffer entry are part // of that transaction From 952efc0e7ed8913fbf7d9c2b90c75281939bf51a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Wed, 6 Dec 2023 15:19:02 +0100 Subject: [PATCH 25/28] move tx_stat_t --- core/cache_subsystem/wt_dcache_wbuffer.sv | 6 ++++++ core/include/wt_cache_pkg.sv | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index 29d136edce..7e698e6863 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -108,6 +108,12 @@ module wt_dcache_wbuffer output logic [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_vld_o ); + typedef struct packed { + logic vld; + logic [(riscv::XLEN/8)-1:0] be; + logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] ptr; + } tx_stat_t; + tx_stat_t [CVA6Cfg.DCACHE_MAX_TX-1:0] tx_stat_d, tx_stat_q; wbuffer_t [DCACHE_WBUF_DEPTH-1:0] wbuffer_d, wbuffer_q; logic [DCACHE_WBUF_DEPTH-1:0] valid; diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index d77d9b797b..6c2a8a7ad4 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -70,12 +70,6 @@ package wt_cache_pkg; // they basically store which bytes from which buffer entry are part // of that transaction - typedef struct packed { - logic vld; - logic [(riscv::XLEN/8)-1:0] be; - logic [$clog2(DCACHE_WBUF_DEPTH)-1:0] ptr; - } tx_stat_t; - // local interfaces between caches and L15 adapter typedef enum logic [1:0] { DCACHE_STORE_REQ, From 5cfdbe43e8b617d2f2fc7e6f7c1ef91ff9b383af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Wed, 6 Dec 2023 16:06:23 +0100 Subject: [PATCH 26/28] move dcache_{req,rtrn,inval}_t --- core/cache_subsystem/wt_axi_adapter.sv | 5 ++- core/cache_subsystem/wt_cache_subsystem.sv | 39 ++++++++++++++++++++-- core/cache_subsystem/wt_dcache.sv | 4 +++ core/cache_subsystem/wt_dcache_missunit.sv | 2 ++ core/cache_subsystem/wt_l15_adapter.sv | 4 ++- core/include/wt_cache_pkg.sv | 29 ---------------- 6 files changed, 50 insertions(+), 33 deletions(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index f167779577..9204684b89 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -23,6 +23,9 @@ module wt_axi_adapter parameter int unsigned MetaFifoDepth = CVA6Cfg.DCACHE_MAX_TX, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic, + parameter type dcache_inval_t = logic, parameter type icache_req_t = logic, parameter type icache_rtrn_t = logic ) ( @@ -440,7 +443,7 @@ module wt_axi_adapter logic [DCACHE_LINE_WIDTH/CVA6Cfg.AxiDataWidth-1:0][CVA6Cfg.AxiDataWidth-1:0] dcache_rd_shift_d, dcache_rd_shift_q; wt_cache_pkg::dcache_in_t dcache_rtrn_type_d, dcache_rtrn_type_q; - wt_cache_pkg::dcache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q; + dcache_inval_t dcache_rtrn_inv_d, dcache_rtrn_inv_q; logic dcache_sc_rtrn, axi_rd_last; always_comb begin : p_axi_rtrn_shift diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index 527356a3c2..a8c336efa2 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -75,14 +75,42 @@ module wt_cache_subsystem // TODO: interrupt interface ); + // dcache interface + localparam type dcache_inval_t = struct packed { + logic vld; // invalidate only affected way + logic all; // invalidate all ways + logic [ariane_pkg::DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate + logic [L15_WAY_WIDTH-1:0] way; // way to invalidate + }; + + localparam type dcache_req_t = struct packed { + wt_cache_pkg::dcache_out_t rtype; // see definitions above + logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [L1D_WAY_WIDTH-1:0] way; // way to replace + logic [riscv::PLEN-1:0] paddr; // physical address + riscv::xlen_t data; // word width of processor (no block stores at the moment) + logic [ariane_pkg::DATA_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment) + logic nc; // noncacheable + logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + ariane_pkg::amo_t amo_op; // amo opcode + }; + + localparam type dcache_rtrn_t = struct packed { + wt_cache_pkg::dcache_in_t rtype; // see definitions above + logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width + logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user; // user bits + dcache_inval_t inv; // invalidation vector + logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) + }; + logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld; icache_req_t icache_adapter; icache_rtrn_t adapter_icache; logic dcache_adapter_data_req, adapter_dcache_data_ack, adapter_dcache_rtrn_vld; - wt_cache_pkg::dcache_req_t dcache_adapter; - wt_cache_pkg::dcache_rtrn_t adapter_dcache; + dcache_req_t dcache_adapter; + dcache_rtrn_t adapter_dcache; cva6_icache #( // use ID 0 for icache reads @@ -120,6 +148,8 @@ module wt_cache_subsystem .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), // use ID 1 for dcache reads and amos. note that the writebuffer // uses all IDs up to DCACHE_MAX_TX-1 for write transactions. .RdAmoTxId(1) @@ -153,6 +183,8 @@ module wt_cache_subsystem `ifdef PITON_ARIANE wt_l15_adapter #( .CVA6Cfg(CVA6Cfg), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), .icache_req_t(icache_req_t), .icache_rtrn_t(icache_rtrn_t) ) i_adapter ( @@ -176,6 +208,9 @@ module wt_cache_subsystem .CVA6Cfg (CVA6Cfg), .axi_req_t(noc_req_t), .axi_rsp_t(noc_resp_t), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), + .dcache_inval_t(dcache_inval_t), .icache_req_t(icache_req_t), .icache_rtrn_t(icache_rtrn_t) ) i_adapter ( diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index 7a86ecba62..d616f3c992 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -20,6 +20,8 @@ module wt_dcache parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic, parameter int unsigned NumPorts = 4, // number of miss ports // ID to be used for read and AMO transactions. // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions @@ -127,6 +129,8 @@ module wt_dcache wt_dcache_missunit #( .CVA6Cfg (CVA6Cfg), + .dcache_req_t(dcache_req_t), + .dcache_rtrn_t(dcache_rtrn_t), .AmoTxId (RdAmoTxId), .NumPorts(NumPorts) ) i_wt_dcache_missunit ( diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 2301fea454..ab9b698901 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -19,6 +19,8 @@ module wt_dcache_missunit import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic, parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs parameter int unsigned NumPorts = 4 // number of miss ports ) ( diff --git a/core/cache_subsystem/wt_l15_adapter.sv b/core/cache_subsystem/wt_l15_adapter.sv index 2201985da6..19df44379d 100644 --- a/core/cache_subsystem/wt_l15_adapter.sv +++ b/core/cache_subsystem/wt_l15_adapter.sv @@ -55,7 +55,9 @@ module wt_l15_adapter #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type icache_req_t = logic, - parameter type icache_rtrn_t = logic + parameter type icache_rtrn_t = logic, + parameter type dcache_req_t = logic, + parameter type dcache_rtrn_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 6c2a8a7ad4..97b0f0f07f 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -91,35 +91,6 @@ package wt_cache_pkg; ICACHE_IFILL_ACK } icache_in_t; - // dcache interface - typedef struct packed { - logic vld; // invalidate only affected way - logic all; // invalidate all ways - logic [ariane_pkg::DCACHE_INDEX_WIDTH-1:0] idx; // physical address to invalidate - logic [L15_WAY_WIDTH-1:0] way; // way to invalidate - } dcache_inval_t; - - typedef struct packed { - dcache_out_t rtype; // see definitions above - logic [2:0] size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) - logic [L1D_WAY_WIDTH-1:0] way; // way to replace - logic [riscv::PLEN-1:0] paddr; // physical address - riscv::xlen_t data; // word width of processor (no block stores at the moment) - logic [ariane_pkg::DATA_USER_WIDTH-1:0] user; // user width of processor (no block stores at the moment) - logic nc; // noncacheable - logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) - ariane_pkg::amo_t amo_op; // amo opcode - } dcache_req_t; - - typedef struct packed { - dcache_in_t rtype; // see definitions above - logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data; // full cache line width - logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user; // user bits - dcache_inval_t inv; // invalidation vector - logic [CACHE_ID_WIDTH-1:0] tid; // threadi id (used as transaction id in Ariane) - } dcache_rtrn_t; - - // taken from iop.h in openpiton // to l1.5 (only marked subset is used) typedef enum logic [4:0] { From cf1d83817ffb8b3f6b6b0127a773ad70d8100b0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Mon, 11 Dec 2023 08:53:18 +0100 Subject: [PATCH 27/28] move l15_{req,rtrn}_t --- core/cache_subsystem/wt_l15_adapter.sv | 45 ++++++++++++++++++++++++ core/include/wt_cache_pkg.sv | 47 -------------------------- 2 files changed, 45 insertions(+), 47 deletions(-) diff --git a/core/cache_subsystem/wt_l15_adapter.sv b/core/cache_subsystem/wt_l15_adapter.sv index 19df44379d..04877e7cb8 100644 --- a/core/cache_subsystem/wt_l15_adapter.sv +++ b/core/cache_subsystem/wt_l15_adapter.sv @@ -83,6 +83,51 @@ module wt_l15_adapter input l15_rtrn_t l15_rtrn_i ); + localparam type l15_req_t = struct packed { + logic l15_val; // valid signal, asserted with request + logic l15_req_ack; // ack for response + wt_cache_pkg::l15_reqtypes_t l15_rqtype; // see below for encoding + logic l15_nc; // non-cacheable bit + logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) + logic [wt_cache_pkg::L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1 + logic l15_prefetch; // unused in openpiton + logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment + logic l15_blockstore; // unused in openpiton + logic l15_blockinitstore; // unused in openpiton + logic [wt_cache_pkg::L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace + logic [39:0] l15_address; // physical address + logic [63:0] l15_data; // word to write + logic [63:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) + logic [wt_cache_pkg::L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane + logic [3:0] l15_amo_op; // atomic operation type + }; + localparam type l15_rtrn_t = struct packed { + logic l15_ack; // ack for request struct + logic l15_header_ack; // ack for request struct + logic l15_val; // valid signal for return struct + wt_l15_adapter::l15_rtrntypes_t l15_returntype; // see below for encoding + logic l15_l2miss; // unused in Ariane + logic [1:0] l15_error; // unused in openpiton + logic l15_noncacheable; // non-cacheable bit + logic l15_atomic; // asserted in load return and store ack packets of atomic tx + logic [wt_cache_pkg::L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID + logic l15_prefetch; // unused in openpiton + logic l15_f4b; // 4byte instruction fill from I/O space (nc). + logic [63:0] l15_data_0; // used for both caches + logic [63:0] l15_data_1; // used for both caches + logic [63:0] l15_data_2; // currently only used for I$ + logic [63:0] l15_data_3; // currently only used for I$ + logic l15_inval_icache_all_way; // invalidate all ways + logic l15_inval_dcache_all_way; // unused in openpiton + logic [15:4] l15_inval_address_15_4; // invalidate selected cacheline + logic l15_cross_invalidate; // unused in openpiton + logic [wt_cache_pkg::L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton + logic l15_inval_dcache_inval; // invalidate selected cacheline and way + logic l15_inval_icache_inval; // unused in openpiton + logic [wt_cache_pkg::L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate + logic l15_blockinitstore; // unused in openpiton + }; + // request path icache_req_t icache_data; logic icache_data_full, icache_data_empty; diff --git a/core/include/wt_cache_pkg.sv b/core/include/wt_cache_pkg.sv index 97b0f0f07f..e84df5dde8 100644 --- a/core/include/wt_cache_pkg.sv +++ b/core/include/wt_cache_pkg.sv @@ -130,53 +130,6 @@ package wt_cache_pkg; L15_CPX_RESTYPE_ATOMIC_RES = 4'b1110 // custom type for atomic responses } l15_rtrntypes_t; - - typedef struct packed { - logic l15_val; // valid signal, asserted with request - logic l15_req_ack; // ack for response - l15_reqtypes_t l15_rqtype; // see below for encoding - logic l15_nc; // non-cacheable bit - logic [2:0] l15_size; // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte) - logic [L15_TID_WIDTH-1:0] l15_threadid; // currently 0 or 1 - logic l15_prefetch; // unused in openpiton - logic l15_invalidate_cacheline; // unused by Ariane as L1 has no ECC at the moment - logic l15_blockstore; // unused in openpiton - logic l15_blockinitstore; // unused in openpiton - logic [L15_WAY_WIDTH-1:0] l15_l1rplway; // way to replace - logic [39:0] l15_address; // physical address - logic [63:0] l15_data; // word to write - logic [63:0] l15_data_next_entry; // unused in Ariane (only used for CAS atomic requests) - logic [L15_TLB_CSM_WIDTH-1:0] l15_csm_data; // unused in Ariane - logic [3:0] l15_amo_op; // atomic operation type - } l15_req_t; - - typedef struct packed { - logic l15_ack; // ack for request struct - logic l15_header_ack; // ack for request struct - logic l15_val; // valid signal for return struct - l15_rtrntypes_t l15_returntype; // see below for encoding - logic l15_l2miss; // unused in Ariane - logic [1:0] l15_error; // unused in openpiton - logic l15_noncacheable; // non-cacheable bit - logic l15_atomic; // asserted in load return and store ack packets of atomic tx - logic [L15_TID_WIDTH-1:0] l15_threadid; // used as transaction ID - logic l15_prefetch; // unused in openpiton - logic l15_f4b; // 4byte instruction fill from I/O space (nc). - logic [63:0] l15_data_0; // used for both caches - logic [63:0] l15_data_1; // used for both caches - logic [63:0] l15_data_2; // currently only used for I$ - logic [63:0] l15_data_3; // currently only used for I$ - logic l15_inval_icache_all_way; // invalidate all ways - logic l15_inval_dcache_all_way; // unused in openpiton - logic [15:4] l15_inval_address_15_4; // invalidate selected cacheline - logic l15_cross_invalidate; // unused in openpiton - logic [L15_WAY_WIDTH-1:0] l15_cross_invalidate_way; // unused in openpiton - logic l15_inval_dcache_inval; // invalidate selected cacheline and way - logic l15_inval_icache_inval; // unused in openpiton - logic [L15_WAY_WIDTH-1:0] l15_inval_way; // way to invalidate - logic l15_blockinitstore; // unused in openpiton - } l15_rtrn_t; - // swap endianess in a 64bit word function automatic logic [63:0] swendian64(input logic [63:0] in); automatic logic [63:0] out; From 472308e50512323c97554f9a9c369ece871429d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20Allart?= Date: Fri, 8 Mar 2024 14:58:48 +0100 Subject: [PATCH 28/28] format: apply Verible --- .../cva6_hpdcache_if_adapter.sv | 16 +++++----- .../cva6_hpdcache_subsystem.sv | 26 ++++++++-------- .../cva6_hpdcache_subsystem_axi_arbiter.sv | 12 ++++---- core/cache_subsystem/miss_handler.sv | 12 ++++---- core/cache_subsystem/std_cache_subsystem.sv | 6 ++-- core/cache_subsystem/std_nbdcache.sv | 6 ++-- core/cache_subsystem/wt_cache_subsystem.sv | 20 ++++++------- core/cache_subsystem/wt_dcache.sv | 10 +++---- core/cache_subsystem/wt_dcache_ctrl.sv | 2 +- core/cache_subsystem/wt_dcache_mem.sv | 6 ++-- core/cva6.sv | 30 +++++++++---------- core/ex_stage.sv | 4 +-- core/frontend/frontend.sv | 8 ++--- core/include/ariane_pkg.sv | 2 +- core/mmu_sv39/mmu.sv | 18 +++++------ 15 files changed, 89 insertions(+), 89 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index fc8d1ce93d..7f27d61b1d 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -15,10 +15,10 @@ module cva6_hpdcache_if_adapter // Parameters // {{{ #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type dcache_req_i_t = logic, - parameter type dcache_req_o_t = logic, - parameter bit is_load_port = 1'b1 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter bit is_load_port = 1'b1 ) // }}} @@ -33,10 +33,10 @@ module cva6_hpdcache_if_adapter input hpdcache_pkg::hpdcache_req_sid_t hpdcache_req_sid_i, // Request/response ports from/to the CVA6 core - input dcache_req_i_t cva6_req_i, - output dcache_req_o_t cva6_req_o, - input ariane_pkg::amo_req_t cva6_amo_req_i, - output ariane_pkg::amo_resp_t cva6_amo_resp_o, + input dcache_req_i_t cva6_req_i, + output dcache_req_o_t cva6_req_o, + input ariane_pkg::amo_req_t cva6_amo_req_i, + output ariane_pkg::amo_resp_t cva6_amo_resp_o, // Request port to the L1 Dcache output logic hpdcache_req_valid_o, diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 0802ba88ca..83a4be5da2 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -68,17 +68,17 @@ module cva6_hpdcache_subsystem output logic dcache_miss_o, // we missed on a ld/st // AMO interface - input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU - output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU + input ariane_pkg::amo_req_t dcache_amo_req_i, // from LSU + output ariane_pkg::amo_resp_t dcache_amo_resp_o, // to LSU // CMO interface - input cmo_req_t dcache_cmo_req_i, // from CMO FU - output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU + input cmo_req_t dcache_cmo_req_i, // from CMO FU + output cmo_rsp_t dcache_cmo_resp_o, // to CMO FU // Request ports - input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU - output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to LSU // Write Buffer status - output logic wbuffer_empty_o, - output logic wbuffer_not_ni_o, + output logic wbuffer_empty_o, + output logic wbuffer_not_ni_o, // Hardware memory prefetcher configuration input logic [NrHwPrefetchers-1:0] hwpf_base_set_i, @@ -119,7 +119,7 @@ module cva6_hpdcache_subsystem .icache_drsp_t(icache_drsp_t), .icache_req_t(icache_req_t), .icache_rtrn_t(icache_rtrn_t), - .RdTxId (ICACHE_RDTXID) + .RdTxId(ICACHE_RDTXID) ) i_cva6_icache ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -232,10 +232,10 @@ module cva6_hpdcache_subsystem assign dcache_req_ports[r] = dcache_req_ports_i[r]; cva6_hpdcache_if_adapter #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .is_load_port(1'b1) + .is_load_port (1'b1) ) i_cva6_hpdcache_load_if_adapter ( .clk_i, .rst_ni, @@ -260,10 +260,10 @@ module cva6_hpdcache_subsystem end cva6_hpdcache_if_adapter #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .is_load_port(1'b0) + .is_load_port (1'b0) ) i_cva6_hpdcache_store_if_adapter ( .clk_i, .rst_ni, diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv index 88728a0e0d..5af3ae6f66 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv @@ -49,13 +49,13 @@ module cva6_hpdcache_subsystem_axi_arbiter // Interfaces from/to I$ // {{{ - input logic icache_miss_valid_i, - output logic icache_miss_ready_o, - input icache_req_t icache_miss_i, - input hpdcache_mem_id_t icache_miss_id_i, + input logic icache_miss_valid_i, + output logic icache_miss_ready_o, + input icache_req_t icache_miss_i, + input hpdcache_mem_id_t icache_miss_id_i, - output logic icache_miss_resp_valid_o, - output icache_rtrn_t icache_miss_resp_o, + output logic icache_miss_resp_valid_o, + output icache_rtrn_t icache_miss_resp_o, // }}} // Interfaces from/to D$ diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index ff977b8e15..223fc46bae 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -20,12 +20,12 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned NR_PORTS = 4, - parameter type axi_req_t = logic, - parameter type axi_rsp_t = logic, - parameter type cache_line_t = logic, - parameter type cl_be_t = logic + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter int unsigned NR_PORTS = 4, + parameter type axi_req_t = logic, + parameter type axi_rsp_t = logic, + parameter type cache_line_t = logic, + parameter type cl_be_t = logic ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index 3dbcf43075..e5d077c7cc 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -76,7 +76,7 @@ module std_cache_subsystem axi_rsp_t axi_resp_data; cva6_icache_axi_wrapper #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .icache_areq_t(icache_areq_t), .icache_arsp_t(icache_arsp_t), .icache_dreq_t(icache_dreq_t), @@ -106,10 +106,10 @@ module std_cache_subsystem // Port 2: Accelerator // Port 3: Store Unit std_nbdcache #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .NumPorts (NumPorts), + .NumPorts(NumPorts), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t) ) i_nbdcache ( diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index f2e71fdaf8..466feaf205 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -53,7 +53,7 @@ module std_nbdcache logic dirty; // state array }; localparam type cl_be_t = struct packed { - logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array + logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits) }; @@ -152,8 +152,8 @@ module std_nbdcache // Miss Handling Unit // ------------------ miss_handler #( - .CVA6Cfg (CVA6Cfg), - .NR_PORTS (NumPorts), + .CVA6Cfg(CVA6Cfg), + .NR_PORTS(NumPorts), .axi_req_t(axi_req_t), .axi_rsp_t(axi_rsp_t), .cache_line_t(cache_line_t), diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index a8c336efa2..a79670cb7a 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -23,18 +23,18 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type icache_areq_t = logic, - parameter type icache_arsp_t = logic, - parameter type icache_dreq_t = logic, - parameter type icache_drsp_t = logic, + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type icache_areq_t = logic, + parameter type icache_arsp_t = logic, + parameter type icache_dreq_t = logic, + parameter type icache_drsp_t = logic, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter type icache_req_t = logic, parameter type icache_rtrn_t = logic, - parameter int unsigned NumPorts = 4, - parameter type noc_req_t = logic, - parameter type noc_resp_t = logic + parameter int unsigned NumPorts = 4, + parameter type noc_req_t = logic, + parameter type noc_resp_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -145,7 +145,7 @@ module wt_cache_subsystem // they have equal prio and are RR arbited // Port 2 is write only and goes into the merging write buffer wt_dcache #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .dcache_req_t(dcache_req_t), @@ -205,7 +205,7 @@ module wt_cache_subsystem ); `else wt_axi_adapter #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .axi_req_t(noc_req_t), .axi_rsp_t(noc_resp_t), .dcache_req_t(dcache_req_t), diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index d616f3c992..a1467ffbf0 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -128,10 +128,10 @@ module wt_dcache /////////////////////////////////////////////////////// wt_dcache_missunit #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .dcache_req_t(dcache_req_t), .dcache_rtrn_t(dcache_rtrn_t), - .AmoTxId (RdAmoTxId), + .AmoTxId(RdAmoTxId), .NumPorts(NumPorts) ) i_wt_dcache_missunit ( .clk_i (clk_i), @@ -194,7 +194,7 @@ module wt_dcache .CVA6Cfg(CVA6Cfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .RdTxId (RdAmoTxId) + .RdTxId(RdAmoTxId) ) i_wt_dcache_ctrl ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -317,9 +317,9 @@ module wt_dcache /////////////////////////////////////////////////////// wt_dcache_mem #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .wbuffer_t(wbuffer_t), - .NumPorts(NumPorts) + .NumPorts (NumPorts) ) i_wt_dcache_mem ( .clk_i (clk_i), .rst_ni (rst_ni), diff --git a/core/cache_subsystem/wt_dcache_ctrl.sv b/core/cache_subsystem/wt_dcache_ctrl.sv index ad76083d67..237cac8ad8 100644 --- a/core/cache_subsystem/wt_dcache_ctrl.sv +++ b/core/cache_subsystem/wt_dcache_ctrl.sv @@ -20,7 +20,7 @@ module wt_dcache_ctrl parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, - parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1 + parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1 ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv index c8b55463fa..90bf80a2d6 100644 --- a/core/cache_subsystem/wt_dcache_mem.sv +++ b/core/cache_subsystem/wt_dcache_mem.sv @@ -30,9 +30,9 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #( - parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type wbuffer_t = logic, - parameter int unsigned NumPorts = 3 + parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, + parameter type wbuffer_t = logic, + parameter int unsigned NumPorts = 3 ) ( input logic clk_i, input logic rst_ni, diff --git a/core/cva6.sv b/core/cva6.sv index 3ca2a0a18c..cb3b065362 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1205,21 +1205,21 @@ module cva6 // note: this only works with one cacheable region // not as important since this cache subsystem is about to be // deprecated - .CVA6Cfg (CVA6Cfg), - .icache_areq_t(icache_areq_t), - .icache_arsp_t(icache_arsp_t), - .icache_dreq_t(icache_dreq_t), - .icache_drsp_t(icache_drsp_t), + .CVA6Cfg (CVA6Cfg), + .icache_areq_t (icache_areq_t), + .icache_arsp_t (icache_arsp_t), + .icache_dreq_t (icache_dreq_t), + .icache_drsp_t (icache_drsp_t), .icache_req_t (icache_req_t), .icache_rtrn_t (icache_rtrn_t), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), - .NumPorts (NumPorts), - .axi_ar_chan_t(axi_ar_chan_t), - .axi_aw_chan_t(axi_aw_chan_t), - .axi_w_chan_t (axi_w_chan_t), - .axi_req_t (noc_req_t), - .axi_rsp_t (noc_resp_t) + .NumPorts (NumPorts), + .axi_ar_chan_t (axi_ar_chan_t), + .axi_aw_chan_t (axi_aw_chan_t), + .axi_w_chan_t (axi_w_chan_t), + .axi_req_t (noc_req_t), + .axi_rsp_t (noc_resp_t) ) i_cache_subsystem ( // to D$ .clk_i (clk_i), @@ -1510,11 +1510,11 @@ module cva6 //RVFI INSTR cva6_rvfi_probes #( - .CVA6Cfg (CVA6Cfg), - .exception_t (exception_t), + .CVA6Cfg (CVA6Cfg), + .exception_t (exception_t), .scoreboard_entry_t(scoreboard_entry_t), - .lsu_ctrl_t (lsu_ctrl_t), - .rvfi_probes_t(rvfi_probes_t) + .lsu_ctrl_t (lsu_ctrl_t), + .rvfi_probes_t (rvfi_probes_t) ) i_cva6_rvfi_probes ( .flush_i (flush_ctrl_if), diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 6340f2b186..d168ad630a 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -240,7 +240,7 @@ module ex_stage assign alu_data = (alu_valid_i | branch_valid_i) ? fu_data_i : '0; alu #( - .CVA6Cfg(CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .fu_data_t(fu_data_t) ) alu_i ( .clk_i, @@ -346,7 +346,7 @@ module ex_stage assign fpu_data = fpu_valid_i ? fu_data_i : '0; fpu_wrap #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg(CVA6Cfg), .exception_t(exception_t), .fu_data_t(fu_data_t) ) fpu_i ( diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 8e0f822792..587887c051 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -455,10 +455,10 @@ module frontend .clk_i, .rst_ni, .flush_bp_i(flush_bp_i), - .push_i (ras_push), - .pop_i (ras_pop), - .data_i (ras_update), - .data_o (ras_predict) + .push_i(ras_push), + .pop_i(ras_pop), + .data_i(ras_update), + .data_o(ras_predict) ); end diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 4b3a0a3553..7240f3f1bf 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -723,7 +723,7 @@ package ariane_pkg; riscv::xlen_t acc_cons_q; riscv::pmpcfg_t [15:0] pmpcfg_q; logic [15:0][riscv::PLEN-3:0] pmpaddr_q; - } rvfi_probes_csr_t; + } rvfi_probes_csr_t; // RVFI CSR structure typedef struct packed { diff --git a/core/mmu_sv39/mmu.sv b/core/mmu_sv39/mmu.sv index 1fdb3f528e..6aecb2b39f 100644 --- a/core/mmu_sv39/mmu.sv +++ b/core/mmu_sv39/mmu.sv @@ -23,9 +23,9 @@ module mmu parameter type icache_arsp_t = logic, parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, - parameter type dcache_req_i_t = logic, - parameter type dcache_req_o_t = logic, - parameter type exception_t = logic, + parameter type dcache_req_i_t = logic, + parameter type dcache_req_o_t = logic, + parameter type exception_t = logic, parameter int unsigned INSTR_TLB_ENTRIES = 4, parameter int unsigned DATA_TLB_ENTRIES = 4, parameter int unsigned ASID_WIDTH = 1 @@ -114,10 +114,10 @@ module mmu tlb #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .tlb_update_t(tlb_update_t), - .TLB_ENTRIES(INSTR_TLB_ENTRIES), - .ASID_WIDTH (ASID_WIDTH) + .TLB_ENTRIES (INSTR_TLB_ENTRIES), + .ASID_WIDTH (ASID_WIDTH) ) i_itlb ( .clk_i (clk_i), .rst_ni (rst_ni), @@ -138,10 +138,10 @@ module mmu ); tlb #( - .CVA6Cfg (CVA6Cfg), + .CVA6Cfg (CVA6Cfg), .tlb_update_t(tlb_update_t), - .TLB_ENTRIES(DATA_TLB_ENTRIES), - .ASID_WIDTH (ASID_WIDTH) + .TLB_ENTRIES (DATA_TLB_ENTRIES), + .ASID_WIDTH (ASID_WIDTH) ) i_dtlb ( .clk_i (clk_i), .rst_ni (rst_ni),