From dc783f090f731434993faffb1226bcc7982828c3 Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Fri, 9 Feb 2024 17:19:35 +0100 Subject: [PATCH] Populate instruction chapter in CV32A65X Design Document --- docs/01_cva6_user/RISCV_Instructions.rst | 4 ++-- docs/04_cv32a65x_design/source/CSRs.rst | 2 +- .../source/functionality.rst | 2 +- .../source/instructions.rst | 22 ++++++++++++++++++- 4 files changed, 25 insertions(+), 5 deletions(-) diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst index 414f883ba7..a2d9cdd245 100644 --- a/docs/01_cva6_user/RISCV_Instructions.rst +++ b/docs/01_cva6_user/RISCV_Instructions.rst @@ -20,8 +20,8 @@ *This chapter is applicable to all configurations.* -RISC-V Instructions -=================== +CVA6 RISC-V Instructions +======================== Introduction ------------------ diff --git a/docs/04_cv32a65x_design/source/CSRs.rst b/docs/04_cv32a65x_design/source/CSRs.rst index ac96dfca7d..b55116a223 100644 --- a/docs/04_cv32a65x_design/source/CSRs.rst +++ b/docs/04_cv32a65x_design/source/CSRs.rst @@ -12,7 +12,7 @@ CSR === .. toctree:: - :hidden: + :maxdepth: 1 csr_list csr diff --git a/docs/04_cv32a65x_design/source/functionality.rst b/docs/04_cv32a65x_design/source/functionality.rst index f6bcc0d050..71198e13ee 100644 --- a/docs/04_cv32a65x_design/source/functionality.rst +++ b/docs/04_cv32a65x_design/source/functionality.rst @@ -13,7 +13,7 @@ Functionality ============= .. toctree:: - :hidden: + :maxdepth: 1 instructions traps diff --git a/docs/04_cv32a65x_design/source/instructions.rst b/docs/04_cv32a65x_design/source/instructions.rst index 75235ad42c..79c15be36d 100644 --- a/docs/04_cv32a65x_design/source/instructions.rst +++ b/docs/04_cv32a65x_design/source/instructions.rst @@ -7,5 +7,25 @@ Original Author: Jean-Roch COULON - Thales +Instructions +============ -.. include:: ../../01_cva6_user/RISCV_Instructions.rst +The next first subchapter lists the extensions implemented in CVA6. +By configuration, we can enable/disable the extensions. +CV32A65X supports the extensions described in the next subchapters. +RVZicond, RV32A and RVZifencei extensions are not supported by CV32A65X. + + +.. toctree:: + :maxdepth: 1 + + ../../01_cva6_user/RISCV_Instructions + ../../01_cva6_user/RISCV_Instructions_RV32I + ../../01_cva6_user/RISCV_Instructions_RV32M + ../../01_cva6_user/RISCV_Instructions_RV32C + ../../01_cva6_user/RISCV_Instructions_RV32ZCb + ../../01_cva6_user/RISCV_Instructions_RVZba + ../../01_cva6_user/RISCV_Instructions_RVZbb + ../../01_cva6_user/RISCV_Instructions_RVZbc + ../../01_cva6_user/RISCV_Instructions_RVZbs + ../../01_cva6_user/RISCV_Instructions_RVZicsr