From 3104fb7d9f578cd30c028731232d6c2b3434d663 Mon Sep 17 00:00:00 2001 From: h-s-99 Date: Tue, 6 Feb 2024 13:46:41 +0500 Subject: [PATCH] added the condition for updating the tlb only after a miss is incurred --- core/mmu_sv32/cva6_tlb_sv32.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/mmu_sv32/cva6_tlb_sv32.sv b/core/mmu_sv32/cva6_tlb_sv32.sv index 79a7c98dc5..ac23bca6db 100644 --- a/core/mmu_sv32/cva6_tlb_sv32.sv +++ b/core/mmu_sv32/cva6_tlb_sv32.sv @@ -124,7 +124,7 @@ module cva6_tlb_sv32 else if ((!content_q[i].g) && (vaddr_to_be_flushed_is0) && (asid_to_be_flushed_i == tags_q[i].asid[ASID_WIDTH-1:0]) && (!asid_to_be_flushed_is0)) tags_n[i].valid = 1'b0; // normal replacement - end else if (update_i.valid & replace_en[i]) begin + end else if (update_i.valid & replace_en[i] & !lu_hit_o) begin // update tag array tags_n[i] = '{ asid: update_i.asid,