diff --git a/docs/01_cva6_user/AXI_Interface.rst b/docs/01_cva6_user/AXI_Interface.rst index fdcc2c0860..d88953d3da 100644 --- a/docs/01_cva6_user/AXI_Interface.rst +++ b/docs/01_cva6_user/AXI_Interface.rst @@ -25,7 +25,7 @@ In order to understand how the AXI memory interface behaves in CVA6, it is neces :header: "Configuration", "Implementation" "CV32A60X", "AXI included" - "CV32E6?X", "AXI included" + "CV32E6-X", "AXI included" About the AXI4 protocol ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/01_cva6_user/CSR_Performance_Counters.rst b/docs/01_cva6_user/CSR_Performance_Counters.rst index 7bd3b35556..69baf851e6 100644 --- a/docs/01_cva6_user/CSR_Performance_Counters.rst +++ b/docs/01_cva6_user/CSR_Performance_Counters.rst @@ -26,7 +26,7 @@ :header: "Configuration", "Implementation" "CV32A60X", "Performance counters included" - "CV32E6?X", "No performance counters" + "CV32E6-X", "No performance counters" CSR performance counters control ================================ diff --git a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst index 76e32a6d7e..ea5e4d46b9 100644 --- a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst +++ b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst @@ -32,7 +32,7 @@ with external coprocessors. :header: "Configuration", "Implementation" "CV32A60X", "CV-X-IF included" - "CV32E6?X", "CV-X-IF included" + "CV32E6-X", "CV-X-IF included" CV-X-IF interface specification diff --git a/docs/01_cva6_user/Interfaces.rst b/docs/01_cva6_user/Interfaces.rst index 3e57bfdd57..aa5fc67e31 100644 --- a/docs/01_cva6_user/Interfaces.rst +++ b/docs/01_cva6_user/Interfaces.rst @@ -33,7 +33,7 @@ The AXI interface is described in a separate chapter. :header: "Configuration", "Implementation" "CV32A60X", "AXI implemented" - "CV32E6?X", "AXI implemented" + "CV32E6-X", "AXI implemented" Debug Interface --------------- @@ -51,7 +51,7 @@ Debug Interface :header: "Configuration", "Implementation" "CV32A60X", "Debug interface implemented" - "CV32E6?X", "No debug interface" + "CV32E6-X", "No debug interface" Interrupt Interface ------------------- @@ -76,4 +76,4 @@ For more information, refer to OpenPiton documents. :header: "Configuration", "Implementation" "CV32A60X", "No TRI interface" - "CV32E6?X", "No TRI interface" + "CV32E6-X", "No TRI interface" diff --git a/docs/01_cva6_user/Introduction.rst b/docs/01_cva6_user/Introduction.rst index 2cadde63ec..7476cfea9d 100644 --- a/docs/01_cva6_user/Introduction.rst +++ b/docs/01_cva6_user/Introduction.rst @@ -101,9 +101,9 @@ As of today, two configurations are being verified and addressed in this documen :header: "Configuration", "Short description", "Target", "Privilege levels", "Supported RISC-V ISA", "CV-X-IF" "**CV32A60X**", "32-bit **application** core", "ASIC", "Machine, Supervisor, User", "RV32IMACZicsr_Zifencei_Zicount_Zba_Zbb_Zbc_Zbs_Zcb_Zicond", "Included" - "**CV32E6?X**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included" + "**CV32E6-X**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included" -The "?" digit in CV32E6?X is to be defined, as the team has not yet decided if this core will be extended with dual-issue. +The "-" digit in CV32E6-X is to be defined, as the team has not yet decided if this core will be extended with dual-issue. In the future, dedicated user manuals for each configuration could be generated. The team is looking for a contributor to implement this through *templating*. diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index d3668b2303..366120ebbc 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -80,10 +80,10 @@ These extensions are available in CV32A60X: "RVZifencei - Instruction-Fetch Fence", "✓" "RVZicond - Integer Conditional Operations(Ratification pending)", "✓" -CV32E6?X extensions +CV32E6-X extensions ~~~~~~~~~~~~~~~~~~~ -These extensions are available in CV32E6?X: +These extensions are available in CV32E6-X: .. csv-table:: :widths: auto @@ -139,15 +139,15 @@ These privilege modes are available in CV32A60X: "S - Supervior", "✓" "U - User", "✓" -CV32E6?X privilege modes +CV32E6-X privilege modes ~~~~~~~~~~~~~~~~~~~~~~~~ -These privilege modes are available in CV32E6?X: +These privilege modes are available in CV32E6-X: .. csv-table:: :widths: auto :align: left - :header: "Privileges", "Available in CV32E6?X" + :header: "Privileges", "Available in CV32E6-X" "M - Machine", "✓" "S - Supervior", "" @@ -184,7 +184,7 @@ CV32A60X virtual memory CV32A60X integrates an MMU and supports both the **Bare** and **Sv32** addressing modes. -CV32E6?X virtual memory +CV32E6-X virtual memory ~~~~~~~~~~~~~~~~~~~~~~~~ CV32A60X integrates no MMU and only supports the **Bare** addressing mode. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32A.rst b/docs/01_cva6_user/RISCV_Instructions_RV32A.rst index 364e4b4c7e..5310add41c 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32A.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32A.rst @@ -26,7 +26,7 @@ :header: "Configuration", "Implementation" "CV32A60X", "Implemented extension" - "CV32E6?X", "Not implemented extension" + "CV32E6-X", "Not implemented extension" **Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64A, that includes additional instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32C.rst b/docs/01_cva6_user/RISCV_Instructions_RV32C.rst index 7733619edc..c6ad7d22f2 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32C.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32C.rst @@ -26,7 +26,7 @@ :header: "Configuration", "Implementation" "CV32A60X", "Implemented extension" - "CV32E6?X", "Implemented extension" + "CV32E6-X", "Implemented extension" **Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64C, that includes a different list of instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32I.rst b/docs/01_cva6_user/RISCV_Instructions_RV32I.rst index dcc1175df5..c4caed7dfd 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32I.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32I.rst @@ -28,7 +28,7 @@ This chapter is applicable to all CV32A6 configurations. :header: "Configuration", "Implementation" "CV32A60X", "Implemented extension" - "CV32E6?X", "Implemented extension" + "CV32E6-X", "Implemented extension" **Note**: CV64A6 implements RV64I that includes additional instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32M.rst b/docs/01_cva6_user/RISCV_Instructions_RV32M.rst index 2fd1b168ac..fec9875ca5 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32M.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32M.rst @@ -28,7 +28,7 @@ This chapter is applicable to all CV32A6 configurations. :header: "Configuration", "Implementation" "CV32A60X", "Implemented extension" - "CV32E6?X", "Implemented extension" + "CV32E6-X", "Implemented extension" **Note**: CV64A6 implements RV64M that includes additional instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst b/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst index 2fda2fc5e4..b64c979bfc 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst @@ -26,7 +26,7 @@ :header: "Configuration", "Implementation" "CV32A60X", "Implemented extension" - "CV32E6?X", "Implemented extension" + "CV32E6-X", "Implemented extension" **Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64Zcb, that includes one additional instruction. diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst b/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst index bef4663d01..bec86809b1 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst @@ -26,7 +26,7 @@ :header: "Configuration", "Implementation" "CV32A60X", "Implemented extension" - "CV32E6?X", "Not implemented extension" + "CV32E6-X", "Not implemented extension" **Note**: RV32Zicond and RV64Zicond are identical.