From d0b4024f182f3ebcdcce8df9abdd111a83da1875 Mon Sep 17 00:00:00 2001 From: Alae-Eddine Ez-Zejjari Date: Mon, 4 Dec 2023 15:38:54 +0100 Subject: [PATCH 1/3] Code coverage: condition RTL With parameters and modify coding style Signed-off-by: Alae-Eddine Ez-Zejjari --- core/axi_shim.sv | 32 +++++++++++++++---------------- core/csr_regfile.sv | 6 +++--- core/decoder.sv | 6 +++--- core/frontend/bht.sv | 2 +- core/frontend/frontend.sv | 4 ++-- core/issue_read_operands.sv | 2 +- core/load_unit.sv | 38 ++++++++++++++++--------------------- core/mult.sv | 2 +- core/scoreboard.sv | 2 +- core/store_unit.sv | 2 +- 10 files changed, 44 insertions(+), 52 deletions(-) diff --git a/core/axi_shim.sv b/core/axi_shim.sv index fff40ed3f6..8e1cfa881d 100644 --- a/core/axi_shim.sv +++ b/core/axi_shim.sv @@ -136,8 +136,18 @@ module axi_shim #( axi_req_o.aw_valid = 1'b1; axi_req_o.w_valid = 1'b1; - // its a single write - if (wr_single_req) begin + if (CVA6Cfg.AxiBurstWriteEn && !wr_single_req) begin + wr_cnt_en = axi_resp_i.w_ready; + + case ({ + axi_resp_i.aw_ready, axi_resp_i.w_ready + }) + 2'b11: wr_state_d = WAIT_LAST_W_READY; + 2'b01: wr_state_d = WAIT_LAST_W_READY_AW_READY; + 2'b10: wr_state_d = WAIT_LAST_W_READY; + default: ; + endcase + end else if (wr_single_req) begin // its a single write wr_cnt_clr = 1'b1; // single req can be granted here wr_gnt_o = axi_resp_i.aw_ready & axi_resp_i.w_ready; @@ -149,17 +159,6 @@ module axi_shim #( default: wr_state_d = IDLE; endcase // its a request for the whole cache line - end else if (CVA6Cfg.AxiBurstWriteEn) begin - wr_cnt_en = axi_resp_i.w_ready; - - case ({ - axi_resp_i.aw_ready, axi_resp_i.w_ready - }) - 2'b11: wr_state_d = WAIT_LAST_W_READY; - 2'b01: wr_state_d = WAIT_LAST_W_READY_AW_READY; - 2'b10: wr_state_d = WAIT_LAST_W_READY; - default: ; - endcase end end end @@ -178,15 +177,14 @@ module axi_shim #( WAIT_LAST_W_READY: begin axi_req_o.w_valid = 1'b1; - // this is the last write - if (wr_cnt_done) begin + if (CVA6Cfg.AxiBurstWriteEn && axi_resp_i.w_ready && !wr_cnt_done) begin + wr_cnt_en = 1'b1; + end else if (wr_cnt_done) begin // this is the last write if (axi_resp_i.w_ready) begin wr_state_d = IDLE; wr_cnt_clr = 1'b1; wr_gnt_o = 1'b1; end - end else if (CVA6Cfg.AxiBurstWriteEn && axi_resp_i.w_ready) begin - wr_cnt_en = 1'b1; end end /////////////////////////////////// diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 39606355bb..687e694c0c 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1347,12 +1347,12 @@ module csr_regfile // check counter-enabled counter CSR accesses // counter address range is C00 to C1F if (csr_addr_i inside {[riscv::CSR_CYCLE : riscv::CSR_HPM_COUNTER_31]}) begin - if (priv_lvl_o == riscv::PRIV_LVL_M) begin - privilege_violation = 1'b0; - end else if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + if (priv_lvl_o == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin privilege_violation = ~mcounteren_q[csr_addr_i[4:0]]; end else if (priv_lvl_o == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin privilege_violation = ~mcounteren_q[csr_addr_i[4:0]] | ~scounteren_q[csr_addr_i[4:0]]; + end else if (priv_lvl_o == riscv::PRIV_LVL_M) begin + privilege_violation = 1'b0; end end end diff --git a/core/decoder.sv b/core/decoder.sv index 53432f2eda..f606c935ee 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -1323,12 +1323,12 @@ module decoder // this exception is valid instruction_o.ex.valid = 1'b1; // depending on the privilege mode, set the appropriate cause - if (priv_lvl_i == riscv::PRIV_LVL_M) begin - instruction_o.ex.cause = riscv::ENV_CALL_MMODE; - end else if (priv_lvl_i == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin + if (priv_lvl_i == riscv::PRIV_LVL_S && CVA6Cfg.RVS) begin instruction_o.ex.cause = riscv::ENV_CALL_SMODE; end else if (priv_lvl_i == riscv::PRIV_LVL_U && CVA6Cfg.RVU) begin instruction_o.ex.cause = riscv::ENV_CALL_UMODE; + end else if (priv_lvl_i == riscv::PRIV_LVL_M) begin + instruction_o.ex.cause = riscv::ENV_CALL_MMODE; end end else if (ebreak) begin // this exception is valid diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv index 8be8b0bb25..bcfb78c74e 100644 --- a/core/frontend/bht.sv +++ b/core/frontend/bht.sv @@ -74,7 +74,7 @@ module bht #( bht_d = bht_q; saturation_counter = bht_q[update_pc][update_row_index].saturation_counter; - if (bht_update_i.valid && !debug_mode_i) begin + if ((bht_update_i.valid && CVA6Cfg.DebugEn && !debug_mode_i) || (bht_update_i.valid && !CVA6Cfg.DebugEn)) begin bht_d[update_pc][update_row_index].valid = 1'b1; if (saturation_counter == 2'b11) begin diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 335f088420..8f2f50a048 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -197,7 +197,7 @@ module frontend 4'b0001: begin ras_pop = 1'b0; ras_push = 1'b0; - if (btb_prediction_shifted[i].valid) begin + if (CVA6Cfg.BTBEntries && btb_prediction_shifted[i].valid) begin predict_address = btb_prediction_shifted[i].target_address; cf_type[i] = ariane_pkg::JumpR; end @@ -390,7 +390,7 @@ module frontend icache_data_q <= icache_data; icache_vaddr_q <= icache_dreq_i.vaddr; // Map the only three exceptions which can occur in the frontend to a two bit enum - if (icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin + if (ariane_pkg::MMU_PRESENT && icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin icache_ex_valid_q <= ariane_pkg::FE_INSTR_PAGE_FAULT; end else if (icache_dreq_i.ex.cause == riscv::INSTR_ACCESS_FAULT) begin icache_ex_valid_q <= ariane_pkg::FE_INSTR_ACCESS_FAULT; diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index db74149e1d..2e32486173 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -260,7 +260,7 @@ module issue_read_operands operand_b_n = rs2_i; end - if (forward_rs3) begin + if (CVA6Cfg.FpPresent && forward_rs3) begin imm_n = imm_forward_rs3; end diff --git a/core/load_unit.sv b/core/load_unit.sv index 76604bb3db..512b498cf3 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -257,28 +257,6 @@ module load_unit end end - // Wait until the write-back buffer is empty in the data cache. - WAIT_WB_EMPTY: begin - // the write buffer is empty, so lets go and re-do the translation. - if (CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) state_d = WAIT_TRANSLATION; - end - - WAIT_TRANSLATION: begin - if (ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn) begin - translation_req_o = 1'b1; - // we've got a hit and we can continue with the request process - if (dtlb_hit_i) state_d = WAIT_GNT; - - // we got an exception - if (ex_i.valid) begin - // the next state will be the idle state - state_d = IDLE; - // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction - pop_ld_o = ~req_port_i.data_rvalid; - end - end - end - WAIT_GNT: begin // keep the translation request up translation_req_o = 1'b1; @@ -371,6 +349,22 @@ module load_unit req_port_o.tag_valid = 1'b1; // re-do the request state_d = WAIT_WB_EMPTY; + end else if (state_q == WAIT_WB_EMPTY && CVA6Cfg.NonIdemPotenceEn && dcache_wbuffer_not_ni_i) begin + // Wait until the write-back buffer is empty in the data cache. + // the write buffer is empty, so lets go and re-do the translation. + state_d = WAIT_TRANSLATION; + end else if(state_q == WAIT_TRANSLATION && (ariane_pkg::MMU_PRESENT || CVA6Cfg.NonIdemPotenceEn)) begin + translation_req_o = 1'b1; + // we've got a hit and we can continue with the request process + if (dtlb_hit_i) state_d = WAIT_GNT; + + // we got an exception + if (ex_i.valid) begin + // the next state will be the idle state + state_d = IDLE; + // pop load - but only if we are not getting an rvalid in here - otherwise we will over-write an incoming transaction + pop_ld_o = ~req_port_i.data_rvalid; + end end else begin state_d = IDLE; end diff --git a/core/mult.sv b/core/mult.sv index 7e694fd6c7..7270389569 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -89,7 +89,7 @@ module mult // we've go a new division operation if (mult_valid_i && fu_data_i.operation inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin // is this a word operation? - if (riscv::IS_XLEN64 && (fu_data_i.operation inside {DIVW, DIVUW, REMW, REMUW})) begin + if (riscv::IS_XLEN64 && (fu_data_i.operation == DIVW || fu_data_i.operation == DIVUW || fu_data_i.operation == REMW || fu_data_i.operation == REMUW)) begin // yes so check if we should sign extend this is only done for a signed operation if (div_signed) begin operand_a = sext32(fu_data_i.operand_a[31:0]); diff --git a/core/scoreboard.sv b/core/scoreboard.sv index e924cd6709..9d59d31856 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -185,7 +185,7 @@ module scoreboard #( // write the exception back if it is valid if (ex_i[i].valid) mem_n[trans_id_i[i]].sbe.ex = ex_i[i]; // write the fflags back from the FPU (exception valid is never set), leave tval intact - else if(CVA6Cfg.FpPresent && mem_q[trans_id_i[i]].sbe.fu inside {ariane_pkg::FPU, ariane_pkg::FPU_VEC}) begin + else if(CVA6Cfg.FpPresent && (mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU || mem_q[trans_id_i[i]].sbe.fu == ariane_pkg::FPU_VEC)) begin mem_n[trans_id_i[i]].sbe.ex.cause = ex_i[i].cause; end end diff --git a/core/store_unit.sv b/core/store_unit.sv index 6436242e18..1a3181a379 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -120,7 +120,7 @@ module store_unit st_valid_without_flush = 1'b1; // we have another request and its not an AMO (the AMO buffer only has depth 1) - if (valid_i && !instr_is_amo) begin + if ((valid_i && CVA6Cfg.RVA &&!instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin translation_req_o = 1'b1; state_d = VALID_STORE; From f1f6417c4370032073cd9d1f55bce371531c2130 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Tue, 12 Dec 2023 19:05:02 +0100 Subject: [PATCH 2/3] Update core/store_unit.sv Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --- core/store_unit.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/store_unit.sv b/core/store_unit.sv index 1a3181a379..29a33a1f65 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -120,7 +120,7 @@ module store_unit st_valid_without_flush = 1'b1; // we have another request and its not an AMO (the AMO buffer only has depth 1) - if ((valid_i && CVA6Cfg.RVA &&!instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin + if ((valid_i && CVA6Cfg.RVA && !instr_is_amo) || (valid_i && !CVA6Cfg.RVA)) begin translation_req_o = 1'b1; state_d = VALID_STORE; From 4bcc0a6d035ce9d3065d0d01cd37d5ebc14a0257 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Wed, 13 Dec 2023 07:00:39 +0100 Subject: [PATCH 3/3] Update expected_synth.yml --- .gitlab-ci/expected_synth.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index f699307cda..67ad7a4e0b 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a6_embedded: - gates: 119494 + gates: 118927