From 8af393ea3d02a69441298bca96b903a356a45a85 Mon Sep 17 00:00:00 2001 From: Alae-Eddine Ez-Zejjari Date: Fri, 1 Dec 2023 12:00:20 +0100 Subject: [PATCH 1/5] Code_coverage: condition RTL with the IS_XLEN64 parameter Signed-off-by: Alae-Eddine Ez-Zejjari --- core/alu.sv | 7 ++----- core/cache_subsystem/wt_axi_adapter.sv | 2 +- core/decoder.sv | 2 +- core/load_store_unit.sv | 4 ++-- core/mult.sv | 4 ++-- core/multiplier.sv | 6 ++++-- 6 files changed, 12 insertions(+), 13 deletions(-) diff --git a/core/alu.sv b/core/alu.sv index 01533b6c0a..75727b488a 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -284,9 +284,6 @@ module alu endcase end unique case (fu_data_i.operation) - // Left Shift 32 bit unsigned - SLLIUW: - result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Integer minimum/maximum MAX: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; MAXU: result_o = less ? fu_data_i.operand_b : fu_data_i.operand_a; @@ -323,8 +320,8 @@ module alu result_o = orcbw_result; REV8: result_o = rev8w_result; - - default: ; // default case to suppress unique warning + // Left Shift 32 bit unsigned + default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // default case to suppress unique warning endcase end if (CVA6Cfg.ZiCondExtEn) begin diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index f3eb698989..fae4fd7047 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -205,7 +205,7 @@ module wt_axi_adapter 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = '1; // word default: - axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword + if (riscv::IS_XLEN64) axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword endcase end ////////////////////////////////////// diff --git a/core/decoder.sv b/core/decoder.sv index 0740906d84..37545b262a 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -722,7 +722,7 @@ module decoder end 3'b101: begin if (instr.instr[31:20] == 12'b001010000111) instruction_o.op = ariane_pkg::ORCB; - else if (instr.instr[31:20] == 12'b011010111000 || instr.instr[31:20] == 12'b011010011000) + else if (riscv::IS_XLEN64 && (instr.instr[31:20] == 12'b011010111000 || instr.instr[31:20] == 12'b011010011000)) instruction_o.op = ariane_pkg::REV8; else if (instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI; else if (instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI; diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 94e1c4f119..7311176d7b 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -107,7 +107,7 @@ module load_store_unit assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a)); assign vaddr_i = vaddr_xlen[riscv::VLEN-1:0]; // we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal - assign overflow = !((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0); + assign overflow = (riscv::IS_XLEN64 && !((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0)); logic st_valid_i; logic ld_valid_i; @@ -406,7 +406,7 @@ module load_store_unit AMO_SWAPD, AMO_ADDD, AMO_ANDD, AMO_ORD, AMO_XORD, AMO_MAXD, AMO_MAXDU, AMO_MIND, AMO_MINDU: begin - if (lsu_ctrl.vaddr[2:0] != 3'b000) begin + if (riscv::IS_XLEN64 && lsu_ctrl.vaddr[2:0] != 3'b000) begin data_misaligned = 1'b1; end end diff --git a/core/mult.sv b/core/mult.sv index 6f98e62ccc..7e694fd6c7 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -89,7 +89,7 @@ module mult // we've go a new division operation if (mult_valid_i && fu_data_i.operation inside {DIV, DIVU, DIVW, DIVUW, REM, REMU, REMW, REMUW}) begin // is this a word operation? - if (fu_data_i.operation inside {DIVW, DIVUW, REMW, REMUW}) begin + if (riscv::IS_XLEN64 && (fu_data_i.operation inside {DIVW, DIVUW, REMW, REMUW})) begin // yes so check if we should sign extend this is only done for a signed operation if (div_signed) begin operand_a = sext32(fu_data_i.operand_a[31:0]); @@ -134,7 +134,7 @@ module mult // Result multiplexer // if it was a signed word operation the bit will be set and the result will be sign extended accordingly - assign div_result = (word_op_q) ? sext32(result) : result; + assign div_result = (riscv::IS_XLEN64 && word_op_q) ? sext32(result) : result; // --------------------- // Registers diff --git a/core/multiplier.sv b/core/multiplier.sv index 5f2fcfb69b..d7527b5527 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -116,12 +116,14 @@ module multiplier always_comb begin : p_selmux unique case (operator_q) MULH, MULHU, MULHSU: result_o = mult_result_q[riscv::XLEN*2-1:riscv::XLEN]; - MULW: result_o = sext32(mult_result_q[31:0]); CLMUL: result_o = clmul_q; CLMULH: result_o = clmulr_q >> 1; CLMULR: result_o = clmulr_q; // MUL performs an XLEN-bit×XLEN-bit multiplication and places the lower XLEN bits in the destination register - default: result_o = mult_result_q[riscv::XLEN-1:0]; // including MUL + default: begin + if (operator_q == MULW && riscv::IS_XLEN64) result_o = sext32(mult_result_q[31:0]); + else result_o = mult_result_q[riscv::XLEN-1:0]; // including MUL + end endcase end if (ariane_pkg::BITMANIP) begin From e039f6a2fdd698467dbc9ebe6f3bb19a6b561cee Mon Sep 17 00:00:00 2001 From: AEzzejjari <110914586+AEzzejjari@users.noreply.github.com> Date: Mon, 4 Dec 2023 12:22:14 +0100 Subject: [PATCH 2/5] Update decoder.sv --- core/decoder.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/decoder.sv b/core/decoder.sv index 37545b262a..0740906d84 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -722,7 +722,7 @@ module decoder end 3'b101: begin if (instr.instr[31:20] == 12'b001010000111) instruction_o.op = ariane_pkg::ORCB; - else if (riscv::IS_XLEN64 && (instr.instr[31:20] == 12'b011010111000 || instr.instr[31:20] == 12'b011010011000)) + else if (instr.instr[31:20] == 12'b011010111000 || instr.instr[31:20] == 12'b011010011000) instruction_o.op = ariane_pkg::REV8; else if (instr.instr[31:26] == 6'b010_010) instruction_o.op = ariane_pkg::BEXTI; else if (instr.instr[31:26] == 6'b011_000) instruction_o.op = ariane_pkg::RORI; From 542af3e4578fe16a30c39cd63295fd8d5ae3a23b Mon Sep 17 00:00:00 2001 From: AEzzejjari <110914586+AEzzejjari@users.noreply.github.com> Date: Mon, 4 Dec 2023 12:22:22 +0100 Subject: [PATCH 3/5] Update load_store_unit.sv --- core/load_store_unit.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 7311176d7b..e750f7c8e1 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -107,7 +107,7 @@ module load_store_unit assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a)); assign vaddr_i = vaddr_xlen[riscv::VLEN-1:0]; // we work with SV39 or SV32, so if VM is enabled, check that all bits [XLEN-1:38] or [XLEN-1:31] are equal - assign overflow = (riscv::IS_XLEN64 && !((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0)); + assign overflow = (riscv::IS_XLEN64 && (!((&vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b1 || (|vaddr_xlen[riscv::XLEN-1:riscv::SV-1]) == 1'b0))); logic st_valid_i; logic ld_valid_i; From 4be0890e83ec8c7c0efcd73a1645b412b30166ae Mon Sep 17 00:00:00 2001 From: AEzzejjari <110914586+AEzzejjari@users.noreply.github.com> Date: Mon, 4 Dec 2023 15:51:08 +0100 Subject: [PATCH 4/5] Update core/cache_subsystem/wt_axi_adapter.sv Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --- core/cache_subsystem/wt_axi_adapter.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/core/cache_subsystem/wt_axi_adapter.sv b/core/cache_subsystem/wt_axi_adapter.sv index 49716b434c..1647f1d072 100644 --- a/core/cache_subsystem/wt_axi_adapter.sv +++ b/core/cache_subsystem/wt_axi_adapter.sv @@ -205,7 +205,10 @@ module wt_axi_adapter 2'b10: axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:4] = '1; // word default: - if (riscv::IS_XLEN64) axi_wr_be[0][dcache_data.paddr[$clog2(CVA6Cfg.AxiDataWidth/8)-1:0]+:8] = '1; // dword + if (riscv::IS_XLEN64) + axi_wr_be[0][dcache_data.paddr[$clog2( + CVA6Cfg.AxiDataWidth/8 + )-1:0]+:8] = '1; // dword endcase end ////////////////////////////////////// From 0166ad149a73747d528a8d0c495246739a61c7fd Mon Sep 17 00:00:00 2001 From: AEzzejjari <110914586+AEzzejjari@users.noreply.github.com> Date: Mon, 4 Dec 2023 15:51:21 +0100 Subject: [PATCH 5/5] Update core/alu.sv Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --- core/alu.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/core/alu.sv b/core/alu.sv index eb8bb79171..c78cd56e58 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -341,7 +341,9 @@ module alu ORCB: result_o = orcbw_result; REV8: result_o = rev8w_result; - default: if(fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned + default: + if (fu_data_i.operation == SLLIUW && riscv::IS_XLEN64) + result_o = {{riscv::XLEN-32{1'b0}}, fu_data_i.operand_a[31:0]} << fu_data_i.operand_b[5:0]; // Left Shift 32 bit unsigned endcase end if (CVA6Cfg.ZiCondExtEn) begin