From d8be28b725d8731ddcebac8413e1a9b224651d0b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?= Date: Tue, 21 Nov 2023 11:25:39 +0100 Subject: [PATCH] CSR user manual: add precise trap description (fix #1217) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: André Sintzoff --- docs/01_cva6_user/CV32A6_Control_Status_Registers.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst b/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst index 18483fe754..f7f3805ff4 100644 --- a/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst +++ b/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst @@ -39,6 +39,9 @@ privileged specification. Reads or writes to a CSR that is not implemented will result in an illegal instruction exception. +Any illegal instruction exception raised by CSR access is precise. +For instance, reading and writing to a read-only CSR will not update the destination register. + .. tip:: This section was auto-generated by **Register Manager** from `Jade Design Automation `_. |logo|