From 2dec551d1683993c39025870bd81f41f2c0fcbee Mon Sep 17 00:00:00 2001 From: Alae Eddine Ez zejjari Date: Fri, 1 Sep 2023 18:02:09 +0200 Subject: [PATCH 1/4] Code_coverage: Add conditions for the MMU Signed-off-by: Alae Eddine Ez zejjari --- core/csr_regfile.sv | 2 +- core/load_store_unit.sv | 2 +- core/load_unit.sv | 57 +++++++++++++++++++++++------------------ core/store_unit.sv | 12 +++++---- 4 files changed, 41 insertions(+), 32 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 14f067c332..fdb14984a6 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1084,7 +1084,7 @@ module csr_regfile import ariane_pkg::*; #( // ------------------------------ // Set the address translation at which the load and stores should occur // we can use the previous values since changing the address translation will always involve a pipeline flush - if (mprv && riscv::vm_mode_t'(satp_q.mode) == riscv::MODE_SV && (mstatus_q.mpp != riscv::PRIV_LVL_M)) + if (ariane_pkg::MMU_PRESENT && mprv && riscv::vm_mode_t'(satp_q.mode) == riscv::MODE_SV && (mstatus_q.mpp != riscv::PRIV_LVL_M)) en_ld_st_translation_d = 1'b1; else // otherwise we go with the regular settings en_ld_st_translation_d = en_translation_o; diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 021761f34f..a3e256db35 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -447,7 +447,7 @@ module load_store_unit import ariane_pkg::*; #( end end - if (en_ld_st_translation_i && lsu_ctrl.overflow) begin + if (ariane_pkg::MMU_PRESENT && en_ld_st_translation_i && lsu_ctrl.overflow) begin if (lsu_ctrl.fu == LOAD) begin misaligned_exception = { diff --git a/core/load_unit.sv b/core/load_unit.sv index e3ba945f45..77d8adf584 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -216,15 +216,17 @@ module load_unit import ariane_pkg::*; #( if (!req_port_i.data_gnt) begin state_d = WAIT_GNT; end else begin - if (dtlb_hit_i && !stall_ni) begin - // we got a grant and a hit on the DTLB so we can send the tag in the next cycle - state_d = SEND_TAG; - pop_ld_o = 1'b1; - // translation valid but this is to NC and the WB is not yet empty. - end else if (dtlb_hit_i && stall_ni) begin - state_d = ABORT_TRANSACTION_NI; - end else begin // TLB miss + if (ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else begin + state_d = ABORT_TRANSACTION_NI; + end end end end else begin @@ -281,16 +283,19 @@ module load_unit import ariane_pkg::*; #( // we finally got a data grant if (req_port_i.data_gnt) begin // so we send the tag in the next cycle - if (dtlb_hit_i && !stall_ni) begin - state_d = SEND_TAG; - pop_ld_o = 1'b1; - // translation valid but this is to NC and the WB is not yet empty. - end else if (dtlb_hit_i && stall_ni) begin - state_d = ABORT_TRANSACTION_NI; - end else begin - // should we not have hit on the TLB abort this transaction an retry later + if (ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin state_d = ABORT_TRANSACTION; + end else begin + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else begin + state_d = ABORT_TRANSACTION_NI; + end end + end // otherwise we keep waiting on our grant end @@ -312,15 +317,17 @@ module load_unit import ariane_pkg::*; #( state_d = WAIT_GNT; end else begin // we got a grant so we can send the tag in the next cycle - if (dtlb_hit_i && !stall_ni) begin - // we got a grant and a hit on the DTLB so we can send the tag in the next cycle - state_d = SEND_TAG; - pop_ld_o = 1'b1; - // translation valid but this is to NC and the WB is not yet empty. - end else if (dtlb_hit_i && stall_ni) begin - state_d = ABORT_TRANSACTION_NI; + if (ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin + state_d = ABORT_TRANSACTION; end else begin - state_d = ABORT_TRANSACTION;// we missed on the TLB -> wait for the translation + if (!stall_ni) begin + // we got a grant and a hit on the DTLB so we can send the tag in the next cycle + state_d = SEND_TAG; + pop_ld_o = 1'b1; + // translation valid but this is to NC and the WB is not yet empty. + end else begin + state_d = ABORT_TRANSACTION_NI; + end end end end else begin @@ -380,7 +387,7 @@ module load_unit import ariane_pkg::*; #( // the output is also valid if we got an exception. An exception arrives one cycle after // dtlb_hit_i is asserted, i.e. when we are in SEND_TAG. Otherwise, the exception // corresponds to the next request that is already being translated (see below). - if (ex_i.valid && (state_q == SEND_TAG)) begin + if(ex_i.valid && (state_q == SEND_TAG)) begin valid_o = 1'b1; ex_o.valid = 1'b1; end diff --git a/core/store_unit.sv b/core/store_unit.sv index 0dd90103aa..cb0f689e22 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -97,7 +97,7 @@ module store_unit import ariane_pkg::*; #( pop_st_o = 1'b1; // check if translation was valid and we have space in the store buffer // otherwise simply stall - if (!dtlb_hit_i) begin + if (ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin state_d = WAIT_TRANSLATION; pop_st_o = 1'b0; end @@ -124,7 +124,7 @@ module store_unit import ariane_pkg::*; #( state_d = VALID_STORE; pop_st_o = 1'b1; - if (!dtlb_hit_i) begin + if(ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin state_d = WAIT_TRANSLATION; pop_st_o = 1'b0; end @@ -153,10 +153,12 @@ module store_unit import ariane_pkg::*; #( // but we know that the store queue is not full as we could only have landed here if // it wasn't full WAIT_TRANSLATION: begin - translation_req_o = 1'b1; + if(ariane_pkg::MMU_PRESENT) begin + translation_req_o = 1'b1; - if (dtlb_hit_i) begin - state_d = IDLE; + if (dtlb_hit_i) begin + state_d = IDLE; + end end end endcase From 69aac5ee2b3ec3ca980cdfb3adbda62a6b293de3 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Sat, 7 Oct 2023 18:37:56 +0200 Subject: [PATCH 2/4] Update load_store_unit.sv --- core/load_store_unit.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index a3e256db35..3f2a05573c 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -447,7 +447,7 @@ module load_store_unit import ariane_pkg::*; #( end end - if (ariane_pkg::MMU_PRESENT && en_ld_st_translation_i && lsu_ctrl.overflow) begin + if (ariane_pkg::MMU_PRESENT && en_ld_st_translation_i && lsu_ctrl.overflow) begin if (lsu_ctrl.fu == LOAD) begin misaligned_exception = { From 51e86d2a632f332c2f226dc36f8ed87597ae4015 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Sat, 7 Oct 2023 18:38:55 +0200 Subject: [PATCH 3/4] Update load_unit.sv --- core/load_unit.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/load_unit.sv b/core/load_unit.sv index 77d8adf584..b233c605ce 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -387,7 +387,7 @@ module load_unit import ariane_pkg::*; #( // the output is also valid if we got an exception. An exception arrives one cycle after // dtlb_hit_i is asserted, i.e. when we are in SEND_TAG. Otherwise, the exception // corresponds to the next request that is already being translated (see below). - if(ex_i.valid && (state_q == SEND_TAG)) begin + if (ex_i.valid && (state_q == SEND_TAG)) begin valid_o = 1'b1; ex_o.valid = 1'b1; end From 730d1cc07bc84da6664e1bb79b920ccadec506db Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Sat, 7 Oct 2023 18:39:29 +0200 Subject: [PATCH 4/4] Update store_unit.sv --- core/store_unit.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/store_unit.sv b/core/store_unit.sv index cb0f689e22..4dc5099d8d 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -124,7 +124,7 @@ module store_unit import ariane_pkg::*; #( state_d = VALID_STORE; pop_st_o = 1'b1; - if(ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin + if (ariane_pkg::MMU_PRESENT && !dtlb_hit_i) begin state_d = WAIT_TRANSLATION; pop_st_o = 1'b0; end