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[DECODER] : Separate between RV32 & RV64 instruction #1613

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AyoubJalali opened this issue Nov 9, 2023 · 4 comments
Closed
1 task done

[DECODER] : Separate between RV32 & RV64 instruction #1613

AyoubJalali opened this issue Nov 9, 2023 · 4 comments
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@fatimasaleem
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Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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@AyoubJalali
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Is there an existing CVA6 bug for this?

  • I have searched the existing bug issues

Bug Description

Still on the same issue, in the line, REV8 has 2 instr[31:20] value to be valid instrcution, but in fact REV8 is a RV64 instruction if instr.instr[31:20] == 12'b011010111000 & it's a RV32 if instr.instr[31:20] == 12'b011010011000, so it sould add a condition on this to improve CC
@AyoubJalali AyoubJalali added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Nov 9, 2023
@JeanRochCoulon
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Hello @AyoubJalali A dediccared PR has been merged concerning this issue. If the issue is fixed, please close it (by indicating the PR number).

@ASintzoff
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No change (except the verible formatting) has been done on that line since the introduction of bitmap RTL code.

@AyoubJalali
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Hello @AyoubJalali A dediccared PR has been merged concerning this issue. If the issue is fixed, please close it (by indicating the PR number).

That's a new one

valentinThomazic pushed a commit to ThalesSiliconSecurity/cva6 that referenced this issue Nov 23, 2023
@JeanRochCoulon
Merge pull request openhwgroup#1613 from AyoubJalali/vp_cvxif
b5f1653 
CVXIF: Verification plan moved to VPTOOL
JeanRochCoulon pushed a commit that referenced this issue Dec 17, 2023
@gullahmed1
resolving issue #1613 (#1714)
8c14b6a
@JeanRochCoulon
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@AyoubJalali #1714 should have fixed this issue. If you confirm, you would have the privilege to close the issue ;-)

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@JeanRochCoulon @ASintzoff @fatimasaleem @AyoubJalali