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[TASK] Condition RTL with RVFI parameter #1441

Closed
1 task done
JeanRochCoulon opened this issue Sep 18, 2023 · 4 comments
Closed
1 task done

[TASK] Condition RTL with RVFI parameter #1441

JeanRochCoulon opened this issue Sep 18, 2023 · 4 comments
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@yanicasa
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Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Component:Verif For issues in the verification environment or test cases (e.g. for testbench, C code, etc.) CV32A60AX Part: Application configuration (former "step1") CV32A65X Part: Embedded configuration Type:Task Project related task

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@JeanRochCoulon
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Is there an existing CVA6 task for this?

  • I have searched the existing task issues

Task Description

Condition RTL with RVFI parameter to remove the related gates from CVA6

Required Changes

RTL modification

Current Status

Todo

Risks

Warning: gate simulation should contain RVFI interface to monitor and stop the simulation

Prerequisites

none

KPI (KEY Performance Indicators)

none

Description of Done

RTL merge in master

Associated PRs

No response
@JeanRochCoulon JeanRochCoulon added Component:Verif For issues in the verification environment or test cases (e.g. for testbench, C code, etc.) CV32A60AX Part: Application configuration (former "step1") CV32A65X Part: Embedded configuration Component:RTL For issues in the RTL (e.g. for files in the rtl directory) and removed Component:Verif For issues in the verification environment or test cases (e.g. for testbench, C code, etc.) labels Sep 18, 2023
zchamski pushed a commit to zchamski/cva6 that referenced this issue Sep 27, 2023
@JeanRochCoulon
Merge pull request openhwgroup#1441 from AyoubJalali/dev/gen_job
3ace6c8 
code coverage: add CI jobs (generated tests & report)
@JeanRochCoulon
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One trial has been done: 6 kgates are saved when removing RVFI from 10B configuration.

@JeanRochCoulon JeanRochCoulon moved this from Todo to In Progress in CVA6 Project Task Board Oct 10, 2023
@JeanRochCoulon
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As @Gchauvon has good idea to implement better RVFI, reassign this task to him.

@JeanRochCoulon JeanRochCoulon added Type:Task Project related task Component:Verif For issues in the verification environment or test cases (e.g. for testbench, C code, etc.) labels Oct 18, 2023
@JeanRochCoulon
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RVFI is 10kgates big. Look at the CV32E where RVFI is bounded, no synthesis impact.

@JeanRochCoulon JeanRochCoulon mentioned this issue Nov 8, 2023
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1 task
@JeanRochCoulon JeanRochCoulon assigned yanicasa and unassigned Gchauvon Nov 30, 2023
@JeanRochCoulon
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CLosed with #1762

@github-project-automation github-project-automation bot moved this from In Progress to Done - Ready for Review in CVA6 Project Task Board May 19, 2024
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@yanicasa yanicasa

Labels
Component:RTL For issues in the RTL (e.g. for files in the rtl directory) Component:Verif For issues in the verification environment or test cases (e.g. for testbench, C code, etc.) CV32A60AX Part: Application configuration (former "step1") CV32A65X Part: Embedded configuration Type:Task Project related task
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CVA6 Project Task Board
Status: Done - Ready for Review
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3 participants
@JeanRochCoulon @yanicasa @Gchauvon