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Spike : Unrecognized CSR #1427

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AyoubJalali opened this issue Jun 7, 2023 · 4 comments
Closed

Spike : Unrecognized CSR #1427

AyoubJalali opened this issue Jun 7, 2023 · 4 comments
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@AyoubJalali
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Hello,
As i know the ICACHE_CSR is implemented in the STEP1 configuration, so i generate a test with a csr instruction with ICACHE_CSR = 12'b700, the spike model raised an exception, because it didn't recognize the CSR (i don't think it's implemented), but the CVA6 did not raised an exception.

to reproduce the bug :

  • Add the yaml description of the test in cva6_base_testlist.yaml

  • test: riscv_rand_jump_illegal_test
    description: >
    Jump among large number of sub-programs, stress testing iTLB operations.
    gen_opts: >
    +instr_cnt=300
    +num_of_sub_program=0
    +directed_instr_0=riscv_load_store_rand_instr_stream,10
    +directed_instr_1=riscv_jal_instr,20
    +illegal_instr_ratio=100
    +tvec_alignment=8
    iterations: 2
    gen_test: cva6_instr_base_test_c
    rtl_test: core_base_test

and run the commend :

python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_rand_jump_illegal_test --iss_yaml cva6.yaml --target cv32a60x --iss=vcs-uvm,spike --simulator_yaml ../env/corev-dv/simulator.yaml --iss_timeout 300 -i 1 --seed 1472969439

with these version :

  1. core-v-verif -> branch : cva6/dev
  2. core-v-core/cva6 -> branch : master
  3. sim/dv (riscv-dv) -> branch : 0ce85d3
@spidugu444
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@AyoubJalali, The CSR address configuration for ICACHE and DCACHE has recently updated to ICACHE: 0x700==>0x7C0 and DCACHE: 0X701==>0x7C1.
These custom CSRs has not been implemented on spike end, so it is raising exception.
For more information please refer this issue.

@MikeOpenHWGroup MikeOpenHWGroup transferred this issue from openhwgroup/core-v-verif Sep 14, 2023
Abdulwadoodd pushed a commit to 10x-Engineers/cva6 that referenced this issue Sep 15, 2023
…d-tracing

[tracing] Add uniform tracing support for VCS and Verilator.

The process of waveform generation is controlled by two environment variables:
    * TRACE_COMPACT (default: empty): When non-empty, activates generation and collection of the most compact waveform format available on the given platform, usually at the expense of compilation and simulation speed.
    * TRACE_FAST (default: empty): When non-empty, activates generation and collection of the fastest waveform format available on the chosen simulation platform (as selected by setting variable DV_SIMULATORS).
@zchamski
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I am developing a proof-of-concept solution to add arbitrary CSRs via Spike extensions (spike --extension=cv32a6embedded ...). This could be the generic approach to add CSRs as apposed to disabling unavailable ones (see #1599, #1145).

@MarioOpenHWGroup
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Already merged by @zchamski openhwgroup/core-v-verif#2334

@zchamski
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zchamski commented Apr 4, 2024

The ICACHE and DCACHE CSRs are now supported in Spike through Spike extension cv32a60x. While the extension may get renamed (currently it only provides the two CSRs mentioned), I propose to close this issue.

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