From f332688fc015de0f36390958211c6f77778a7bb5 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Fri, 23 Feb 2024 23:09:11 +0100 Subject: [PATCH] Complete Design Document (#1865) --- core/alu.sv | 13 +- core/branch_unit.sv | 30 ++- core/csr_buffer.sv | 26 +- core/csr_regfile.sv | 8 +- core/cva6.sv | 2 +- core/cvxif_fu.sv | 17 +- core/ex_stage.sv | 27 +- core/include/config_pkg.sv | 32 +-- core/issue_read_operands.sv | 93 ++++--- core/issue_stage.sv | 20 +- core/load_store_unit.sv | 100 ++++--- core/load_unit.sv | 46 +++- core/lsu_bypass.sv | 9 + core/mult.sv | 9 + core/multiplier.sv | 11 + core/scoreboard.sv | 61 +++-- core/serdiv.sv | 18 +- core/store_unit.sv | 45 +++- docs/04_cv32a65x_design/images/bht.png | Bin 113873 -> 76434 bytes .../images/frontend_modules.png | Bin 29540 -> 10504 bytes .../source/cv32a6_execute.rst | 84 ++++-- .../source/cv32a6_frontend.rst | 135 ++++++---- .../source/cva6_commit_stage.rst | 8 +- .../source/cva6_id_stage.rst | 13 +- .../source/cva6_issue_stage.rst | 14 +- docs/04_cv32a65x_design/source/mmu.rst | 15 +- .../source/parameters_cv32a65x.rst | 32 +-- docs/04_cv32a65x_design/source/port_alu.rst | 51 ++++ docs/04_cv32a65x_design/source/port_bht.rst | 3 +- .../source/port_branch_unit.rst | 103 ++++++++ docs/04_cv32a65x_design/source/port_btb.rst | 3 +- .../source/port_commit_stage.rst | 64 ++--- .../source/port_compressed_decoder.rst | 4 +- .../source/port_controller.rst | 34 +-- .../source/port_csr_buffer.rst | 75 ++++++ .../source/port_csr_regfile.rst | 154 ++--------- docs/04_cv32a65x_design/source/port_cva6.rst | 11 +- .../source/port_cvxif_fu.rst | 103 ++++++++ .../source/port_decoder.rst | 24 +- .../source/port_ex_stage.rst | 160 +++++------ .../source/port_frontend.rst | 5 +- .../source/port_id_stage.rst | 24 +- .../source/port_instr_queue.rst | 4 +- .../source/port_instr_realign.rst | 4 +- .../source/port_instr_scan.rst | 4 +- .../source/port_issue_read_operands.rst | 248 ++++++++---------- .../source/port_issue_stage.rst | 35 +-- .../source/port_load_store_unit.rst | 209 +++++++++++++++ .../source/port_load_unit.rst | 153 +++++++++++ .../source/port_lsu_bypass.rst | 75 ++++++ docs/04_cv32a65x_design/source/port_mult.rst | 75 ++++++ .../source/port_multiplier.rst | 87 ++++++ docs/04_cv32a65x_design/source/port_ras.rst | 4 +- .../source/port_scoreboard.rst | 195 +++++++------- .../04_cv32a65x_design/source/port_serdiv.rst | 99 +++++++ .../source/port_store_unit.rst | 169 ++++++++++++ docs/scripts/define_blacklist.py | 63 ++++- docs/scripts/spec_builder.py | 27 +- 58 files changed, 2217 insertions(+), 920 deletions(-) create mode 100644 docs/04_cv32a65x_design/source/port_alu.rst create mode 100644 docs/04_cv32a65x_design/source/port_branch_unit.rst create mode 100644 docs/04_cv32a65x_design/source/port_csr_buffer.rst create mode 100644 docs/04_cv32a65x_design/source/port_cvxif_fu.rst create mode 100644 docs/04_cv32a65x_design/source/port_load_store_unit.rst create mode 100644 docs/04_cv32a65x_design/source/port_load_unit.rst create mode 100644 docs/04_cv32a65x_design/source/port_lsu_bypass.rst create mode 100644 docs/04_cv32a65x_design/source/port_mult.rst create mode 100644 docs/04_cv32a65x_design/source/port_multiplier.rst create mode 100644 docs/04_cv32a65x_design/source/port_serdiv.rst create mode 100644 docs/04_cv32a65x_design/source/port_store_unit.rst diff --git a/core/alu.sv b/core/alu.sv index a928725ebc..e57e0d1fd5 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -23,11 +23,16 @@ module alu #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input fu_data_t fu_data_i, + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // ALU result - ISSUE_STAGE output riscv::xlen_t result_o, - output logic alu_branch_res_o + // ALU branch compare result - branch_unit + output logic alu_branch_res_o ); riscv::xlen_t operand_a_rev; diff --git a/core/branch_unit.sv b/core/branch_unit.sv index d04adb7308..f7070e100b 100644 --- a/core/branch_unit.sv +++ b/core/branch_unit.sv @@ -15,22 +15,34 @@ module branch_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // Debug mode state - CSR_REGFILE input logic debug_mode_i, + // FU data needed to execute instruction - ISSUE_STAGE input ariane_pkg::fu_data_t fu_data_i, - input logic [riscv::VLEN-1:0] pc_i, // PC of instruction + // Instruction PC - ISSUE_STAGE + input logic [riscv::VLEN-1:0] pc_i, + // Instruction is compressed - ISSUE_STAGE input logic is_compressed_instr_i, - input logic fu_valid_i, // any functional unit is valid, check that there is no accidental mis-predict + // any functional unit is valid, check that there is no accidental mis-predict - TO_BE_COMPLETED + input logic fu_valid_i, + // Branch unit instruction is valid - ISSUE_STAGE input logic branch_valid_i, - input logic branch_comp_res_i, // branch comparison result from ALU + // ALU branch compare result - ALU + input logic branch_comp_res_i, + // Brach unit result - ISSUE_STAGE output logic [riscv::VLEN-1:0] branch_result_o, - - input ariane_pkg::branchpredict_sbe_t branch_predict_i, // this is the address we predicted - output ariane_pkg::bp_resolve_t resolved_branch_o, // this is the actual address we are targeting - output logic resolve_branch_o, // to ID to clear that we resolved the branch and we can - // accept new entries to the scoreboard - output ariane_pkg::exception_t branch_exception_o // branch exception out + // Information of branch prediction - ISSUE_STAGE + input ariane_pkg::branchpredict_sbe_t branch_predict_i, + // Signaling that we resolved the branch - ISSUE_STAGE + output ariane_pkg::bp_resolve_t resolved_branch_o, + // Branch is resolved, new entries can be accepted by scoreboard - ID_STAGE + output logic resolve_branch_o, + // Branch exception out - TO_BE_COMPLETED + output ariane_pkg::exception_t branch_exception_o ); logic [riscv::VLEN-1:0] target_address; logic [riscv::VLEN-1:0] next_pc; diff --git a/core/csr_buffer.sv b/core/csr_buffer.sv index 57be04dda4..8c93052b69 100644 --- a/core/csr_buffer.sv +++ b/core/csr_buffer.sv @@ -19,18 +19,24 @@ module csr_buffer #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush CSR - CONTROLLER input logic flush_i, - + // FU data needed to execute instruction - ISSUE_STAGE input fu_data_t fu_data_i, - - output logic csr_ready_o, // FU is ready e.g. not busy - input logic csr_valid_i, // Input is valid - output riscv::xlen_t csr_result_o, - input logic csr_commit_i, // commit the pending CSR OP - // to CSR file - output logic [11:0] csr_addr_o // CSR address to commit stage + // CSR FU is ready - ISSUE_STAGE + output logic csr_ready_o, + // CSR instruction is valid - ISSUE_STAGE + input logic csr_valid_i, + // CSR buffer result - ISSUE_STAGE + output riscv::xlen_t csr_result_o, + // commit the pending CSR OP - TO_BE_COMPLETED + input logic csr_commit_i, + // CSR address to write - COMMIT_STAGE + output logic [11:0] csr_addr_o ); // this is a single entry store buffer for the address of the CSR // which we are going to need in the commit stage diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 416b28c4f6..c6cdf72ac1 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -83,15 +83,15 @@ module csr_regfile output riscv::xs_t vs_o, // interrupt management to id stage - ID_STAGE output irq_ctrl_t irq_ctrl_o, - // enable VA translation - EX_STAGE + // Enable virtual address translation - EX_STAGE output logic en_translation_o, - // enable VA translation for load and stores - EX_STAGE + // Enable virtual address translation for load and stores - EX_STAGE output logic en_ld_st_translation_o, // Privilege level at which load and stores should happen - EX_STAGE output riscv::priv_lvl_t ld_st_priv_lvl_o, - // TO_BE_COMPLETED - EX_STAGE + // Supervisor User Memory - EX_STAGE output logic sum_o, - // TO_BE_COMPLETED - EX_STAGE + // Make Executable Readable - EX_STAGE output logic mxr_o, // TO_BE_COMPLETED - EX_STAGE output logic [ riscv::PPNW-1:0] satp_ppn_o, diff --git a/core/cva6.sv b/core/cva6.sv index 385a487908..9b40998ebf 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -131,7 +131,7 @@ module cva6 input logic time_irq_i, // Debug (async) request - SUBSYSTEM input logic debug_req_i, - // Probes to build RVFI, can be left open when not used - SUBSYSTEM + // Probes to build RVFI, can be left open when not used - RVFI output rvfi_probes_t rvfi_probes_o, // CVXIF request - SUBSYSTEM output cvxif_req_t cvxif_req_o, diff --git a/core/cvxif_fu.sv b/core/cvxif_fu.sv index ebe180621c..b1dabfcd0c 100644 --- a/core/cvxif_fu.sv +++ b/core/cvxif_fu.sv @@ -15,22 +15,33 @@ module cvxif_fu #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // FU data needed to execute instruction - ISSUE_STAGE input fu_data_t fu_data_i, + // Current privilege mode - CSR_REGFILE input riscv::priv_lvl_t priv_lvl_i, - //from issue + // CVXIF instruction is valid - ISSUE_STAGE input logic x_valid_i, + // CVXIF is ready - ISSUE_STAGE output logic x_ready_o, + // Offloaded instruction - ISSUE_STAGE input logic [ 31:0] x_off_instr_i, - //to writeback + // CVXIF transaction ID - ISSUE_STAGE output logic [TRANS_ID_BITS-1:0] x_trans_id_o, + // CVXIF exception - ISSUE_STAGE output exception_t x_exception_o, + // CVXIF FU result - ISSUE_STAGE output riscv::xlen_t x_result_o, + // CVXIF result valid - ISSUE_STAGE output logic x_valid_o, + // CVXIF write enable - ISSUE_STAGE output logic x_we_o, - //to coprocessor + // CVXIF request - SUBSYSTEM output cvxif_pkg::cvxif_req_t cvxif_req_o, + // CVXIF response - SUBSYSTEM input cvxif_pkg::cvxif_resp_t cvxif_resp_i ); localparam X_NUM_RS = ariane_pkg::NR_RGPR_PORTS; diff --git a/core/ex_stage.sv b/core/ex_stage.sv index e31f7b2670..d6237dcc24 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -26,7 +26,7 @@ module ex_stage input logic rst_ni, // Fetch flush request - CONTROLLER input logic flush_i, - // TO_BE_COMPLETED - CSR_REGFILE + // Debug mode is enabled - CSR_REGFILE input logic debug_mode_i, // rs1 forwarding - ISSUE_STAGE input logic [riscv::VLEN-1:0] rs1_forwarding_i, @@ -38,11 +38,11 @@ module ex_stage input logic [riscv::VLEN-1:0] pc_i, // Report whether isntruction is compressed - ISSUE_STAGE input logic is_compressed_instr_i, - // TO_BE_COMPLETED - ISSUE_STAGE + // Fixed Latency Unit result - ISSUE_STAGE output riscv::xlen_t flu_result_o, // ID of the scoreboard entry at which a=to write back - ISSUE_STAGE output logic [TRANS_ID_BITS-1:0] flu_trans_id_o, - // TO_BE_COMPLETED - ISSUE_STAGE + // Fixed Latency Unit exception - ISSUE_STAGE output exception_t flu_exception_o, // FLU is ready - ISSUE_STAGE output logic flu_ready_o, @@ -62,7 +62,7 @@ module ex_stage input logic csr_valid_i, // CSR address to write - COMMIT_STAGE output logic [11:0] csr_addr_o, - // TO_BE_COMPLETED - COMMIT_STAGE + // CSR commit - COMMIT_STAGE input logic csr_commit_i, // MULT instruction is valid - ISSUE_STAGE input logic mult_valid_i, @@ -86,11 +86,11 @@ module ex_stage output logic [TRANS_ID_BITS-1:0] store_trans_id_o, // Exception generated by store instruction - ISSUE_STAGE output exception_t store_exception_o, - // TO_BE_COMPLETED - COMMIT_STAGE + // LSU commit - COMMIT_STAGE input logic lsu_commit_i, // Commit queue ready to accept another commit request - COMMIT_STAGE output logic lsu_commit_ready_o, - // TO_BE_COMPLETED - COMMIT_STAGE + // Commit transaction ID - COMMIT_STAGE input logic [TRANS_ID_BITS-1:0] commit_tran_id_i, // TO_BE_COMPLETED - ACC_DISPATCHER input logic stall_st_pending_i, @@ -140,11 +140,11 @@ module ex_stage input cvxif_pkg::cvxif_resp_t cvxif_resp_i, // accelerate port result is valid - ACC_DISPATCHER input logic acc_valid_i, - // TO_BE_COMPLETED - CSR_REGFILE + // Enable virtual memory translation - CSR_REGFILE input logic enable_translation_i, - // TO_BE_COMPLETED - CSR_REGFILE + // Enable virtual memory translation for load/stores - CSR_REGFILE input logic en_ld_st_translation_i, - // TO_BE_COMPLETED - CONTROLLER + // Flush TLB - CONTROLLER input logic flush_tlb_i, // Privilege mode - CSR_REGFILE input riscv::priv_lvl_t priv_lvl_i, @@ -162,18 +162,17 @@ module ex_stage input icache_arsp_t icache_areq_i, // icache translation request - CACHE output icache_areq_t icache_areq_o, - // TO_BE_COMPLETED - CACHE - // interface to dcache + // Data cache request ouput - CACHE input dcache_req_o_t [2:0] dcache_req_ports_i, - // TO_BE_COMPLETED - CACHE + // Data cache request input - CACHE output dcache_req_i_t [2:0] dcache_req_ports_o, - // TO_BE_COMPLETED - CACHE + // Write buffer is empty - CACHE input logic dcache_wbuffer_empty_i, // TO_BE_COMPLETED - CACHE input logic dcache_wbuffer_not_ni_i, // AMO request - CACHE output amo_req_t amo_req_o, - // AMO response from cache - CACHE + // AMO response - CACHE input amo_resp_t amo_resp_i, // To count the instruction TLB misses - PERF_COUNTERS output logic itlb_miss_o, diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index bb06c35aaf..f202411bb0 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -46,15 +46,15 @@ package config_pkg; int unsigned AxiIdWidth; // AXI User width int unsigned AxiUserWidth; - // TO_BE_COMPLETED + // Load buffer entry buffer int unsigned NrLoadBufEntries; - // FPU is enabled + // Floating Point bit FpuEn; - // TO_BE_COMPLETED + // Non standard 16bits Floating Point bit XF16; - // TO_BE_COMPLETED + // Non standard 16bits Floating Point Alt bit XF16ALT; - // TO_BE_COMPLETED + // Non standard 8bits Floating Point bit XF8; // Atomic RISC-V extension bit RVA; @@ -66,33 +66,33 @@ package config_pkg; bit RVC; // Zcb RISC-V extension bit RVZCB; - // TO_BE_COMPLETED + // Non standard Vector Floating Point bit XFVec; // CV-X-IF coprocessor interface is supported bit CvxifEn; - // Zicond RISC-V extension is enabled + // Zicond RISC-V extension bit ZiCondExtEn; // Single precision FP RISC-V extension bit RVF; // Double precision FP RISC-V extension bit RVD; - // Floating point is present + // Floating Point is present bit FpPresent; - // TO_BE_COMPLETED + // Non standard Floating is Point present bit NSX; - // TO_BE_COMPLETED + // Floating Point lenght int unsigned FLen; - // Vector floating point extension + // Vector Floating Point extension bit RVFVec; - // 16 bits vector floating point extension + // 16 bits vector Floating Point extension bit XF16Vec; - // TO_BE_COMPLETED + // 16 bits vector Floating Point Alt extension bit XF16ALTVec; - // 8 bits vector floating point extension + // 8 bits vector Floating Point extension bit XF8Vec; // TO_BE_COMPLETED int unsigned NrRgprPorts; - // TO_BE_COMPLETED + // Function Unit write back port number int unsigned NrWbPorts; // Accelerate Port coprocessor interface bit EnableAccelerator; @@ -144,7 +144,7 @@ package config_pkg; logic [NrMaxRules-1:0][63:0] CachedRegionLength; // Maximum number of outstanding stores int unsigned MaxOutstandingStores; - // Debug mode + // Debug support bit DebugEn; // Non idem potency bit NonIdemPotenceEn; diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index b62d016b88..a46bc81fe5 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -20,69 +20,96 @@ module issue_read_operands parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rs3_len_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - // flush + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush - CONTROLLER input logic flush_i, - // stall + // Stall inserted by Acc dispatcher - ACC_DISPATCHER input logic stall_i, - // coming from decoder + // TO_BE_COMPLETED - TO_BE_COMPLETED input scoreboard_entry_t issue_instr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [31:0] orig_instr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic issue_instr_valid_i, + // Issue stage acknowledge - TO_BE_COMPLETED output logic issue_ack_o, - // lookup rd in scoreboard + // rs1 operand address - scoreboard output logic [REG_ADDR_SIZE-1:0] rs1_o, + // rs1 operand - scoreboard input riscv::xlen_t rs1_i, + // rs1 operand is valid - scoreboard input logic rs1_valid_i, + // rs2 operand address - scoreboard output logic [REG_ADDR_SIZE-1:0] rs2_o, + // rs2 operand - scoreboard input riscv::xlen_t rs2_i, + // rs2 operand is valid - scoreboard input logic rs2_valid_i, + // rs3 operand address - scoreboard output logic [REG_ADDR_SIZE-1:0] rs3_o, + // rs3 operand - scoreboard input rs3_len_t rs3_i, + // rs3 operand is valid - scoreboard input logic rs3_valid_i, // get clobber input + // TO_BE_COMPLETED - TO_BE_COMPLETED input fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_i, - // To FU, just single issue for now + // TO_BE_COMPLETED - TO_BE_COMPLETED output fu_data_t fu_data_o, - output riscv::xlen_t rs1_forwarding_o, // unregistered version of fu_data_o.operanda - output riscv::xlen_t rs2_forwarding_o, // unregistered version of fu_data_o.operandb + // Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED + output riscv::xlen_t rs1_forwarding_o, + // Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED + output riscv::xlen_t rs2_forwarding_o, + // Instruction pc - TO_BE_COMPLETED output logic [riscv::VLEN-1:0] pc_o, + // Is compressed instruction - TO_BE_COMPLETED output logic is_compressed_instr_o, - // ALU 1 - input logic flu_ready_i, // Fixed latency unit ready to accept a new request - output logic alu_valid_o, // Output is valid - // Branches and Jumps - output logic branch_valid_o, // this is a valid branch instruction + // Fixed Latency Unit ready to accept new request - TO_BE_COMPLETED + input logic flu_ready_i, + // ALU output is valid - TO_BE_COMPLETED + output logic alu_valid_o, + // Branch instruction is valid - TO_BE_COMPLETED + output logic branch_valid_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output branchpredict_sbe_t branch_predict_o, - // LSU - input logic lsu_ready_i, // FU is ready - output logic lsu_valid_o, // Output is valid - // MULT - output logic mult_valid_o, // Output is valid - // FPU - input logic fpu_ready_i, // FU is ready - output logic fpu_valid_o, // Output is valid - output logic [1:0] fpu_fmt_o, // FP fmt field from instr. - output logic [2:0] fpu_rm_o, // FP rm field from instr. - // CSR - output logic csr_valid_o, // Output is valid - // CVXIF + // Load Store Unit is ready - TO_BE_COMPLETED + input logic lsu_ready_i, + // Load Store Unit result is valid - TO_BE_COMPLETED + output logic lsu_valid_o, + // Mult result is valid - TO_BE_COMPLETED + output logic mult_valid_o, + // FPU is ready - TO_BE_COMPLETED + input logic fpu_ready_i, + // FPU result is valid - TO_BE_COMPLETED + output logic fpu_valid_o, + // FPU fmt field from instruction - TO_BE_COMPLETED + output logic [1:0] fpu_fmt_o, + // FPU rm field from isntruction - TO_BE_COMPLETED + output logic [2:0] fpu_rm_o, + // CSR result is valid - TO_BE_COMPLETED + output logic csr_valid_o, + // CVXIF result is valid - TO_BE_COMPLETED output logic cvxif_valid_o, + // CVXIF is ready - TO_BE_COMPLETED input logic cvxif_ready_i, + // CVXIF offloaded instruction - TO_BE_COMPLETED output logic [31:0] cvxif_off_instr_o, - // commit port + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, - output logic stall_issue_o // stall signal, we do not want to fetch any more entries - // committing instruction instruction - // from scoreboard - // input scoreboard_entry commit_instr_i, - // output logic commit_ack_o + // Stall signal, we do not want to fetch any more entries - TO_BE_COMPLETED + output logic stall_issue_o ); logic stall; logic fu_busy; // functional unit is busy diff --git a/core/issue_stage.sv b/core/issue_stage.sv index d046b24f68..e5dfa3b51b 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -47,15 +47,15 @@ module issue_stage output [riscv::VLEN-1:0] rs2_forwarding_o, // FU data useful to execute instruction - EX_STAGE output fu_data_t fu_data_o, - // TO_BE_COMPLETED - EX_STAGE + // Program Counter - EX_STAGE output logic [riscv::VLEN-1:0] pc_o, // Is compressed instruction - EX_STAGE output logic is_compressed_instr_o, - // TO_BE_COMPLETED - EX_STAGE + // Fixed Latency Unit is ready - EX_STAGE input logic flu_ready_i, // ALU FU is valid - EX_STAGE output logic alu_valid_o, - // TO_BE_COMPLETED - EX_STAGE + // Signaling that we resolved the branch - EX_STAGE input logic resolve_branch_i, // Load store unit FU is ready - EX_STAGE input logic lsu_ready_i, @@ -87,9 +87,9 @@ module issue_stage output scoreboard_entry_t issue_instr_o, // TO_BE_COMPLETED - ACC_DISPATCHER output logic issue_instr_hs_o, - // TO_BE_COMPLETED - EX_STAGE + // Transaction ID - EX_STAGE input logic [CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] trans_id_i, - // TO_BE_COMPLETED - EX_STAGE + // The branch engine uses the write back from the ALU - EX_STAGE input bp_resolve_t resolved_branch_i, // TO_BE_COMPLETED - EX_STAGE input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, @@ -97,19 +97,19 @@ module issue_stage input exception_t [CVA6Cfg.NrWbPorts-1:0] ex_ex_i, // TO_BE_COMPLETED - EX_STAGE input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, - // TO_BE_COMPLETED - EX_STAGE + // CVXIF write enable - EX_STAGE input logic x_we_i, // TO_BE_COMPLETED - EX_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_i, // TO_BE_COMPLETED - EX_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i, - // TO_BE_COMPLETED - EX_STAGE + // GPR write enable - EX_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_i, - // TO_BE_COMPLETED - EX_STAGE + // FPR write enable - EX_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, - // TO_BE_COMPLETED - COMMIT_STAGE + // Instructions to commit - COMMIT_STAGE output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, - // TO_BE_COMPLETED - COMMIT_STAGE + // Commit acknowledge - COMMIT_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Issue stall - PERF_COUNTERS output logic stall_issue_o, diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 9a5c9245c6..cb899c6c05 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -19,65 +19,103 @@ module load_store_unit parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned ASID_WIDTH = 1 ) ( - input logic clk_i, - input logic rst_ni, - input logic flush_i, - input logic stall_st_pending_i, + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic flush_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic stall_st_pending_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic no_st_pending_o, - input logic amo_valid_commit_i, - - input fu_data_t fu_data_i, - output logic lsu_ready_o, // FU is ready e.g. not busy - input logic lsu_valid_i, // Input is valid - - output logic [TRANS_ID_BITS-1:0] load_trans_id_o, // ID of scoreboard entry at which to write back + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic amo_valid_commit_i, + // FU data needed to execute instruction - ISSUE_STAGE + input fu_data_t fu_data_i, + // Load Store Unit is ready - ISSUE_STAGE + output logic lsu_ready_o, + // Load Store Unit instruction is valid - ISSUE_STAGE + input logic lsu_valid_i, + + // Load transaction ID - ISSUE_STAGE + output logic [TRANS_ID_BITS-1:0] load_trans_id_o, + // Load result - ISSUE_STAGE output riscv::xlen_t load_result_o, + // Load result is valid - ISSUE_STAGE output logic load_valid_o, - output exception_t load_exception_o, // to WB, signal exception status LD exception + // Load exception - ISSUE_STAGE + output exception_t load_exception_o, - output logic [TRANS_ID_BITS-1:0] store_trans_id_o, // ID of scoreboard entry at which to write back + // Store transaction ID - ISSUE_STAGE + output logic [TRANS_ID_BITS-1:0] store_trans_id_o, + // Store result - ISSUE_STAGE output riscv::xlen_t store_result_o, + // Store result is valid - ISSUE_STAGE output logic store_valid_o, - output exception_t store_exception_o, // to WB, signal exception status ST exception - - input logic commit_i, // commit the pending store - output logic commit_ready_o, // commit queue is ready to accept another commit request + // Store exception - ISSUE_STAGE + output exception_t store_exception_o, + + // Commit the first pending store - TO_BE_COMPLETED + input logic commit_i, + // Commit queue is ready to accept another commit request - TO_BE_COMPLETED + output logic commit_ready_o, + // Commit transaction ID - TO_BE_COMPLETED input logic [TRANS_ID_BITS-1:0] commit_tran_id_i, - input logic enable_translation_i, // enable virtual memory translation - input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores + // Enable virtual memory translation - TO_BE_COMPLETED + input logic enable_translation_i, + // Enable virtual memory translation for load/stores - TO_BE_COMPLETED + input logic en_ld_st_translation_i, - // icache translation requests + // Instruction cache input request - CACHES input icache_arsp_t icache_areq_i, + // Instruction cache output request - CACHES output icache_areq_t icache_areq_o, - input riscv::priv_lvl_t priv_lvl_i, // From CSR register file - input riscv::priv_lvl_t ld_st_priv_lvl_i, // From CSR register file - input logic sum_i, // From CSR register file - input logic mxr_i, // From CSR register file - input logic [riscv::PPNW-1:0] satp_ppn_i, // From CSR register file - input logic [ ASID_WIDTH-1:0] asid_i, // From CSR register file + // Current privilege mode - CSR_REGFILE + input riscv::priv_lvl_t priv_lvl_i, + // Privilege level at which load and stores should happen - CSR_REGFILE + input riscv::priv_lvl_t ld_st_priv_lvl_i, + // Supervisor User Memory - CSR_REGFILE + input logic sum_i, + // Make Executable Readable - CSR_REGFILE + input logic mxr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [riscv::PPNW-1:0] satp_ppn_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [ ASID_WIDTH-1:0] asid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [ ASID_WIDTH-1:0] asid_to_be_flushed_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i, + // TLB flush - CONTROLLER input logic flush_tlb_i, - // Performance counters + // Instruction TLB miss - PERF_COUNTERS output logic itlb_miss_o, + // Data TLB miss - PERF_COUNTERS output logic dtlb_miss_o, - // interface to dcache + // Data cache request output - CACHES input dcache_req_o_t [ 2:0] dcache_req_ports_i, + // Data cache request input - CACHES output dcache_req_i_t [ 2:0] dcache_req_ports_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic dcache_wbuffer_empty_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic dcache_wbuffer_not_ni_i, - // AMO interface + // AMO request - CACHE output amo_req_t amo_req_o, + // AMO response - CACHE input amo_resp_t amo_resp_i, - // PMP + // PMP configuration - CSR_REGFILE input riscv::pmpcfg_t [15:0] pmpcfg_i, + // PMP address - CSR_REGFILE input logic [15:0][riscv::PLEN-3:0] pmpaddr_i, - //RVFI + // RVFI inforamtion - RVFI output lsu_ctrl_t rvfi_lsu_ctrl_o, + // RVFI information - RVFI output [riscv::PLEN-1:0] rvfi_mem_paddr_o ); // data is misaligned diff --git a/core/load_unit.sv b/core/load_unit.sv index 512b498cf3..2b5bec9446 100644 --- a/core/load_unit.sv +++ b/core/load_unit.sv @@ -23,33 +23,51 @@ module load_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic flush_i, - // load unit input port + // Load unit input port - TO_BE_COMPLETED input logic valid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input lsu_ctrl_t lsu_ctrl_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic pop_ld_o, - // load unit output port + // Load unit result is valid - TO_BE_COMPLETED output logic valid_o, + // Load transaction ID - TO_BE_COMPLETED output logic [TRANS_ID_BITS-1:0] trans_id_o, + // Load result - TO_BE_COMPLETED output riscv::xlen_t result_o, + // Load exception - TO_BE_COMPLETED output exception_t ex_o, - // MMU -> Address Translation - output logic translation_req_o, // request address translation - output logic [riscv::VLEN-1:0] vaddr_o, // virtual address out - input logic [riscv::PLEN-1:0] paddr_i, // physical address in - input exception_t ex_i, // exception which may has happened earlier. for example: mis-aligned exception - input logic dtlb_hit_i, // hit on the dtlb, send in the same cycle as the request - input logic [riscv::PPNW-1:0] dtlb_ppn_i, // ppn on the dtlb, send in the same cycle as the request - // address checker + // Request address translation - TO_BE_COMPLETED + output logic translation_req_o, + // Virtual address - TO_BE_COMPLETED + output logic [riscv::VLEN-1:0] vaddr_o, + // Physical address - TO_BE_COMPLETED + input logic [riscv::PLEN-1:0] paddr_i, + // Excepted which appears before load - TO_BE_COMPLETED + input exception_t ex_i, + // Data TLB hit - lsu + input logic dtlb_hit_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED + input logic [riscv::PPNW-1:0] dtlb_ppn_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic [11:0] page_offset_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic page_offset_matches_i, - input logic store_buffer_empty_i, // the entire store-buffer is empty + // Store buffer is empty - TO_BE_COMPLETED + input logic store_buffer_empty_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [TRANS_ID_BITS-1:0] commit_tran_id_i, - // D$ interface + // Data cache request out - CACHES input dcache_req_o_t req_port_i, + // Data cache request in - CACHES output dcache_req_i_t req_port_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic dcache_wbuffer_not_ni_i ); enum logic [3:0] { diff --git a/core/lsu_bypass.sv b/core/lsu_bypass.sv index 96f6d50252..5790c73a95 100644 --- a/core/lsu_bypass.sv +++ b/core/lsu_bypass.sv @@ -28,16 +28,25 @@ module lsu_bypass #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic flush_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input lsu_ctrl_t lsu_req_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic lsu_req_valid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic pop_ld_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic pop_st_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output lsu_ctrl_t lsu_ctrl_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic ready_o ); diff --git a/core/mult.sv b/core/mult.sv index 7270389569..dcb0fa6a3c 100644 --- a/core/mult.sv +++ b/core/mult.sv @@ -5,14 +5,23 @@ module mult #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // Flush - CONTROLLER input logic flush_i, + // FU data needed to execute instruction - ISSUE_STAGE input fu_data_t fu_data_i, + // Mult instruction is valid - ISSUE_STAGE input logic mult_valid_i, + // Mult result - ISSUE_STAGE output riscv::xlen_t result_o, + // Mult result is valid - ISSUE_STAGE output logic mult_valid_o, + // Mutl is ready - ISSUE_STAGE output logic mult_ready_o, + // Mult transaction ID - ISSUE_STAGE output logic [TRANS_ID_BITS-1:0] mult_trans_id_o ); logic mul_valid; diff --git a/core/multiplier.sv b/core/multiplier.sv index e13d614749..bdcd36e884 100644 --- a/core/multiplier.sv +++ b/core/multiplier.sv @@ -20,16 +20,27 @@ module multiplier #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // Multiplier transaction ID - Mult input logic [TRANS_ID_BITS-1:0] trans_id_i, + // Multiplier instruction is valid - Mult input logic mult_valid_i, + // Multiplier operation - Mult input fu_op operation_i, + // A operand - Mult input riscv::xlen_t operand_a_i, + // B operand - Mult input riscv::xlen_t operand_b_i, + // Multiplier result - Mult output riscv::xlen_t result_o, + // Mutliplier result is valid - Mult output logic mult_valid_o, + // Multiplier FU is ready - Mult output logic mult_ready_o, + // Multiplier transaction ID - Mult output logic [TRANS_ID_BITS-1:0] mult_trans_id_o ); // Carry-less multiplication diff --git a/core/scoreboard.sv b/core/scoreboard.sv index d5c06848e7..568a4aa7ef 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -16,56 +16,87 @@ module scoreboard #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rs3_len_t = logic ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic sb_full_o, - input logic flush_unissued_instr_i, // flush only un-issued instructions - input logic flush_i, // flush whole scoreboard - input logic unresolved_branch_i, // we have an unresolved branch - // list of clobbered registers to issue stage + // Flush only un-issued instructions - TO_BE_COMPLETED + input logic flush_unissued_instr_i, + // Flush whole scoreboard - TO_BE_COMPLETED + input logic flush_i, + // We have an unresolved branch - TO_BE_COMPLETED + input logic unresolved_branch_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output ariane_pkg::fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_gpr_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output ariane_pkg::fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_fpr_o, - // regfile like interface to operand read stage + // rs1 operand address - issue_read_operands input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i, + // rs1 operand - issue_read_operands output riscv::xlen_t rs1_o, + // rs1 operand is valid - issue_read_operands output logic rs1_valid_o, + // rs2 operand address - issue_read_operands input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i, + // rs2 operand - issue_read_operands output riscv::xlen_t rs2_o, + // rs2 operand is valid - issue_read_operands output logic rs2_valid_o, + // rs3 operand address - issue_read_operands input logic [ariane_pkg::REG_ADDR_SIZE-1:0] rs3_i, + // rs3 operand - issue_read_operands output rs3_len_t rs3_o, + // rs3 operand is valid - issue_read_operands output logic rs3_valid_o, // advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer + // TO_BE_COMPLETED - TO_BE_COMPLETED output ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // instruction to put on top of scoreboard e.g.: top pointer // we can always put this instruction to the top unless we signal with asserted full_o + // TO_BE_COMPLETED - TO_BE_COMPLETED input ariane_pkg::scoreboard_entry_t decoded_instr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic [31:0] orig_instr_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic decoded_instr_valid_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic decoded_instr_ack_o, // instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer + // Issue scoreboard entry - ACC_DISPATCHER output ariane_pkg::scoreboard_entry_t issue_instr_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic [31:0] orig_instr_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic issue_instr_valid_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic issue_ack_i, - // write-back port + // TO_BE_COMPLETED - TO_BE_COMPLETED input ariane_pkg::bp_resolve_t resolved_branch_i, - input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, // transaction ID at which to write the result back - input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, // write data in - input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, // exception from a functional unit (e.g.: ld/st exception) - input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, // data in is valid - input logic x_we_i, // cvxif we for writeback - - // RVFI + // Transaction ID at which to write the result back - TO_BE_COMPLETED + input logic [CVA6Cfg.NrWbPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] trans_id_i, + // Results to write back - TO_BE_COMPLETED + input logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, + // Exception from a functional unit (e.g.: ld/st exception) - TO_BE_COMPLETED + input ariane_pkg::exception_t [CVA6Cfg.NrWbPorts-1:0] ex_i, + // Indicates valid results - TO_BE_COMPLETED + input logic [CVA6Cfg.NrWbPorts-1:0] wt_valid_i, + // Cvxif we for writeback - TO_BE_COMPLETED + input logic x_we_i, + + // TO_BE_COMPLETED - RVFI output logic [ariane_pkg::TRANS_ID_BITS-1:0] rvfi_issue_pointer_o, + // TO_BE_COMPLETED - RVFI output logic [CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] rvfi_commit_pointer_o ); diff --git a/core/serdiv.sv b/core/serdiv.sv index 244ee975dc..328cfc7205 100644 --- a/core/serdiv.sv +++ b/core/serdiv.sv @@ -22,21 +22,31 @@ module serdiv parameter WIDTH = 64, parameter STABLE_HANDSHAKE = 0 // Guarantee a stable in_rdy_o during the input handshake. Keep it at 0 in CVA6 ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, - // input IF + // Serdiv translation ID - Mult input logic [TRANS_ID_BITS-1:0] id_i, + // A operand - Mult input logic [WIDTH-1:0] op_a_i, + // B operand - Mult input logic [WIDTH-1:0] op_b_i, + // Serdiv operation - Mult input logic [1:0] opcode_i, // 0: udiv, 2: urem, 1: div, 3: rem - // handshake - input logic in_vld_i, // there is a cycle delay from in_rdy_o->in_vld_i, see issue_read_operands.sv stage + // Serdiv instruction is valid - Mult + input logic in_vld_i, + // Serdiv FU is ready - Mult output logic in_rdy_o, + // Flush - CONTROLLER input logic flush_i, - // output IF + // Serdiv result is valid - Mult output logic out_vld_o, + // Serdiv is ready - Mult input logic out_rdy_i, + // Serdiv transaction ID - Mult output logic [TRANS_ID_BITS-1:0] id_o, + // Serdiv result - Mult output logic [WIDTH-1:0] res_o ); diff --git a/core/store_unit.sv b/core/store_unit.sv index fb93818c24..0c0a75de8b 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -18,38 +18,61 @@ module store_unit #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Flush - CONTROLLER input logic flush_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic stall_st_pending_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic no_st_pending_o, + // Store buffer is empty - TO_BE_COMPLETED output logic store_buffer_empty_o, - // store unit input port + // Store instruction is valid - ISSUE_STAGE input logic valid_i, + // Data input - ISSUE_STAGE input lsu_ctrl_t lsu_ctrl_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic pop_st_o, + // Instruction commit - TO_BE_COMPLETED input logic commit_i, + // TO_BE_COMPLETED - TO_BE_COMPLETED output logic commit_ready_o, + // TO_BE_COMPLETED - TO_BE_COMPLETED input logic amo_valid_commit_i, - // store unit output port + // Store result is valid - ISSUE_STAGE output logic valid_o, + // Transaction ID - ISSUE_STAGE output logic [TRANS_ID_BITS-1:0] trans_id_o, + // Store result - ISSUE_STAGE output riscv::xlen_t result_o, + // Store exception output - TO_BE_COMPLETED output exception_t ex_o, - // MMU -> Address Translation - output logic translation_req_o, // request address translation - output logic [riscv::VLEN-1:0] vaddr_o, // virtual address out + // Address translation request - TO_BE_COMPLETED + output logic translation_req_o, + // Virtual address - TO_BE_COMPLETED + output logic [riscv::VLEN-1:0] vaddr_o, + // RVFI information - RVFI output [riscv::PLEN-1:0] rvfi_mem_paddr_o, - input logic [riscv::PLEN-1:0] paddr_i, // physical address in + // Physical address - TO_BE_COMPLETED + input logic [riscv::PLEN-1:0] paddr_i, + // Exception raised before store - TO_BE_COMPLETED input exception_t ex_i, - input logic dtlb_hit_i, // will be one in the same cycle translation_req was asserted if it hits - // address checker + // Data TLB hit - lsu + input logic dtlb_hit_i, + // Address to be checked - load_unit input logic [11:0] page_offset_i, + // Address check result - load_unit output logic page_offset_matches_o, - // D$ interface + // AMO request - CACHES output amo_req_t amo_req_o, + // AMO response - CACHES input amo_resp_t amo_resp_i, + // Data cache request - CACHES input dcache_req_o_t req_port_i, + // Data cache response - CACHES output dcache_req_i_t req_port_o ); // it doesn't matter what we are writing back as stores don't return anything diff --git a/docs/04_cv32a65x_design/images/bht.png b/docs/04_cv32a65x_design/images/bht.png index 5983816a4e2e9a582a28e7b432099400f2155928..33d3a7533a28cbfe5f53d7fcd77ae514e26a6376 100644 GIT binary patch literal 76434 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