From e397f5ed14f99b47207d49c67985bdb31290f04c Mon Sep 17 00:00:00 2001 From: Michael Platzer Date: Tue, 16 Jan 2024 14:41:26 +0000 Subject: [PATCH] config_pkg/csr_regfile: Add PMP entry rst vals & RO option This commit adds three new fields to the cva6_cfg_t configuration struct, which allow to specify reset values for the PMP configuration and address CSRs as well as optionally making invidiual PMP entries read-only. The purpose is to allow hard-wiring of certain regions' privileges, which is explicitely allowed by the RISC-V Privileged Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7). --- core/csr_regfile.sv | 19 +++++++++++++++---- core/include/cv32a60x_config_pkg.sv | 3 +++ core/include/cv32a6_embedded_config_pkg.sv | 3 +++ .../cv32a6_ima_sv32_fpga_config_pkg.sv | 3 +++ core/include/cv32a6_imac_sv0_config_pkg.sv | 3 +++ core/include/cv32a6_imac_sv32_config_pkg.sv | 3 +++ core/include/cv32a6_imafc_sv32_config_pkg.sv | 3 +++ .../cv64a6_imadfcv_sv39_polara_config_pkg.sv | 3 +++ core/include/cv64a6_imafdc_sv39_config_pkg.sv | 3 +++ .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 3 +++ ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 3 +++ .../cv64a6_imafdc_sv39_wb_config_pkg.sv | 3 +++ .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 3 +++ 13 files changed, 51 insertions(+), 4 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 27e2252f9ed..48c748f0c77 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1554,8 +1554,15 @@ module csr_regfile // wait for interrupt wfi_q <= 1'b0; // pmp - pmpcfg_q <= '0; - pmpaddr_q <= '0; + for (int i = 0; i < 16; i++) begin + if (i < CVA6Cfg.NrPMPEntries) begin + pmpcfg_q[i] <= CVA6Cfg.PMPCfgRstVal[i]; + pmpaddr_q[i] <= CVA6Cfg.PMPAddrRstVal[i]; + end else begin + pmpcfg_q[i] <= '0; + pmpaddr_q[i] <= '0; + end + end end else begin priv_lvl_q <= priv_lvl_d; // floating-point registers @@ -1607,12 +1614,16 @@ module csr_regfile for (int i = 0; i < 16; i++) begin if (i < CVA6Cfg.NrPMPEntries) begin // We only support >=8-byte granularity, NA4 is disabled - if(pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin + if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin pmpcfg_q[i] <= pmpcfg_d[i]; end else begin pmpcfg_q[i] <= pmpcfg_q[i]; end - pmpaddr_q[i] <= pmpaddr_d[i]; + if (!CVA6Cfg.PMPEntryReadOnly[i]) begin + pmpaddr_q[i] <= pmpaddr_d[i]; + end else begin + pmpaddr_q[i] <= pmpaddr_q[i]; + end end else begin pmpcfg_q[i] <= '0; pmpaddr_q[i] <= '0; diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index 7f00a042607..2b38c691e18 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index f8129a317bf..26570089544 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -115,6 +115,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index b89243cd733..8866aa86118 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 11be0b699ef..8ed16309da6 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index ac0365474c8..2dfb6deeabe 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index a74a8c1cdca..6fdd44d1185 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index f77599a1e40..b84bd495729 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -115,6 +115,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 4f109453cbe..cbffd809f31 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index b6573865f62..dcfbb1b7911 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -123,6 +123,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index b7809464bbb..7f88b4fafbb 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 3de80826710..4f836b98145 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 5adfaa7d3c9..25107d6fa44 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -115,6 +115,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{riscv::pmpcfg_t'('0)}}, + PMPAddrRstVal: {16{(riscv::PLEN - 2)'('0)}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: