From d960b715fbbbdca7f8d8bf1c89e61c1d6dfc84d7 Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Mon, 16 Dec 2024 14:04:17 +0100 Subject: [PATCH] treewide: verible pass --- core/acc_dispatcher.sv | 42 ++++---- core/cache_subsystem/cva6_icache.sv | 4 +- core/cache_subsystem/wt_dcache_missunit.sv | 4 +- core/cache_subsystem/wt_dcache_wbuffer.sv | 8 +- core/cva6.sv | 4 +- core/cva6_mmu/cva6_shared_tlb.sv | 6 +- core/ex_stage.sv | 4 +- core/frontend/frontend.sv | 3 +- core/include/build_config_pkg.sv | 6 +- .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 40 +++---- core/load_store_unit.sv | 102 +++++++++--------- core/pmp/tb/tb_pkg.sv | 3 +- core/scoreboard.sv | 3 +- 13 files changed, 120 insertions(+), 109 deletions(-) diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index f1f13764e8..0f6bfdf6c9 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -27,7 +27,7 @@ module acc_dispatcher parameter type acc_resp_t = logic, parameter type accelerator_req_t = logic, parameter type accelerator_resp_t = logic, - parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_req_t = logic, parameter type acc_mmu_resp_t = logic, parameter type acc_cfg_t = logic, parameter acc_cfg_t AccCfg = '0 @@ -207,21 +207,21 @@ module acc_dispatcher *************************/ accelerator_req_t acc_req; - logic acc_req_valid; - logic acc_req_ready; + logic acc_req_valid; + logic acc_req_ready; accelerator_req_t acc_req_int; spill_register #( .T(accelerator_req_t) ) i_accelerator_req_register ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .data_i (acc_req), - .valid_i (acc_req_valid), - .ready_o (acc_req_ready), - .data_o (acc_req_int), - .valid_o (acc_req_o.acc_req.req_valid), - .ready_i (acc_resp_i.acc_resp.req_ready) + .clk_i (clk_i), + .rst_ni (rst_ni), + .data_i (acc_req), + .valid_i(acc_req_valid), + .ready_o(acc_req_ready), + .data_o (acc_req_int), + .valid_o(acc_req_o.acc_req.req_valid), + .ready_i(acc_resp_i.acc_resp.req_ready) ); assign acc_req_o.acc_req.insn = acc_req_int.insn; @@ -234,8 +234,8 @@ module acc_dispatcher assign acc_req_o.acc_req.inval_ready = inval_ready_i; // MMU interface - assign acc_req_o.acc_mmu_resp = acc_mmu_resp_i; - assign acc_req_o.acc_mmu_en = acc_mmu_en_i; + assign acc_req_o.acc_mmu_resp = acc_mmu_resp_i; + assign acc_req_o.acc_mmu_en = acc_mmu_en_i; always_comb begin : accelerator_req_dispatcher // Do not fetch from the instruction queue @@ -279,13 +279,13 @@ module acc_dispatcher logic acc_ld_disp; logic acc_st_disp; - assign acc_trans_id_o = acc_resp_i.acc_resp.trans_id; - assign acc_result_o = acc_resp_i.acc_resp.result; - assign acc_valid_o = acc_resp_i.acc_resp.resp_valid; - assign acc_exception_o = acc_resp_i.acc_resp.exception; + assign acc_trans_id_o = acc_resp_i.acc_resp.trans_id; + assign acc_result_o = acc_resp_i.acc_resp.result; + assign acc_valid_o = acc_resp_i.acc_resp.resp_valid; + assign acc_exception_o = acc_resp_i.acc_resp.exception; // Unpack the accelerator response assign acc_fflags_valid_o = acc_resp_i.acc_resp.fflags_valid; - assign acc_fflags_o = acc_resp_i.acc_resp.fflags; + assign acc_fflags_o = acc_resp_i.acc_resp.fflags; // MMU interface assign acc_mmu_req_o = acc_resp_i.acc_mmu_req; @@ -294,8 +294,8 @@ module acc_dispatcher assign acc_req_o.acc_req.resp_ready = 1'b1; // Signal dispatched load/store to issue stage - assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); - assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); + assign acc_ld_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_LOAD); + assign acc_st_disp = acc_req_valid && (acc_insn_queue_o.operation == ACCEL_OP_STORE); // Cache invalidation assign inval_valid_o = acc_resp_i.acc_resp.inval_valid; @@ -338,7 +338,7 @@ module acc_dispatcher // Set on store barrier. Clear when no store is pending. assign wait_acc_store_d = (wait_acc_store_q | commit_st_barrier_i) & acc_resp_i.acc_resp.store_pending; - assign ctrl_halt_o = wait_acc_store_q; + assign ctrl_halt_o = wait_acc_store_q; /************************** * Load/Store tracking * diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv index a173af54ce..be7becb0a0 100644 --- a/core/cache_subsystem/cva6_icache.sv +++ b/core/cache_subsystem/cva6_icache.sv @@ -424,8 +424,8 @@ module cva6_icache logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] hit_idx; for (genvar i = 0; i < CVA6Cfg.ICACHE_SET_ASSOC; i++) begin : gen_tag_cmpsel - assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i]; - assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; + assign cl_hit[i] = (cl_tag_rdata[i] == cl_tag_d) & vld_rdata[i]; + assign cl_sel[i] = cl_rdata[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; assign cl_user[i] = CVA6Cfg.FETCH_USER_EN ? cl_ruser[i][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_USER_WIDTH] : '0; end diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 5eb202e08e..59f637fe7e 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -91,8 +91,8 @@ module wt_dcache_missunit // 010: word // 011: dword // 111: DCACHE line - function automatic logic [CVA6Cfg.PLEN-1:0] paddrSizeAlign(input logic [CVA6Cfg.PLEN-1:0] paddr, - input logic [2:0] size); + function automatic logic [CVA6Cfg.PLEN-1:0] paddrSizeAlign( + input logic [CVA6Cfg.PLEN-1:0] paddr, input logic [2:0] size); logic [CVA6Cfg.PLEN-1:0] out; out = paddr; unique case (size) diff --git a/core/cache_subsystem/wt_dcache_wbuffer.sv b/core/cache_subsystem/wt_dcache_wbuffer.sv index be2029952c..841dea9cbd 100644 --- a/core/cache_subsystem/wt_dcache_wbuffer.sv +++ b/core/cache_subsystem/wt_dcache_wbuffer.sv @@ -136,8 +136,8 @@ module wt_dcache_wbuffer // openpiton requires the data to be replicated in case of smaller sizes than dwords function automatic logic [CVA6Cfg.XLEN-1:0] repData64( - input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, - input logic [1:0] size); + input logic [CVA6Cfg.XLEN-1:0] data, + input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); logic [CVA6Cfg.XLEN-1:0] out; unique case (size) 2'b00: for (int k = 0; k < 8; k++) out[k*8+:8] = data[offset*8+:8]; // byte @@ -149,8 +149,8 @@ module wt_dcache_wbuffer endfunction : repData64 function automatic logic [CVA6Cfg.XLEN-1:0] repData32( - input logic [CVA6Cfg.XLEN-1:0] data, input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, - input logic [1:0] size); + input logic [CVA6Cfg.XLEN-1:0] data, + input logic [CVA6Cfg.XLEN_ALIGN_BYTES-1:0] offset, input logic [1:0] size); logic [CVA6Cfg.XLEN-1:0] out; unique case (size) 2'b00: for (int k = 0; k < 4; k++) out[k*8+:8] = data[offset*8+:8]; // byte diff --git a/core/cva6.sv b/core/cva6.sv index 8f77964c6d..c1c9df5f0c 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -212,11 +212,11 @@ module cva6 }, // Accelerator - CVA6 - parameter type accelerator_req_t = logic, + parameter type accelerator_req_t = logic, parameter type accelerator_resp_t = logic, // Accelerator - CVA6's MMU - parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_req_t = logic, parameter type acc_mmu_resp_t = logic, // AXI types diff --git a/core/cva6_mmu/cva6_shared_tlb.sv b/core/cva6_mmu/cva6_shared_tlb.sv index 729d2194c5..2654cdb7f1 100644 --- a/core/cva6_mmu/cva6_shared_tlb.sv +++ b/core/cva6_mmu/cva6_shared_tlb.sv @@ -94,7 +94,8 @@ module cva6_shared_tlb #( shared_tag_t shared_tag_wr; shared_tag_t [SHARED_TLB_WAYS-1:0] shared_tag_rd; - logic [CVA6Cfg.SharedTlbDepth-1:0][SHARED_TLB_WAYS-1:0] shared_tag_valid_q, shared_tag_valid_d; + logic [CVA6Cfg.SharedTlbDepth-1:0][SHARED_TLB_WAYS-1:0] + shared_tag_valid_q, shared_tag_valid_d; logic [ SHARED_TLB_WAYS-1:0] shared_tag_valid; @@ -122,7 +123,8 @@ module cva6_shared_tlb #( logic [ SHARED_TLB_WAYS-1:0] pte_we; logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] pte_addr; - logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] vpn_d, vpn_q; + logic [CVA6Cfg.PtLevels+HYP_EXT-1:0][(CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-1:0] + vpn_d, vpn_q; logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] vpn_match; logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] page_match; logic [SHARED_TLB_WAYS-1:0][CVA6Cfg.PtLevels-1:0] level_match; diff --git a/core/ex_stage.sv b/core/ex_stage.sv index b1a9984bc6..8570b02f73 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -30,7 +30,7 @@ module ex_stage parameter type icache_drsp_t = logic, parameter type lsu_ctrl_t = logic, parameter type x_result_t = logic, - parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_req_t = logic, parameter type acc_mmu_resp_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -162,7 +162,7 @@ module ex_stage // accelerate port result is valid - ACC_DISPATCHER input logic acc_valid_i, // Accelerator MMU access - input acc_mmu_req_t acc_mmu_req_i, + input acc_mmu_req_t acc_mmu_req_i, output acc_mmu_resp_t acc_mmu_resp_o, // Enable virtual memory translation - CSR_REGFILE input logic enable_translation_i, diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 3117e27654..99a1b4c93d 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -127,7 +127,8 @@ module frontend logic [CVA6Cfg.INSTR_PER_FETCH-1:0] rvi_return, rvi_call, rvi_branch, rvi_jalr, rvi_jump; logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] rvi_imm; // RVC branching - logic [CVA6Cfg.INSTR_PER_FETCH-1:0] rvc_branch, rvc_jump, rvc_jr, rvc_return, rvc_jalr, rvc_call; + logic [CVA6Cfg.INSTR_PER_FETCH-1:0] + rvc_branch, rvc_jump, rvc_jr, rvc_return, rvc_jalr, rvc_call; logic [CVA6Cfg.INSTR_PER_FETCH-1:0][CVA6Cfg.VLEN-1:0] rvc_imm; // re-aligned instruction and address (coming from cache - combinationally) logic [CVA6Cfg.INSTR_PER_FETCH-1:0][ 31:0] instr; diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index bb37c194ca..94bae36d8f 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -123,7 +123,8 @@ package build_config_pkg; cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc; - cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc; + cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : + CVA6Cfg.IcacheSetAssoc; cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH; cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH; cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth; @@ -131,7 +132,8 @@ package build_config_pkg; cfg.DCacheType = CVA6Cfg.DCacheType; cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth; cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc; - cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc; + cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : + CVA6Cfg.DcacheSetAssoc; cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH; cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH; cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth; diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 3791c83a4e..1c24181b8a 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -34,7 +34,7 @@ package cva6_config_pkg; localparam CVA6ConfigAxiAddrWidth = 64; localparam CVA6ConfigAxiDataWidth = 64; localparam CVA6ConfigFetchUserEn = 0; - localparam CVA6ConfigFetchUserWidth = 1; // Just not to raise warnings + localparam CVA6ConfigFetchUserWidth = 1; // Just not to raise warnings localparam CVA6ConfigDataUserEn = 0; localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; @@ -177,23 +177,23 @@ package cva6_config_pkg; fpnew_pkg::roundmode_e frm; logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id; logic store_pending; - logic acc_cons_en; // Invalidation interface - logic inval_ready; // Invalidation interface + logic acc_cons_en; // Invalidation interface + logic inval_ready; // Invalidation interface } accelerator_req_t; typedef struct packed { - logic req_ready; - logic resp_valid; - logic [cva6_cfg.XLEN-1:0] result; - logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id; - exception_t exception; - logic store_pending; - logic store_complete; - logic load_complete; - logic [4:0] fflags; - logic fflags_valid; - logic inval_valid; // Invalidation interface - logic [63:0] inval_addr; // Invalidation interface + logic req_ready; + logic resp_valid; + logic [cva6_cfg.XLEN-1:0] result; + logic [cva6_cfg.TRANS_ID_BITS-1:0] trans_id; + exception_t exception; + logic store_pending; + logic store_complete; + logic load_complete; + logic [4:0] fflags; + logic fflags_valid; + logic inval_valid; // Invalidation interface + logic [63:0] inval_addr; // Invalidation interface } accelerator_resp_t; // Accelerator - CVA6's MMU @@ -213,13 +213,13 @@ package cva6_config_pkg; } acc_mmu_resp_t; typedef struct packed { - accelerator_req_t acc_req; // Insn/mem - logic acc_mmu_en; // MMU - acc_mmu_resp_t acc_mmu_resp; // MMU + accelerator_req_t acc_req; // Insn/mem + logic acc_mmu_en; // MMU + acc_mmu_resp_t acc_mmu_resp; // MMU } cva6_to_acc_t; typedef struct packed { - accelerator_resp_t acc_resp; // Insn/mem - acc_mmu_req_t acc_mmu_req; // MMU + accelerator_resp_t acc_resp; // Insn/mem + acc_mmu_req_t acc_mmu_req; // MMU } acc_to_cva6_t; endpackage diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv index 978a18d471..5134e13d5b 100644 --- a/core/load_store_unit.sv +++ b/core/load_store_unit.sv @@ -26,7 +26,7 @@ module load_store_unit parameter type icache_dreq_t = logic, parameter type icache_drsp_t = logic, parameter type lsu_ctrl_t = logic, - parameter type acc_mmu_req_t = logic, + parameter type acc_mmu_req_t = logic, parameter type acc_mmu_resp_t = logic ) ( // Subsystem Clock - SUBSYSTEM @@ -85,7 +85,7 @@ module load_store_unit input logic en_ld_st_g_translation_i, // Accelerator request for CVA6's MMU - input acc_mmu_req_t acc_mmu_req_i, + input acc_mmu_req_t acc_mmu_req_i, output acc_mmu_resp_t acc_mmu_resp_o, // Instruction cache input request - CACHES @@ -165,26 +165,26 @@ module load_store_unit ); // data is misaligned - logic data_misaligned; + logic data_misaligned; // -------------------------------------- // 1st register stage - (stall registers) // -------------------------------------- // those are the signals which are always correct // e.g.: they keep the value in the stall case - lsu_ctrl_t lsu_ctrl, lsu_ctrl_byp; + lsu_ctrl_t lsu_ctrl, lsu_ctrl_byp; - logic pop_st; - logic pop_ld; + logic pop_st; + logic pop_ld; // ------------------------------ // Address Generation Unit (AGU) // ------------------------------ // virtual address as calculated by the AGU in the first cycle - logic [ CVA6Cfg.VLEN-1:0] vaddr_i; - logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen; - logic overflow; - logic g_overflow; - logic [(CVA6Cfg.XLEN/8)-1:0] be_i; + logic [ CVA6Cfg.VLEN-1:0] vaddr_i; + logic [ CVA6Cfg.XLEN-1:0] vaddr_xlen; + logic overflow; + logic g_overflow; + logic [(CVA6Cfg.XLEN/8)-1:0] be_i; assign vaddr_xlen = $unsigned($signed(fu_data_i.imm) + $signed(fu_data_i.operand_a)); assign vaddr_i = vaddr_xlen[CVA6Cfg.VLEN-1:0]; @@ -196,10 +196,10 @@ module load_store_unit assign g_overflow = 1'b0; end - logic st_valid_i; - logic ld_valid_i; - logic ld_translation_req; - logic st_translation_req, cva6_st_translation_req, acc_st_translation_req; + logic st_valid_i; + logic ld_valid_i; + logic ld_translation_req; + logic st_translation_req, cva6_st_translation_req, acc_st_translation_req; logic [CVA6Cfg.VLEN-1:0] ld_vaddr; logic [ 31:0] ld_tinst; logic ld_hs_ld_st_inst; @@ -208,36 +208,36 @@ module load_store_unit logic [ 31:0] st_tinst; logic st_hs_ld_st_inst; logic st_hlvx_inst; - logic translation_req, cva6_translation_req, acc_translation_req; - logic translation_valid, cva6_translation_valid, acc_translataion_valid; + logic translation_req, cva6_translation_req, acc_translation_req; + logic translation_valid, cva6_translation_valid, acc_translataion_valid; logic [CVA6Cfg.VLEN-1:0] mmu_vaddr, cva6_mmu_vaddr, acc_mmu_vaddr; logic [CVA6Cfg.PLEN-1:0] mmu_paddr, cva6_mmu_paddr, acc_mmu_paddr, lsu_paddr; - logic [ 31:0] mmu_tinst; - logic mmu_hs_ld_st_inst; - logic mmu_hlvx_inst; - exception_t mmu_exception, cva6_mmu_exception, acc_mmu_exception; - exception_t pmp_exception; - icache_areq_t pmp_icache_areq_i; - logic pmp_translation_valid; - logic dtlb_hit, cva6_dtlb_hit, acc_dtlb_hit; - logic [ CVA6Cfg.PPNW-1:0] dtlb_ppn, cva6_dtlb_ppn, acc_dtlb_ppn; - - logic ld_valid; - logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; - logic [ CVA6Cfg.XLEN-1:0] ld_result; - logic st_valid; - logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; - logic [ CVA6Cfg.XLEN-1:0] st_result; - - logic [ 11:0] page_offset; - logic page_offset_matches; - - exception_t misaligned_exception, cva6_misaligned_exception, acc_misaligned_exception; - exception_t ld_ex; - exception_t st_ex; - - logic hs_ld_st_inst; - logic hlvx_inst; + logic [31:0] mmu_tinst; + logic mmu_hs_ld_st_inst; + logic mmu_hlvx_inst; + exception_t mmu_exception, cva6_mmu_exception, acc_mmu_exception; + exception_t pmp_exception; + icache_areq_t pmp_icache_areq_i; + logic pmp_translation_valid; + logic dtlb_hit, cva6_dtlb_hit, acc_dtlb_hit; + logic [CVA6Cfg.PPNW-1:0] dtlb_ppn, cva6_dtlb_ppn, acc_dtlb_ppn; + + logic ld_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; + logic [ CVA6Cfg.XLEN-1:0] ld_result; + logic st_valid; + logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; + logic [ CVA6Cfg.XLEN-1:0] st_result; + + logic [ 11:0] page_offset; + logic page_offset_matches; + + exception_t misaligned_exception, cva6_misaligned_exception, acc_misaligned_exception; + exception_t ld_ex; + exception_t st_ex; + + logic hs_ld_st_inst; + logic hlvx_inst; logic [1:0] sum, mxr; logic [CVA6Cfg.PPNW-1:0] satp_ppn[2:0]; logic [CVA6Cfg.ASID_WIDTH-1:0] asid[2:0], asid_to_be_flushed[1:0]; @@ -399,7 +399,11 @@ module load_store_unit if (CVA6Cfg.EnableAccelerator) begin // The MMU can be connected to CVA6 or the ACCELERATOR - enum logic {CVA6, ACC} mmu_state_d, mmu_state_q; + enum logic { + CVA6, + ACC + } + mmu_state_d, mmu_state_q; always_ff @(posedge clk_i or negedge rst_ni) begin if (~rst_ni) begin mmu_state_q <= CVA6; @@ -411,7 +415,7 @@ module load_store_unit // This logic can be optimized to reduce answer latency and contention always_comb begin // Maintain state - mmu_state_d = mmu_state_q; + mmu_state_d = mmu_state_q; // Serve CVA6 and gate the accelerator by default // MMU input misaligned_exception = cva6_misaligned_exception; @@ -487,9 +491,9 @@ module load_store_unit assign cva6_dtlb_hit = dtlb_hit; assign cva6_dtlb_ppn = dtlb_ppn; // No accelerator - assign acc_mmu_resp_o = '0; + assign acc_mmu_resp_o = '0; // Feed forward the lsu_ctrl bypass - assign lsu_ctrl = lsu_ctrl_byp; + assign lsu_ctrl = lsu_ctrl_byp; end logic store_buffer_empty; @@ -614,8 +618,8 @@ module load_store_unit // determine whether this is a load or store always_comb begin : which_op - ld_valid_i = 1'b0; - st_valid_i = 1'b0; + ld_valid_i = 1'b0; + st_valid_i = 1'b0; cva6_translation_req = 1'b0; cva6_mmu_vaddr = {CVA6Cfg.VLEN{1'b0}}; diff --git a/core/pmp/tb/tb_pkg.sv b/core/pmp/tb/tb_pkg.sv index 9bcac61f7d..56127db85d 100644 --- a/core/pmp/tb/tb_pkg.sv +++ b/core/pmp/tb/tb_pkg.sv @@ -18,7 +18,8 @@ package tb_pkg; parameter WIDTH = 32, parameter PMP_LEN = 32 ); - static function logic [PMP_LEN-1:0] base_to_conf(logic [WIDTH-1:0] base, int unsigned size_i); + static function logic [PMP_LEN-1:0] base_to_conf(logic [WIDTH-1:0] base, + int unsigned size_i); logic [PMP_LEN-1:0] pmp_reg; pmp_reg = '0; diff --git a/core/scoreboard.sv b/core/scoreboard.sv index 6a1b3d094f..97b1bc800e 100644 --- a/core/scoreboard.sv +++ b/core/scoreboard.sv @@ -111,7 +111,8 @@ module scoreboard #( logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_n, issue_pointer_q; logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer; - logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_n, commit_pointer_q; + logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] + commit_pointer_n, commit_pointer_q; logic [$clog2(CVA6Cfg.NrCommitPorts):0] num_commit; for (genvar i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin