From d26612f5b570eebc03e1843ab63e98de66fa5d3b Mon Sep 17 00:00:00 2001
From: AngelaGonzalezMarino <gonzalezmarinoangela@gmail.com>
Date: Tue, 19 Dec 2023 17:54:48 +0100
Subject: [PATCH] try fixing weird splits issues

---
 core/mmu_unify/cva6_ptw.sv |  6 +++---
 core/mmu_unify/cva6_tlb.sv | 16 ++++++++--------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/core/mmu_unify/cva6_ptw.sv b/core/mmu_unify/cva6_ptw.sv
index 1b9d2c7d46..0e8656628c 100644
--- a/core/mmu_unify/cva6_ptw.sv
+++ b/core/mmu_unify/cva6_ptw.sv
@@ -185,9 +185,9 @@ module cva6_ptw
   );
 
 
-   assign req_port_o.data_be = riscv::XLEN ==32?
-                               be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size):
-                               be_gen(req_port_o.address_index[2:0], req_port_o.data_size);
+   assign req_port_o.data_be = (riscv::XLEN == 32) ?
+          be_gen_32(req_port_o.address_index[1:0], req_port_o.data_size) :
+          be_gen(req_port_o.address_index[2:0], req_port_o.data_size);
 
   //-------------------
   // Page table walker
diff --git a/core/mmu_unify/cva6_tlb.sv b/core/mmu_unify/cva6_tlb.sv
index 61bbc4754c..3394cbc30a 100644
--- a/core/mmu_unify/cva6_tlb.sv
+++ b/core/mmu_unify/cva6_tlb.sv
@@ -179,14 +179,14 @@ module cva6_tlb
     shift = '0;
     new_index = '0;
     // The PLRU-tree indexing:
-    // lvl0        0
-    //            / \
-    //           /   \
-    // lvl1     1     2
-    //         / \   / \
-    // lvl2   3   4 5   6
-    //       / \ /\/\  /\
-    //      ... ... ... ...
+    // | lvl0        0        |
+    // |            / \       |
+    // |           /   \      |
+    // | lvl1     1     2     |
+    // |         / \   / \    |
+    // | lvl2   3   4 5   6   |
+    // |       / \ /\/\  /\   |
+    // |      ... ... ... ... |
     // Just predefine which nodes will be set/cleared
     // E.g. for a TLB with 8 entries, the for-loop is semantically
     // equivalent to the following pseudo-code: