From c5bde406363168bda7c5682c5c0d6c0d6dd98763 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me?= <124148386+cathales@users.noreply.github.com> Date: Tue, 17 Dec 2024 23:29:24 +0100 Subject: [PATCH 1/2] apply verible (#2670) There were formatting issues in core/ --- core/include/build_config_pkg.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/core/include/build_config_pkg.sv b/core/include/build_config_pkg.sv index 5d4808bb1c..95260fc0f6 100644 --- a/core/include/build_config_pkg.sv +++ b/core/include/build_config_pkg.sv @@ -123,7 +123,8 @@ package build_config_pkg; cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn; cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc; - cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc; + cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : + CVA6Cfg.IcacheSetAssoc; cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH; cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH; cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth; @@ -131,7 +132,8 @@ package build_config_pkg; cfg.DCacheType = CVA6Cfg.DCacheType; cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth; cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc; - cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc; + cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : + CVA6Cfg.DcacheSetAssoc; cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH; cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH; cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth; From a4cec295a8d653ea34f3bbfc03528f4125d49917 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me?= <124148386+cathales@users.noreply.github.com> Date: Tue, 17 Dec 2024 23:37:02 +0100 Subject: [PATCH 2/2] csr only uses one commit port (#2671) Only the first commit port is used by CSR. --- core/csr_regfile.sv | 12 ++++++------ core/cva6.sv | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 296a8d7916..e5cf84dcf3 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -35,7 +35,7 @@ module csr_regfile // halt requested - CONTROLLER output logic halt_csr_o, // Instruction to be committed - ID_STAGE - input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input scoreboard_entry_t commit_instr_i, // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM @@ -2000,11 +2000,11 @@ module csr_regfile dcsr_d.prv = priv_lvl_o; dcsr_d.v = (!CVA6Cfg.RVH) ? 1'b0 : v_q; // valid CTRL flow change - if (commit_instr_i[0].fu == CTRL_FLOW) begin + if (commit_instr_i.fu == CTRL_FLOW) begin // we saved the correct target address during execute dpc_d = { - {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i[0].bp.predict_address[CVA6Cfg.VLEN-1]}}, - commit_instr_i[0].bp.predict_address + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i.bp.predict_address[CVA6Cfg.VLEN-1]}}, + commit_instr_i.bp.predict_address }; // exception valid end else if (ex_i.valid) begin @@ -2015,8 +2015,8 @@ module csr_regfile // consecutive PC end else begin dpc_d = { - {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i[0].pc[CVA6Cfg.VLEN-1]}}, - commit_instr_i[0].pc + (commit_instr_i[0].is_compressed ? 'h2 : 'h4) + {CVA6Cfg.XLEN - CVA6Cfg.VLEN{commit_instr_i.pc[CVA6Cfg.VLEN-1]}}, + commit_instr_i.pc + (commit_instr_i.is_compressed ? 'h2 : 'h4) }; end debug_mode_d = 1'b1; diff --git a/core/cva6.sv b/core/cva6.sv index ffb6d28460..b06ccd128d 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -1088,7 +1088,7 @@ module cva6 .time_irq_i, .flush_o (flush_csr_ctrl), .halt_csr_o (halt_csr_ctrl), - .commit_instr_i (commit_instr_id_commit), + .commit_instr_i (commit_instr_id_commit[0]), .commit_ack_i (commit_ack), .boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]), .hart_id_i (hart_id_i[CVA6Cfg.XLEN-1:0]),