From bbea82732c0c0c1a822caa669fb29715fc70f83d Mon Sep 17 00:00:00 2001 From: ajalali Date: Tue, 17 Dec 2024 18:53:24 +0100 Subject: [PATCH] Interrupt cov : sample when rvfi.intr is asserted --- verif/env/uvme/cov/uvme_interrupt_covg.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/verif/env/uvme/cov/uvme_interrupt_covg.sv b/verif/env/uvme/cov/uvme_interrupt_covg.sv index e14097de6d..06519bf4e4 100644 --- a/verif/env/uvme/cov/uvme_interrupt_covg.sv +++ b/verif/env/uvme/cov/uvme_interrupt_covg.sv @@ -28,12 +28,12 @@ covergroup cg_interrupt( option.name = name; cp_interrupt: coverpoint instr.rvfi.name_csrs["mcause"].wdata { - bins NO_INTERRUPT = {0} iff (!instr.trap); + bins NO_INTERRUPT = {0} iff (!instr.rvfi.intr); ignore_bins IGN_SOFTWARE_INTERRUPT = {32'h80000003} iff (!sw_int_supported); - bins MACHINE_MODE_EXTERNAL_INTERRUPT = {32'h8000000b} iff (instr.trap); - bins MACHINE_MODE_SOFTWARE_INTERRUPT = {32'h80000003} iff (instr.trap); - bins MACHINE_MODE_TIMER_INTERRUPT = {32'h80000007} iff (instr.trap); + bins MACHINE_MODE_EXTERNAL_INTERRUPT = {32'h8000000b} iff (instr.rvfi.intr)); + bins MACHINE_MODE_SOFTWARE_INTERRUPT = {32'h80000003} iff (instr.rvfi.intr)); + bins MACHINE_MODE_TIMER_INTERRUPT = {32'h80000007} iff (instr.rvfi.intr)); }