From ba8ac715d883ce174982dcd3814e87b5a3cfc785 Mon Sep 17 00:00:00 2001
From: AngelaGonzalezMarino
 <135128652+AngelaGonzalezMarino@users.noreply.github.com>
Date: Mon, 2 Dec 2024 17:40:38 +0100
Subject: [PATCH] use dcache_assoc_width (#2640)

cva6/core/cache_subsystem/wt_dcache_missunit.sv

Line 202 in b718824
 .OutWidth ($clog2(CVA6Cfg.DCACHE_SET_ASSOC))

Better to use the width parameter which already contemplates the case of 0 to avoid issues if associativity is set to 1
cva6/core/include/build_config_pkg.sv

Line 134 in b718824
 cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc;
---
 core/cache_subsystem/wt_dcache_missunit.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv
index a521244f45..5eb202e08e 100644
--- a/core/cache_subsystem/wt_dcache_missunit.sv
+++ b/core/cache_subsystem/wt_dcache_missunit.sv
@@ -199,7 +199,7 @@ module wt_dcache_missunit
   // generate random cacheline index
   lfsr #(
       .LfsrWidth(8),
-      .OutWidth ($clog2(CVA6Cfg.DCACHE_SET_ASSOC))
+      .OutWidth (CVA6Cfg.DCACHE_SET_ASSOC_WIDTH)
   ) i_lfsr_inv (
       .clk_i (clk_i),
       .rst_ni(rst_ni),