From b6a3aa1b037f38313a972b421509bbfe73687beb Mon Sep 17 00:00:00 2001
From: Moritz Schneider <moritz.schneider@inf.ethz.ch>
Date: Tue, 9 Jul 2024 10:39:52 +0200
Subject: [PATCH] Fix non-standard usage of SystemVerilog (#2336)

Strings cannot be initially assigned to an integer without a cast.
---
 corev_apu/tb/ariane_testharness.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv
index 336def732e..1df11e7578 100644
--- a/corev_apu/tb/ariane_testharness.sv
+++ b/corev_apu/tb/ariane_testharness.sv
@@ -749,7 +749,7 @@ module ariane_testharness #(
 
 `ifdef VERILATOR
     initial begin
-        string verbosity = 0;
+        string verbosity;
         if ($value$plusargs("UVM_VERBOSITY=%s",verbosity)) begin
           uvm_set_verbosity_level(verbosity);
           `uvm_info("ariane_testharness", $sformatf("Set UVM_VERBOSITY to %s", verbosity), UVM_NONE)