diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc index a3c37d8035..f7c8f5aeea 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc @@ -221,16 +221,3 @@ | BSET | bset rd, rs1, rs2 | X(rd) = X(rs1) \| (1 << (X(rs2) & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in rs2. The index is read from the lower log2(XLEN) bits of rs2. | Single_bit_Operations | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) \| (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations |=== - -==== RVZbkb Bitmanip instructions for Cryptography - -|=== -| Name | Format | Pseudocode|Invalid_values | Exception_raised | Description| Op Name - -| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions -| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions -| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions -| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions -| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions -| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse -|=== diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst index 5af067961b..f7fa06620c 100644 --- a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst +++ b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst @@ -395,23 +395,3 @@ RVZbs Single bit Instructions +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+ | BSETI | bseti rd, rs1, shamt | X(rd) = X(rs1) | (1 << (shamt & (XLEN - 1))) | NONE | NONE | This instruction returns rs1 with a single bit set at the index specified in shamt. The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding to shamt[5]=1 are reserved. | Single_bit_Operations | +--------+----------------------+------------------------------------------------+------------------+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------+ - -RVZbkb Bitmanip instructions for Cryptography -------------------------------------- - - -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ -| Name | Format | Pseudocode | Invalid_values | Exception_raised | Description | Op Name | -+===========+========================+==========================================+==================+====================+===========================================================================================================================================================================================================================+==========================================================================================================================+ -| PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions | -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ -| PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions | -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ -| PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions | -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ -| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions | -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ -| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions | -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ -| BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse | -+-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+ diff --git a/core/alu.sv b/core/alu.sv index 6184534de8..ce62bc7b5b 100644 --- a/core/alu.sv +++ b/core/alu.sv @@ -387,12 +387,17 @@ module alu // ZKN instructions if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin unique case (fu_data_i.operation) - PACK: result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]}); - PACK_H: result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}); + PACK: + result_o = (CVA6Cfg.IS_XLEN32) ? ({fu_data_i.operand_b[15:0], fu_data_i.operand_a[15:0]}) : ({fu_data_i.operand_b[31:0], fu_data_i.operand_a[31:0]}); + PACK_H: + result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}) : ({48'b0, fu_data_i.operand_b[7:0], fu_data_i.operand_a[7:0]}); BREV8: result_o = brev8_reversed; default: ; endcase - if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) result_o = {{32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]}}; + if (fu_data_i.operation == PACK_W && CVA6Cfg.IS_XLEN64) + result_o = { + {32{fu_data_i.operand_b[15]}}, {fu_data_i.operand_b[15:0]}, {fu_data_i.operand_a[15:0]} + }; if (fu_data_i.operation == UNZIP && CVA6Cfg.IS_XLEN32) result_o = unzip_gen; if (fu_data_i.operation == ZIP && CVA6Cfg.IS_XLEN32) result_o = zip_gen; end diff --git a/core/decoder.sv b/core/decoder.sv index 2154299774..cd8900840f 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -777,8 +777,16 @@ module decoder {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROL; // rol {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::ROR; // ror // Packing - {7'b000_0100, 3'b100} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; else illegal_instr_bm = 1'b1; //pack - {7'b000_0100, 3'b111} : if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; else illegal_instr_bm = 1'b1; //packh + { + 7'b000_0100, 3'b100 + } : + if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK; + else illegal_instr_bm = 1'b1; //pack + { + 7'b000_0100, 3'b111 + } : + if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_H; + else illegal_instr_bm = 1'b1; //packh // Zero Extend Op RV32 encoding { 7'b000_0100, 3'b100 @@ -852,10 +860,14 @@ module decoder // Unsigned word Op's {7'b000_0100, 3'b000}: instruction_o.op = ariane_pkg::ADDUW; // add.uw // Bitwise Shifting - {7'b011_0000, 3'b001}: instruction_o.op = ariane_pkg::ROLW; // rolw - {7'b011_0000, 3'b101}: instruction_o.op = ariane_pkg::RORW; // rorw + {7'b011_0000, 3'b001} : instruction_o.op = ariane_pkg::ROLW; // rolw + {7'b011_0000, 3'b101} : instruction_o.op = ariane_pkg::RORW; // rorw // Pack_W - {7'b000_0100, 3'b100}: if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; else illegal_instr_bm = 1'b1; //packw + { + 7'b000_0100, 3'b100 + } : + if (CVA6Cfg.ZKN) instruction_o.op = ariane_pkg::PACK_W; + else illegal_instr_bm = 1'b1; //packw // Zero Extend Op RV64 encoding {7'b000_0100, 3'b100}: begin diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index 8c3cd7923b..f3f0a3982c 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -39,7 +39,7 @@ package cva6_config_pkg; XF8: bit'(0), RVA: bit'(0), RVB: bit'(1), - ZKN: bit'(1), + ZKN: bit'(0), RVV: bit'(0), RVC: bit'(1), RVH: bit'(0), diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index 562afba8a3..788ae83e9b 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -39,7 +39,7 @@ package cva6_config_pkg; XF8: bit'(0), RVA: bit'(0), RVB: bit'(1), - ZKN: bit'(1), + ZKN: bit'(0), RVV: bit'(0), RVC: bit'(1), RVH: bit'(0), diff --git a/core/include/cv32a6_embedded_config_pkg_deprecated.sv b/core/include/cv32a6_embedded_config_pkg_deprecated.sv index f003c36495..9168be9ed6 100644 --- a/core/include/cv32a6_embedded_config_pkg_deprecated.sv +++ b/core/include/cv32a6_embedded_config_pkg_deprecated.sv @@ -24,7 +24,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 0; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 0; @@ -91,7 +90,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index 6f162f1296..4efbdfdf52 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(1), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 278c442ef9..9d5edd3653 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index 1b976d4064..060fee513f 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index 7f2f3fbdcc..c29dd93f60 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index 6a57d10d16..26d5819862 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -24,7 +24,6 @@ package cva6_config_pkg; localparam CVA6ConfigZcmpExtEn = 0; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigHExtEn = 0; localparam CVA6ConfigVExtEn = 1; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index de18d570dd..c7a6cc5f85 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigZknExtEn = 1; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 1; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(1), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index 7347db2106..8be842fa27 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -31,7 +31,6 @@ package cva6_config_pkg; localparam CVA6ConfigZcmpExtEn = 0; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigZknExtEn = 1; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigHExtEn = 0; localparam CVA6ConfigRVZiCond = 1; @@ -99,7 +98,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(1), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index 167dd286d9..e36dffbdb2 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 0; // always disabled localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 0543244380..8acc084ee2 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -24,7 +24,6 @@ package cva6_config_pkg; localparam CVA6ConfigZcmpExtEn = 0; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigZknExtEn = 1; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigHExtEn = 0; localparam CVA6ConfigRVZiCond = 1; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(1), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdch_sv39_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_config_pkg.sv index 64d964f02e..5cce0a9ec1 100644 --- a/core/include/cv64a6_imafdch_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_config_pkg.sv @@ -25,7 +25,6 @@ package cva6_config_pkg; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigHExtEn = 1; localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigRVZiCond = 1; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv index 2e9b46077d..2705c7583b 100644 --- a/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv @@ -24,7 +24,6 @@ package cva6_config_pkg; localparam CVA6ConfigZcmpExtEn = 0; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigVExtEn = 0; localparam CVA6ConfigHExtEn = 1; localparam CVA6ConfigRVZiCond = 1; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 87cb67f9b0..c7a36e6d9b 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -24,7 +24,6 @@ package cva6_config_pkg; localparam CVA6ConfigZcmpExtEn = 0; localparam CVA6ConfigAExtEn = 1; localparam CVA6ConfigBExtEn = 0; - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigHExtEn = 0; localparam CVA6ConfigVExtEn = 1; localparam CVA6ConfigRVZiCond = 0; @@ -92,7 +91,7 @@ package cva6_config_pkg; XF8: bit'(CVA6ConfigF8En), RVA: bit'(CVA6ConfigAExtEn), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(CVA6ConfigVExtEn), RVC: bit'(CVA6ConfigCExtEn), RVH: bit'(CVA6ConfigHExtEn), diff --git a/core/include/cv64a6_mmu_config_pkg.sv b/core/include/cv64a6_mmu_config_pkg.sv index eafcbd27b1..3d902c4240 100644 --- a/core/include/cv64a6_mmu_config_pkg.sv +++ b/core/include/cv64a6_mmu_config_pkg.sv @@ -12,7 +12,6 @@ package cva6_config_pkg; localparam CVA6ConfigXlen = 64; localparam CVA6ConfigBExtEn = 1; // UVM - localparam CVA6ConfigZknExtEn = 0; localparam CVA6ConfigRvfiTrace = 1; localparam CVA6ConfigAxiIdWidth = 4; // axi_pkg.sv @@ -47,7 +46,7 @@ package cva6_config_pkg; XF8: bit'(0), RVA: bit'(0), RVB: bit'(CVA6ConfigBExtEn), - ZKN: bit'(CVA6ConfigZknExtEn), + ZKN: bit'(0), RVV: bit'(0), RVC: bit'(1), RVH: bit'(0), diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst index 83408ff800..149bbee44a 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst @@ -26,7 +26,6 @@ :header: "Configuration", "Implementation" "CV32A60AX", "Implemented extension" - "CV32A60X", "Implemented extension" "CV64A6_MMU", "Implemented extension" ============================= diff --git a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml index a7d30004ae..94dc5f7941 100644 --- a/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml +++ b/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml @@ -608,28 +608,3 @@ testlist: <<: *common_test_config iterations: 1 asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/A/src/amoxor.w-01.S - - - test: rv32im-pack-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S - - - test: rv32im-packh-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S - - - test: rv32im-brev8_32-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S - - - test: rv32im-unzip-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S - - - test: rv32im-zip-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S \ No newline at end of file diff --git a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml index 9462abe4d2..21e2b91430 100644 --- a/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml +++ b/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml @@ -562,28 +562,3 @@ testlist: iterations: 1 <<: *common_test_config asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/B/src/zext.h_32-01.S - - - test: rv32im-pack-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/pack-01.S - - - test: rv32im-packh-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/packh-01.S - - - test: rv32im-brev8_32-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/brev8_32-01.S - - - test: rv32im-unzip-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/unzip-01.S - - - test: rv32im-zip-01 - <<: *common_test_config - iterations: 1 - asm_tests: /riscv-arch-test/riscv-test-suite/rv32i_m/K/src/zip-01.S \ No newline at end of file