From 820a8c6e01a03a178b5f0e82b375f77cb8d53271 Mon Sep 17 00:00:00 2001 From: Valentin Thomazic Date: Fri, 29 Nov 2024 14:37:50 +0100 Subject: [PATCH] Fix documentation build (#2641) * Fix rtd yaml * add rtd badge to readme --- .readthedocs.yaml | 4 ++-- README.md | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.readthedocs.yaml b/.readthedocs.yaml index 957bd7983f..8d888364c3 100644 --- a/.readthedocs.yaml +++ b/.readthedocs.yaml @@ -11,10 +11,10 @@ build: nodejs: "20" ruby: "3.3" jobs: - post-install: + post_install: - npm install docs/riscv-isa/riscv-isa-manual/dependencies - gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile - pre-build: + pre_build: - make -C docs prepare # Build from the docs directory with Sphinx diff --git a/README.md b/README.md index 758a93fe14..faf2fc9a77 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/) +# CVA6 RISC-V CPU [![Build Status](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/openhwgroup/cva6/actions/workflows/ci.yml) [![CVA6 dashboard](https://riscv-ci.pages.thales-invia.fr/dashboard/badge.svg)](https://riscv-ci.pages.thales-invia.fr/dashboard/) [![Documentation Status](https://readthedocs.com/projects/openhw-group-cva6-user-manual/badge/?version=latest)](https://docs.openhwgroup.org/projects/cva6-user-manual/?badge=latest) [![GitHub release](https://img.shields.io/github/release/openhwgroup/cva6?include_prereleases=&sort=semver&color=blue)](https://github.com/openhwgroup/cva6/releases/) CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions as specified in Volume I: User-Level ISA V 2.3 as well as the draft privilege extension 1.10. It implements three privilege levels M, S, U to fully support a Unix-like operating system. Furthermore, it is compliant to the draft external debug spec 0.13.