diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 9aa7b452b4..e98921ca8a 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -181,9 +181,13 @@ smoke-bench: DASHBOARD_JOB_CATEGORY: "Performance" SPIKE_TANDEM: 1 BENCH: "dhrystone" + parallel: + matrix: + - DV_TARGET: "cv32a60x" + - DV_TARGET: "cv32a65x" script: - bash verif/regress/"$BENCH"_smoke.sh --no-print - - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_cv32a65x verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log + - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$DV_TARGET" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log smoke-hwconfig: extends: @@ -324,16 +328,16 @@ benchmarks: matrix: - BENCH: "dhrystone" ISSUE: "single" - DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] - BENCH: "dhrystone" ISSUE: "dual" - DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=1 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] - BENCH: "coremark" ISSUE: "single" - DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a60x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] - BENCH: "coremark" ISSUE: "dual" - DV_HWCONFIG_OPTS: ["cv32a65x SuperscalarEn=1 IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] + DV_HWCONFIG_OPTS: ["cv32a65x IcacheByteSize=16384 IcacheSetAssoc=8 DcacheByteSize=32768 DcacheSetAssoc=8 BHTEntries=128 NrScoreboardEntries=8 DCacheType=config_pkg::WT"] script: - bash verif/regress/"$BENCH".sh - python3 .gitlab-ci/scripts/report_benchmark.py --"$BENCH"_"$ISSUE" verif/sim/out_*/vcs-uvm_sim/"$BENCH"_main.*.log diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index 70861ac251..98a2aeb83f 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a65x: - gates: 142603 + gates: 178869 diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py index 53c9518c23..7f781c8046 100644 --- a/.gitlab-ci/scripts/report_benchmark.py +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -23,7 +23,8 @@ "dhrystone_single": 25019, "coremark_dual": 1017451, "coremark_single": 1308656, - "dhrystone_cv32a65x": 39994, + "dhrystone_cv32a65x": 32566, + "dhrystone_cv32a60x": 39994, } for arg in sys.argv[1:]: diff --git a/config/gen_from_riscv_config/cv32a60x/linker/link.ld b/config/gen_from_riscv_config/cv32a60x/linker/link.ld new file mode 100644 index 0000000000..a134ec289a --- /dev/null +++ b/config/gen_from_riscv_config/cv32a60x/linker/link.ld @@ -0,0 +1,82 @@ +/*======================================================================*/ +/* Proxy kernel linker script */ +/*======================================================================*/ +/* This is the linker script used when building the proxy kernel. */ + +/*----------------------------------------------------------------------*/ +/* Setup */ +/*----------------------------------------------------------------------*/ + +/* The OUTPUT_ARCH command specifies the machine architecture where the + argument is one of the names used in the BFD library. More + specifically one of the entires in bfd/cpu-mips.c */ + +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +/*----------------------------------------------------------------------*/ +/* Sections */ +/*----------------------------------------------------------------------*/ + +SECTIONS +{ + + /* text: test code section */ + . = 0x80000000; + _start_text = .; + .text.init : { *(.text.init) } + + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + + . = ALIGN(0x1000); + .uvmif : { *(.uvmif) } + + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .text.startup : { *(.text.startup) } + . = ALIGN(0x1000); + _end_text = .; + . = ALIGN(0x1000); + .rodata : { *(.rodata*)} + . = ALIGN(0x8); + . = ALIGN(0x1000); + .page_table : { *(.page_table) } + .user_stack : { *(.user_stack) } + .kernel_data : { *(.kernel_data) } + .kernel_stack : { *(.kernel_stack) } + + /* data segment */ + .data : { *(.data) } + + .sdata : { + __global_pointer$ = . + 0x800; + *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) + *(.sdata .sdata.* .gnu.linkonce.s.*) + } + + /* bss segment */ + .sbss : { + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + } + .bss : { *(.bss) } + + /* thread-local data segment */ + .tdata : + { + _tdata_begin = .; + *(.tdata) + _tdata_end = .; + } + .tbss : + { + *(.tbss) + _tbss_end = .; + } + + /* End of uninitalized data segement */ + _end = .; +} + diff --git a/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml b/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml new file mode 100644 index 0000000000..3d9646a554 --- /dev/null +++ b/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml @@ -0,0 +1,53 @@ +spike_param_tree: + bootrom: true + bootrom_base: 65536 + bootrom_size: 4096 + dram: true + dram_base: 2147483648 + dram_size: 1073741824 + generic_core_config: false + max_steps: 200000 + max_steps_enabled: false + isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs + priv: M + core_configs: + - + isa: rv32imczicsr_zcb_zba_zbb_zbc_zbs + extensions: cv32a60x,cvxif + boot_addr: 2147483648 + marchid_override_mask: 0xFFFFFFFF + marchid_override_value: 0x3 + misa_write_mask: 0x0 + pmpaddr0: 0 + pmpcfg0: 0 + pmpregions_max: 64 + pmpregions_writable: 8 + priv: M + status_fs_field_we: false + status_fs_field_we_enable: false + status_vs_field_we: false + status_vs_field_we_enable: false + mstatus_write_mask: 136 + mstatus_override_mask: 6144 + mie_write_mask: 0x00000880 + mie_override_mask: 0xfffff77f + mie_override_value: 0x00000000 + mip_write_mask: 0x00000000 + mip_override_mask: 0xfffff77f + mip_override_value: 0x00000000 + mtval_write_mask: 0 + tinfo_accessible: 0 + mscontext_accessible: 0 + mcontext_accessible: 0 + tdata1_accessible: 0 + tdata2_accessible: 0 + tdata3_accessible: 0 + tselect_accessible: 0 + mhartid: 0 + mvendorid_override_mask : 0xFFFFFFFF + mvendorid_override_value: 1538 + csr_counters_injection: true + interrupts_injection: true + unified_traps: true + mcycleh_implemented: false + mhpmevent31_implemented: false diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv new file mode 100644 index 0000000000..9604b24d39 --- /dev/null +++ b/core/include/cv32a60x_config_pkg.sv @@ -0,0 +1,102 @@ +// Copyright 2022 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 32; + + localparam CVA6ConfigRvfiTrace = 1; + + localparam CVA6ConfigAxiIdWidth = 4; // axi_pkg.sv + localparam CVA6ConfigAxiAddrWidth = 64; // axi_pkg.sv + localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv + localparam CVA6ConfigDataUserWidth = 32; // axi_pkg.sv + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(32), + FpgaEn: bit'(0), + FpgaAlteraEn: bit'(0), + TechnoCut: bit'(1), + SuperscalarEn: bit'(0), + NrCommitPorts: unsigned'(1), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigAxiIdWidth), + NrLoadBufEntries: unsigned'(2), + RVF: bit'(0), + RVD: bit'(0), + XF16: bit'(0), + XF16ALT: bit'(0), + XF8: bit'(0), + RVA: bit'(0), + RVB: bit'(1), + RVV: bit'(0), + RVC: bit'(1), + RVH: bit'(0), + RVZCB: bit'(1), + RVZCMP: bit'(1), + XFVec: bit'(0), + CvxifEn: bit'(1), + RVZiCond: bit'(0), + RVZicntr: bit'(0), + RVZihpm: bit'(0), + NrScoreboardEntries: unsigned'(4), + PerfCounterEn: bit'(0), + MmuPresent: bit'(0), + RVS: bit'(0), + RVU: bit'(0), + HaltAddress: 64'h800, + ExceptionAddress: 64'h808, + RASDepth: unsigned'(2), + BTBEntries: unsigned'(0), + BHTEntries: unsigned'(32), + DmBaseAddress: 64'h0, + TvalEn: bit'(0), + DirectVecOnly: bit'(1), + NrPMPEntries: unsigned'(8), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(0), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(0), + ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), + ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(0), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(2048), + IcacheSetAssoc: unsigned'(2), + IcacheLineWidth: unsigned'(128), + DCacheType: config_pkg::HPDCACHE, + DcacheByteSize: unsigned'(2028), + DcacheSetAssoc: unsigned'(2), + DcacheLineWidth: unsigned'(128), + DataUserEn: unsigned'(1), + WtDcacheWbufDepth: int'(8), + FetchUserWidth: unsigned'(32), + FetchUserEn: unsigned'(1), + InstrTlbEntries: int'(2), + DataTlbEntries: int'(2), + UseSharedTlb: bit'(1), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(0), + NrStorePipeRegs: int'(0), + DcacheIdWidth: int'(1) + }; + +endpackage diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg_deprecated.sv deleted file mode 100644 index 660e8c9f34..0000000000 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ /dev/null @@ -1,154 +0,0 @@ -// Copyright 2022 Thales DIS design services SAS -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 -// You may obtain a copy of the License at https://solderpad.org/licenses/ -// -// Original Author: Jean-Roch COULON - Thales - - -package cva6_config_pkg; - - localparam CVA6ConfigXlen = 32; - - localparam CVA6ConfigRVF = 0; - localparam CVA6ConfigF16En = 0; - localparam CVA6ConfigF16AltEn = 0; - localparam CVA6ConfigF8En = 0; - localparam CVA6ConfigFVecEn = 0; - - localparam CVA6ConfigCvxifEn = 1; - localparam CVA6ConfigCExtEn = 1; - localparam CVA6ConfigZcbExtEn = 1; - localparam CVA6ConfigZcmpExtEn = 1; - localparam CVA6ConfigAExtEn = 1; - localparam CVA6ConfigHExtEn = 0; // always disabled - localparam CVA6ConfigBExtEn = 1; - localparam CVA6ConfigVExtEn = 0; - localparam CVA6ConfigRVZiCond = 1; - - localparam CVA6ConfigAxiIdWidth = 4; - localparam CVA6ConfigAxiAddrWidth = 64; - localparam CVA6ConfigAxiDataWidth = 64; - localparam CVA6ConfigFetchUserEn = 0; - localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; - localparam CVA6ConfigDataUserEn = 0; - localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; - - localparam CVA6ConfigIcacheByteSize = 16384; - localparam CVA6ConfigIcacheSetAssoc = 4; - localparam CVA6ConfigIcacheLineWidth = 128; - localparam CVA6ConfigDcacheByteSize = 32768; - localparam CVA6ConfigDcacheSetAssoc = 8; - localparam CVA6ConfigDcacheLineWidth = 128; - - localparam CVA6ConfigDcacheIdWidth = 1; - localparam CVA6ConfigMemTidWidth = 2; - - localparam CVA6ConfigWtDcacheWbufDepth = 8; - - localparam CVA6ConfigSuperscalarEn = 0; - localparam CVA6ConfigNrCommitPorts = 1; - localparam CVA6ConfigNrScoreboardEntries = 4; - - localparam CVA6ConfigNrLoadPipeRegs = 1; - localparam CVA6ConfigNrStorePipeRegs = 0; - localparam CVA6ConfigNrLoadBufEntries = 2; - - localparam CVA6ConfigRASDepth = 0; - localparam CVA6ConfigBTBEntries = 0; - localparam CVA6ConfigBHTEntries = 0; - - localparam CVA6ConfigTvalEn = 1; - - localparam CVA6ConfigNrPMPEntries = 8; - - localparam CVA6ConfigPerfCounterEn = 0; - - localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT; - - localparam CVA6ConfigMmuPresent = 1; - - localparam CVA6ConfigRvfiTrace = 1; - - localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ - XLEN: unsigned'(CVA6ConfigXlen), - FpgaEn: bit'(0), // for Xilinx and Altera - FpgaAlteraEn: bit'(0), // for Altera (only) - TechnoCut: bit'(0), - NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), - AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), - AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), - AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), - AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), - MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), - NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), - RVF: bit'(CVA6ConfigRVF), - RVD: bit'(CVA6ConfigRVF), - XF16: bit'(CVA6ConfigF16En), - XF16ALT: bit'(CVA6ConfigF16AltEn), - XF8: bit'(CVA6ConfigF8En), - RVA: bit'(CVA6ConfigAExtEn), - RVB: bit'(CVA6ConfigBExtEn), - RVV: bit'(CVA6ConfigVExtEn), - RVC: bit'(CVA6ConfigCExtEn), - RVH: bit'(CVA6ConfigHExtEn), - RVZCB: bit'(CVA6ConfigZcbExtEn), - RVZCMP: bit'(CVA6ConfigZcmpExtEn), - XFVec: bit'(CVA6ConfigFVecEn), - CvxifEn: bit'(CVA6ConfigCvxifEn), - RVZiCond: bit'(CVA6ConfigRVZiCond), - RVZicntr: bit'(1), - RVZihpm: bit'(1), - NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), - PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), - MmuPresent: bit'(CVA6ConfigMmuPresent), - RVS: bit'(1), - RVU: bit'(1), - HaltAddress: 64'h800, - ExceptionAddress: 64'h808, - RASDepth: unsigned'(CVA6ConfigRASDepth), - BTBEntries: unsigned'(CVA6ConfigBTBEntries), - BHTEntries: unsigned'(CVA6ConfigBHTEntries), - DmBaseAddress: 64'h0, - TvalEn: bit'(CVA6ConfigTvalEn), - DirectVecOnly: bit'(0), - NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), - PMPCfgRstVal: {64{64'h0}}, - PMPAddrRstVal: {64{64'h0}}, - PMPEntryReadOnly: 64'd0, - NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, - NrNonIdempotentRules: unsigned'(2), - NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), - NonIdempotentLength: 1024'({64'b0, 64'b0}), - NrExecuteRegionRules: unsigned'(3), - ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), - ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), - NrCachedRegionRules: unsigned'(1), - CachedRegionAddrBase: 1024'({64'h8000_0000}), - CachedRegionLength: 1024'({64'h40000000}), - MaxOutstandingStores: unsigned'(7), - DebugEn: bit'(1), - AxiBurstWriteEn: bit'(0), - IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), - IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), - IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), - DCacheType: CVA6ConfigDcacheType, - DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), - DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), - DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), - DataUserEn: unsigned'(CVA6ConfigDataUserEn), - WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), - FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), - FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), - InstrTlbEntries: int'(2), - DataTlbEntries: int'(2), - UseSharedTlb: bit'(1), - SharedTlbDepth: int'(64), - NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), - NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), - DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) - }; - -endpackage diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index 61f3d7edda..d9d028fa16 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -24,7 +24,7 @@ package cva6_config_pkg; FpgaEn: bit'(0), FpgaAlteraEn: bit'(0), TechnoCut: bit'(1), - SuperscalarEn: bit'(0), + SuperscalarEn: bit'(1), NrCommitPorts: unsigned'(1), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), @@ -49,7 +49,7 @@ package cva6_config_pkg; RVZiCond: bit'(0), RVZicntr: bit'(0), RVZihpm: bit'(0), - NrScoreboardEntries: unsigned'(4), + NrScoreboardEntries: unsigned'(8), PerfCounterEn: bit'(0), MmuPresent: bit'(0), RVS: bit'(0), diff --git a/verif/regress/dhrystone_smoke.sh b/verif/regress/dhrystone_smoke.sh index f1238cb805..fdc7f82f7f 100644 --- a/verif/regress/dhrystone_smoke.sh +++ b/verif/regress/dhrystone_smoke.sh @@ -17,6 +17,10 @@ if ! [ -n "$DV_SIMULATORS" ]; then DV_SIMULATORS=vcs-uvm fi +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv32a65x +fi + # install the required tools if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then source ./verif/regress/install-verilator.sh @@ -54,7 +58,7 @@ cflags=( ) python3 cva6.py \ - --target cv32a65x \ + --target $DV_TARGET \ --iss="$DV_SIMULATORS" \ --iss_yaml=cva6.yaml \ --c_tests "$src0" \ diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py index b874ff382f..4b93c6728d 100644 --- a/verif/sim/cva6.py +++ b/verif/sim/cva6.py @@ -1049,9 +1049,10 @@ def load_config(args, cwd): if base in ("cv64a6_imafdc_sv39", "cv64a6_imafdc_sv39_hpdcache", "cv64a6_imafdc_sv39_wb"): args.mabi = "lp64d" args.isa = "rv64gc_zba_zbb_zbs_zbc" - elif base == "cv32a60x": # step1 configuration + elif base == "cv32a60x": args.mabi = "ilp32" - args.isa = "rv32imac_zba_zbb_zbs_zbc" + args.isa = "rv32imc_zba_zbb_zbs_zbc" + args.priv = "m" elif base == "cv32a65x": args.mabi = "ilp32" args.isa = "rv32imc_zba_zbb_zbs_zbc"