From a10ba44f48de3ce0e98633888607d8354f85b471 Mon Sep 17 00:00:00 2001 From: AngelaGonzalezMarino Date: Tue, 19 Dec 2023 10:31:29 +0100 Subject: [PATCH] more linting issues --- core/mmu_unify/cva6_shared_tlb.sv | 16 ++++++++-------- core/mmu_unify/cva6_tlb.sv | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/core/mmu_unify/cva6_shared_tlb.sv b/core/mmu_unify/cva6_shared_tlb.sv index 9a79fc3054..6bd34a0d0e 100644 --- a/core/mmu_unify/cva6_shared_tlb.sv +++ b/core/mmu_unify/cva6_shared_tlb.sv @@ -152,20 +152,20 @@ module cva6_shared_tlb for (i = 0; i < SHARED_TLB_WAYS; i++) begin //identify page_match for all TLB Entries - for (x=0; x < PT_LEVELS; x++) begin - assign page_match[i][x] = x==0 ? 1 :shared_tag_rd[i].is_page[PT_LEVELS-1-x]; - assign vpn_match[i][x] = vpn_q[x] == shared_tag_rd[i].vpn[x]; - assign level_match[i][x] = &vpn_match[i][PT_LEVELS-1:x] & page_match[i][x]; + for (x = 0; x < PT_LEVELS; x++) begin + assign page_match[i][x] = x == 0 ? 1 :shared_tag_rd[i].is_page[PT_LEVELS-1-x]; + assign vpn_match[i][x] = vpn_q[x] == shared_tag_rd[i].vpn[x]; + assign level_match[i][x] = &vpn_match[i][PT_LEVELS-1:x] & page_match[i][x]; end end endgenerate genvar w; generate - for (w=0; w < PT_LEVELS; w++) begin - assign vpn_d[w] = (enable_translation_i & itlb_access_i & ~itlb_hit_i & ~dtlb_access_i) ? // - itlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : // - ((en_ld_st_translation_i & dtlb_access_i & ~dtlb_hit_i)? // + for (w = 0; w < PT_LEVELS; w++) begin + assign vpn_d[w] = (enable_translation_i & itlb_access_i & ~itlb_hit_i & ~dtlb_access_i) ? // + itlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : // + ((en_ld_st_translation_i & dtlb_access_i & ~dtlb_hit_i) ? // dtlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : vpn_q[w]); end endgenerate diff --git a/core/mmu_unify/cva6_tlb.sv b/core/mmu_unify/cva6_tlb.sv index c06ff17eaa..95f0b2b29a 100644 --- a/core/mmu_unify/cva6_tlb.sv +++ b/core/mmu_unify/cva6_tlb.sv @@ -264,8 +264,8 @@ module cva6_tlb // Sanity checks //-------------- - //pragma translate_off - `ifndef VERILATOR +//pragma translate_off +`ifndef VERILATOR initial begin : p_assertions assert ((TLB_ENTRIES % 2 == 0) && (TLB_ENTRIES > 1)) @@ -300,7 +300,7 @@ module cva6_tlb $stop(); end - `endif - //pragma translate_on +`endif +//pragma translate_on endmodule