From 9e670f64c6aacc48443b6caa717660a351f926bd Mon Sep 17 00:00:00 2001 From: Matteo Perotti Date: Fri, 1 Nov 2024 17:04:12 +0100 Subject: [PATCH] acc_dispatcher: don't issue instruction from buffer if flushing (#2490) The controller flushes the pipeline and all the unissued instructions in the presence of instructions with side effects (e.g., fence). The accelerator dispatcher buffer (now used with the Ara RVV Vector processor) is flushed when this happens and avoids accepting a new instruction in that cycle, but it does not prevent the actual issuing of instructions during a flush cycle. This fix avoids the issue during a flush cycle. --- core/acc_dispatcher.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 57a8170b69..b4fc196a96 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -285,7 +285,7 @@ module acc_dispatcher }; // Wait until the instruction is no longer speculative. acc_req_valid = insn_ready_q[acc_insn_queue_o.trans_id] || - (acc_commit && insn_pending_q[acc_commit_trans_id]); + (acc_commit && insn_pending_q[acc_commit_trans_id] && !flush_unissued_instr_i); acc_insn_queue_pop = acc_req_valid && acc_req_ready; end end