From 9e47cc6947b5c47d01d2ac5c9b7e0a36b5c99627 Mon Sep 17 00:00:00 2001 From: Abdul Wadood <82087831+Abdulwadoodd@users.noreply.github.com> Date: Mon, 23 Oct 2023 19:55:05 +0500 Subject: [PATCH] removed c.zext.w from rv32 spec (#1563) Signed-off-by: Abdul Wadood --- docs/01_cva6_user/RISCV_Instructions.rst | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst index 74f13e7a2f..2a59e62066 100644 --- a/docs/01_cva6_user/RISCV_Instructions.rst +++ b/docs/01_cva6_user/RISCV_Instructions.rst @@ -1307,18 +1307,6 @@ All the Zcb instructions require at least standard C extension support as pre-re **Exception raised**: NONE -- **C.ZEXT.W**: Compressed Zero Extend Word - - **Format**: c.zext.w rd' - - **Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant word of the operand by inserting zeros into all of the bits more significant than 31. It also requires Bit-Manipulation (Zbb) extension support. - - **Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][31:0]) - - **Invalid values**: NONE - - **Exception raised**: NONE - - **C.NOT**: Compressed Bitwise NOT **Format**: c.not rd'