From 9df64701bdd5bd2677ba8f97a34273db61c68a10 Mon Sep 17 00:00:00 2001 From: Cesar Fuguet Date: Tue, 18 Jun 2024 11:54:35 +0200 Subject: [PATCH] Update submodule core/cache_subsystem/hpdcache (#2265) --- .gitlab-ci/scripts/report_benchmark.py | 2 +- .../cva6_hpdcache_if_adapter.sv | 6 ++-- .../cva6_hpdcache_subsystem.sv | 20 +++++------ core/cache_subsystem/cva6_hpdcache_wrapper.sv | 36 +++++++++---------- core/cache_subsystem/hpdcache | 2 +- 5 files changed, 32 insertions(+), 34 deletions(-) diff --git a/.gitlab-ci/scripts/report_benchmark.py b/.gitlab-ci/scripts/report_benchmark.py index f3eddf5ba5..c471190956 100644 --- a/.gitlab-ci/scripts/report_benchmark.py +++ b/.gitlab-ci/scripts/report_benchmark.py @@ -18,7 +18,7 @@ # Will fail if the number of cycles is different from this one valid_cycles = { 'dhrystone': 217900, - 'coremark': 686479, + 'coremark': 686072, } for arg in sys.argv[1:]: diff --git a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv index 52f988b929..1b40134377 100644 --- a/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_if_adapter.sv @@ -14,7 +14,7 @@ module cva6_hpdcache_if_adapter // {{{ #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg = '0, + parameter hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = '0, parameter type hpdcache_tag_t = logic, parameter type hpdcache_req_offset_t = logic, parameter type hpdcache_req_sid_t = logic, @@ -120,8 +120,8 @@ module cva6_hpdcache_if_adapter // {{{ always_comb begin : amo_op_comb amo_addr = cva6_amo_req_i.operand_a; - amo_addr_offset = amo_addr[0+:hpdcacheCfg.reqOffsetWidth]; - amo_tag = amo_addr[hpdcacheCfg.reqOffsetWidth+:hpdcacheCfg.tagWidth]; + amo_addr_offset = amo_addr[0+:HPDcacheCfg.reqOffsetWidth]; + amo_tag = amo_addr[HPDcacheCfg.reqOffsetWidth+:HPDcacheCfg.tagWidth]; unique case (cva6_amo_req_i.amo_op) ariane_pkg::AMO_LR: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_LR; ariane_pkg::AMO_SC: amo_op = hpdcache_pkg::HPDCACHE_REQ_AMO_SC; diff --git a/core/cache_subsystem/cva6_hpdcache_subsystem.sv b/core/cache_subsystem/cva6_hpdcache_subsystem.sv index 45f2a337b1..80a00a5799 100644 --- a/core/cache_subsystem/cva6_hpdcache_subsystem.sv +++ b/core/cache_subsystem/cva6_hpdcache_subsystem.sv @@ -189,7 +189,7 @@ module cva6_hpdcache_subsystem // NumPorts + 1: Hardware Memory Prefetcher (hwpf) localparam int HPDCACHE_NREQUESTERS = NumPorts + 2; - localparam hpdcache_pkg::hpdcache_user_cfg_t hpdcacheUserCfg = '{ + localparam hpdcache_pkg::hpdcache_user_cfg_t HPDcacheUserCfg = '{ nRequesters: HPDCACHE_NREQUESTERS, paWidth: CVA6Cfg.PLEN, wordWidth: CVA6Cfg.XLEN, @@ -223,12 +223,12 @@ module cva6_hpdcache_subsystem memDataWidth: CVA6Cfg.AxiDataWidth }; - localparam hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg = hpdcache_pkg::hpdcacheBuildConfig( - hpdcacheUserCfg + localparam hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg = hpdcache_pkg::hpdcacheBuildConfig( + HPDcacheUserCfg ); `HPDCACHE_TYPEDEF_MEM_ATTR_T(hpdcache_mem_addr_t, hpdcache_mem_id_t, hpdcache_mem_data_t, - hpdcache_mem_be_t, hpdcacheCfg); + hpdcache_mem_be_t, HPDcacheCfg); `HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t); `HPDCACHE_TYPEDEF_MEM_RESP_R_T(hpdcache_mem_resp_r_t, hpdcache_mem_id_t, hpdcache_mem_data_t); `HPDCACHE_TYPEDEF_MEM_REQ_W_T(hpdcache_mem_req_w_t, hpdcache_mem_data_t, hpdcache_mem_be_t); @@ -236,14 +236,14 @@ module cva6_hpdcache_subsystem `HPDCACHE_TYPEDEF_REQ_ATTR_T(hpdcache_req_offset_t, hpdcache_data_word_t, hpdcache_data_be_t, hpdcache_req_data_t, hpdcache_req_be_t, hpdcache_req_sid_t, - hpdcache_req_tid_t, hpdcache_tag_t, hpdcacheCfg); + hpdcache_req_tid_t, hpdcache_tag_t, HPDcacheCfg); `HPDCACHE_TYPEDEF_REQ_T(hpdcache_req_t, hpdcache_req_offset_t, hpdcache_req_data_t, hpdcache_req_be_t, hpdcache_req_sid_t, hpdcache_req_tid_t, hpdcache_tag_t); `HPDCACHE_TYPEDEF_RSP_T(hpdcache_rsp_t, hpdcache_req_data_t, hpdcache_req_sid_t, hpdcache_req_tid_t); - typedef logic [hpdcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; + typedef logic [HPDcacheCfg.u.wbufTimecntWidth-1:0] hpdcache_wbuf_timecnt_t; logic dcache_miss_ready; logic dcache_miss_valid; @@ -287,7 +287,7 @@ module cva6_hpdcache_subsystem cva6_hpdcache_wrapper #( .CVA6Cfg(CVA6Cfg), - .hpdcacheCfg(hpdcacheCfg), + .HPDcacheCfg(HPDcacheCfg), .dcache_req_i_t(dcache_req_i_t), .dcache_req_o_t(dcache_req_o_t), .NumPorts(NumPorts), @@ -467,13 +467,13 @@ module cva6_hpdcache_subsystem // {{{ // pragma translate_off initial begin : initial_assertions - assert (hpdcacheCfg.u.reqSrcIdWidth >= $clog2(HPDCACHE_NREQUESTERS)) + assert (HPDcacheCfg.u.reqSrcIdWidth >= $clog2(HPDCACHE_NREQUESTERS)) else $fatal(1, "HPDCACHE_REQ_SRC_ID_WIDTH is not wide enough"); assert (CVA6Cfg.MEM_TID_WIDTH <= CVA6Cfg.AxiIdWidth) else $fatal(1, "MEM_TID_WIDTH shall be less or equal to the AxiIdWidth"); - assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(hpdcacheCfg.u.mshrSets * hpdcacheCfg.u.mshrWays) + 1)) + assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.mshrSets * HPDcacheCfg.u.mshrWays) + 1)) else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ and I$ miss requests "); - assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(hpdcacheCfg.u.wbufDirEntries) + 1)) + assert (CVA6Cfg.MEM_TID_WIDTH >= ($clog2(HPDcacheCfg.u.wbufDirEntries) + 1)) else $fatal(1, "MEM_TID_WIDTH shall allow to uniquely identify all D$ write requests "); end diff --git a/core/cache_subsystem/cva6_hpdcache_wrapper.sv b/core/cache_subsystem/cva6_hpdcache_wrapper.sv index 24d2a45d7b..1e532a2b5e 100644 --- a/core/cache_subsystem/cva6_hpdcache_wrapper.sv +++ b/core/cache_subsystem/cva6_hpdcache_wrapper.sv @@ -8,9 +8,7 @@ // // Authors: Cesar Fuguet // Date: February, 2023 -// Description: CVA6 cache subsystem integrating standard CVA6's -// instruction cache and the Core-V High-Performance L1 -// data cache (CV-HPDcache). +// Description: Wrapper for the Core-V High-Performance L1 data cache (CV-HPDcache) `include "hpdcache_typedef.svh" @@ -19,7 +17,7 @@ module cva6_hpdcache_wrapper // {{{ #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter hpdcache_pkg::hpdcache_cfg_t hpdcacheCfg, // TODO + parameter hpdcache_pkg::hpdcache_cfg_t HPDcacheCfg, parameter type dcache_req_i_t = logic, parameter type dcache_req_o_t = logic, parameter int NumPorts = 4, @@ -153,14 +151,14 @@ module cva6_hpdcache_wrapper typedef logic [63:0] hwpf_stride_param_t; - logic dcache_req_valid[HPDCACHE_NREQUESTERS-1:0]; - logic dcache_req_ready[HPDCACHE_NREQUESTERS-1:0]; - hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS-1:0]; - logic dcache_req_abort[HPDCACHE_NREQUESTERS-1:0]; - hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS-1:0]; - hpdcache_pkg::hpdcache_pma_t dcache_req_pma [HPDCACHE_NREQUESTERS-1:0]; - logic dcache_rsp_valid[HPDCACHE_NREQUESTERS-1:0]; - hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS-1:0]; + logic dcache_req_valid[HPDCACHE_NREQUESTERS]; + logic dcache_req_ready[HPDCACHE_NREQUESTERS]; + hpdcache_req_t dcache_req [HPDCACHE_NREQUESTERS]; + logic dcache_req_abort[HPDCACHE_NREQUESTERS]; + hpdcache_tag_t dcache_req_tag [HPDCACHE_NREQUESTERS]; + hpdcache_pkg::hpdcache_pma_t dcache_req_pma [HPDCACHE_NREQUESTERS]; + logic dcache_rsp_valid[HPDCACHE_NREQUESTERS]; + hpdcache_rsp_t dcache_rsp [HPDCACHE_NREQUESTERS]; logic dcache_read_miss, dcache_write_miss; logic [ 2:0] snoop_valid; @@ -175,14 +173,14 @@ module cva6_hpdcache_wrapper hwpf_stride_pkg::hwpf_stride_throttle_t [NrHwPrefetchers-1:0] hwpf_throttle_out; generate - dcache_req_i_t dcache_req_ports[HPDCACHE_NREQUESTERS-1:0]; + dcache_req_i_t dcache_req_ports[NumPorts - 1]; for (genvar r = 0; r < (NumPorts - 1); r++) begin : gen_cva6_hpdcache_load_if_adapter assign dcache_req_ports[r] = dcache_req_ports_i[r]; cva6_hpdcache_if_adapter #( .CVA6Cfg (CVA6Cfg), - .hpdcacheCfg (hpdcacheCfg), + .HPDcacheCfg (HPDcacheCfg), .hpdcache_tag_t (hpdcache_tag_t), .hpdcache_req_offset_t(hpdcache_req_offset_t), .hpdcache_req_sid_t (hpdcache_req_sid_t), @@ -216,7 +214,7 @@ module cva6_hpdcache_wrapper cva6_hpdcache_if_adapter #( .CVA6Cfg (CVA6Cfg), - .hpdcacheCfg (hpdcacheCfg), + .HPDcacheCfg (HPDcacheCfg), .hpdcache_tag_t (hpdcache_tag_t), .hpdcache_req_offset_t(hpdcache_req_offset_t), .hpdcache_req_sid_t (hpdcache_req_sid_t), @@ -315,13 +313,13 @@ module cva6_hpdcache_wrapper generate for (genvar h = 0; h < NrHwPrefetchers; h++) begin : gen_hwpf_throttle - assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]), - hwpf_throttle_o[h] = hwpf_stride_pkg::hwpf_stride_param_t'(hwpf_throttle_out[h]); + assign hwpf_throttle_in[h] = hwpf_stride_pkg::hwpf_stride_throttle_t'(hwpf_throttle_i[h]); + assign hwpf_throttle_o[h] = hwpf_stride_pkg::hwpf_stride_param_t'(hwpf_throttle_out[h]); end endgenerate hwpf_stride_wrapper #( - .hpdcacheCfg (hpdcacheCfg), + .HPDcacheCfg (HPDcacheCfg), .NUM_HW_PREFETCH (NrHwPrefetchers), .NUM_SNOOP_PORTS (3), .hpdcache_tag_t (hpdcache_tag_t), @@ -366,7 +364,7 @@ module cva6_hpdcache_wrapper ); hpdcache #( - .hpdcacheCfg (hpdcacheCfg), + .HPDcacheCfg (HPDcacheCfg), .wbuf_timecnt_t (hpdcache_wbuf_timecnt_t), .hpdcache_tag_t (hpdcache_tag_t), .hpdcache_data_word_t (hpdcache_data_word_t), diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache index 32407cb8f6..25ffa3438c 160000 --- a/core/cache_subsystem/hpdcache +++ b/core/cache_subsystem/hpdcache @@ -1 +1 @@ -Subproject commit 32407cb8f69b71824083abd72b2d4e8bcd0c2f01 +Subproject commit 25ffa3438c8150fef791dd165234694a51e3c529