From 9d0c700f42dbbce4c6ae10fde34d7ba21d6f76b0 Mon Sep 17 00:00:00 2001 From: JeanRochCoulon Date: Tue, 6 Feb 2024 12:06:13 +0100 Subject: [PATCH] port_builder generates the table of ports (#1805) --- core/cva6.sv | 31 +- core/frontend/bht.sv | 20 +- core/frontend/btb.sv | 20 +- core/frontend/frontend.sv | 59 +- core/frontend/instr_queue.sv | 23 +- core/frontend/instr_scan.sv | 38 +- core/frontend/ras.sv | 21 +- core/instr_realign.sv | 12 +- .../.gitignore | 0 .../Makefile | 0 .../images/CVA6_subsystems.png | Bin .../images/LZC.png | Bin .../images/RR.png | Bin .../images/ariane_overview.drawio.png | Bin .../images/ariane_overview.png | Bin .../images/bht.png | Bin .../images/cva6_tlb_entry.png | Bin .../images/cva6_tlb_hit.png | Bin .../images/frontend_modules.png | Bin .../images/in_out_tlb.png | Bin .../images/mmu_control_flow.png | Bin .../images/mmu_in_out.png | Bin .../images/mmu_major_blocks.png | Bin .../images/openhw-landscape.svg | 0 .../images/plru_tree_indexing.png | Bin .../images/ptw_dptw.png | Bin .../images/ptw_dptw_s.png | Bin .../images/ptw_idle.png | Bin .../images/ptw_in_out.png | Bin .../images/ptw_iptw.png | Bin .../images/ptw_mis_sup.png | Bin .../images/ptw_nlvl.png | Bin .../images/ptw_pte_1.png | Bin .../images/ptw_pte_flowchart.png | Bin .../images/ptw_state_diagram.png | Bin .../images/replacement_entry.png | Bin .../images/sfence_vaddr_asid.png | Bin .../images/sfence_vaddr_x0.png | Bin .../images/sfence_x0_asid.png | Bin .../images/sfence_x0_x0.png | Bin .../images/shared_tlb.png | Bin .../images/shared_tlb_in_out.png | Bin .../images/shared_tlb_set.png | Bin .../images/subsystems.png | Bin .../images/update_tree.png | Bin .../make.bat | 0 .../requirements.txt | 0 .../source/AXI.rst | 0 .../source/CSRs.rst | 0 .../source/CVXIF.rst | 0 .../source/architecture.rst | 0 .../source/conf.py | 0 .../source/csr.rst | 0 .../source/csr_list.rst | 0 .../source/cv32a6_execute.rst | 0 .../source/cv32a6_frontend.rst | 552 +----------------- .../source/cv32a6_glossary.rst | 0 .../source/functionality.rst | 0 .../source/index.rst | 2 +- .../source/instructions.rst | 0 .../source/intro.rst | 2 +- .../source/overview.rst | 0 docs/04_cv32a65x_design/source/port_bht.rst | 61 ++ docs/04_cv32a65x_design/source/port_btb.rst | 61 ++ docs/04_cv32a65x_design/source/port_cva6.rst | 97 +++ .../source/port_frontend.rst | 139 +++++ .../source/port_instr_queue.rst | 121 ++++ .../source/port_instr_realign.rst | 79 +++ .../source/port_instr_scan.rst | 103 ++++ docs/04_cv32a65x_design/source/port_ras.rst | 61 ++ .../source/subsystem.rst | 86 +-- .../source/traps.rst | 0 docs/index.rst | 8 +- docs/scripts/table_port_builder.py | 96 +++ 74 files changed, 982 insertions(+), 710 deletions(-) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/.gitignore (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/Makefile (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/CVA6_subsystems.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/LZC.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/RR.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ariane_overview.drawio.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ariane_overview.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/bht.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/cva6_tlb_entry.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/cva6_tlb_hit.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/frontend_modules.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/in_out_tlb.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/mmu_control_flow.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/mmu_in_out.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/mmu_major_blocks.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/openhw-landscape.svg (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/plru_tree_indexing.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_dptw.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_dptw_s.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_idle.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_in_out.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_iptw.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_mis_sup.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_nlvl.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_pte_1.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_pte_flowchart.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/ptw_state_diagram.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/replacement_entry.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/sfence_vaddr_asid.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/sfence_vaddr_x0.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/sfence_x0_asid.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/sfence_x0_x0.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/shared_tlb.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/shared_tlb_in_out.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/shared_tlb_set.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/subsystems.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/images/update_tree.png (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/make.bat (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/requirements.txt (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/AXI.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/CSRs.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/CVXIF.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/architecture.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/conf.py (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/csr.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/csr_list.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/cv32a6_execute.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/cv32a6_frontend.rst (52%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/cv32a6_glossary.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/functionality.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/index.rst (95%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/instructions.rst (100%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/intro.rst (98%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/overview.rst (100%) create mode 100644 docs/04_cv32a65x_design/source/port_bht.rst create mode 100644 docs/04_cv32a65x_design/source/port_btb.rst create mode 100644 docs/04_cv32a65x_design/source/port_cva6.rst create mode 100644 docs/04_cv32a65x_design/source/port_frontend.rst create mode 100644 docs/04_cv32a65x_design/source/port_instr_queue.rst create mode 100644 docs/04_cv32a65x_design/source/port_instr_realign.rst create mode 100644 docs/04_cv32a65x_design/source/port_instr_scan.rst create mode 100644 docs/04_cv32a65x_design/source/port_ras.rst rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/subsystem.rst (65%) rename docs/{04_cv32a6_design => 04_cv32a65x_design}/source/traps.rst (100%) create mode 100755 docs/scripts/table_port_builder.py diff --git a/core/cva6.sv b/core/cva6.sv index 681c2fa1e4..385a487908 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -115,24 +115,31 @@ module cva6 parameter type cvxif_req_t = cvxif_pkg::cvxif_req_t, parameter type cvxif_resp_t = cvxif_pkg::cvxif_resp_t ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, - // Core ID, Cluster ID and boot address are considered more or less static - input logic [riscv::VLEN-1:0] boot_addr_i, // reset boot address - input logic [riscv::XLEN-1:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR) - // Interrupt inputs - input logic [1:0] irq_i, // level sensitive IR lines, mip & sip (async) - input logic ipi_i, // inter-processor interrupts (async) - // Timer facilities - input logic time_irq_i, // timer interrupt in (async) - input logic debug_req_i, // debug request (async) - // RISC-V formal interface port (`rvfi`): - // Can be left open when formal tracing is not needed. + // Reset boot address - SUBSYSTEM + input logic [riscv::VLEN-1:0] boot_addr_i, + // Hard ID reflected as CSR - SUBSYSTEM + input logic [riscv::XLEN-1:0] hart_id_i, + // Level sensitive (async) interrupts - SUBSYSTEM + input logic [1:0] irq_i, + // Inter-processor (async) interrupt - SUBSYSTEM + input logic ipi_i, + // Timer (async) interrupt - SUBSYSTEM + input logic time_irq_i, + // Debug (async) request - SUBSYSTEM + input logic debug_req_i, + // Probes to build RVFI, can be left open when not used - SUBSYSTEM output rvfi_probes_t rvfi_probes_o, + // CVXIF request - SUBSYSTEM output cvxif_req_t cvxif_req_o, + // CVXIF response - SUBSYSTEM input cvxif_resp_t cvxif_resp_i, - // memory side + // noc request, can be AXI or OpenPiton - SUBSYSTEM output noc_req_t noc_req_o, + // noc response, can be AXI or OpenPiton - SUBSYSTEM input noc_resp_t noc_resp_i ); diff --git a/core/frontend/bht.sv b/core/frontend/bht.sv index bcfb78c74e..e25724b0c4 100644 --- a/core/frontend/bht.sv +++ b/core/frontend/bht.sv @@ -22,13 +22,19 @@ module bht #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned NR_ENTRIES = 1024 ) ( - input logic clk_i, - input logic rst_ni, - input logic flush_i, - input logic debug_mode_i, - input logic [ riscv::VLEN-1:0] vpc_i, - input ariane_pkg::bht_update_t bht_update_i, - // we potentially need INSTR_PER_FETCH predictions/cycle + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // Debug mode state - CSR + input logic debug_mode_i, + // Virtual PC - CACHE + input logic [riscv::VLEN-1:0] vpc_i, + // Update bht with resolved address - EXECUTE + input ariane_pkg::bht_update_t bht_update_i, + // Prediction from bht - FRONTEND output ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] bht_prediction_o ); // the last bit is always zero, we don't need it for indexing diff --git a/core/frontend/btb.sv b/core/frontend/btb.sv index 9500f37339..52e2497ccd 100644 --- a/core/frontend/btb.sv +++ b/core/frontend/btb.sv @@ -29,14 +29,20 @@ module btb #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int NR_ENTRIES = 8 ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic flush_i, // flush the btb + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // Debug mode state - CSR input logic debug_mode_i, - - input logic [riscv::VLEN-1:0] vpc_i, // virtual PC from IF stage - input ariane_pkg::btb_update_t btb_update_i, // update btb with this information - output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o // prediction from btb + // Virtual PC - CACHE + input logic [riscv::VLEN-1:0] vpc_i, + // Update BTB with resolved address - EXECUTE + input ariane_pkg::btb_update_t btb_update_i, + // BTB Prediction - FRONTEND + output ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] btb_prediction_o ); // the last bit is always zero, we don't need it for indexing localparam OFFSET = CVA6Cfg.RVC == 1'b1 ? 1 : 2; diff --git a/core/frontend/frontend.sv b/core/frontend/frontend.sv index 8f2f50a048..1b8035f304 100644 --- a/core/frontend/frontend.sv +++ b/core/frontend/frontend.sv @@ -20,33 +20,46 @@ module frontend #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( - input logic clk_i, // Clock - input logic rst_ni, // Asynchronous reset active low - input logic flush_i, // flush request for PCGEN - input logic flush_bp_i, // flush branch prediction - input logic halt_i, // halt commit stage + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // flush branch prediction - zero + input logic flush_bp_i, + // halt commit stage - CONTROLLER + input logic halt_i, + // Debug mode state - CSR input logic debug_mode_i, - // global input + // Next PC when reset - SUBSYSTEM input logic [riscv::VLEN-1:0] boot_addr_i, - // Set a new PC - // mispredict - input bp_resolve_t resolved_branch_i, // from controller signaling a branch_predict -> update BTB - // from commit, when flushing the whole pipeline - input logic set_pc_commit_i, // Take the PC from commit stage - input logic [riscv::VLEN-1:0] pc_commit_i, // PC of instruction in commit stage - // CSR input - input logic [riscv::VLEN-1:0] epc_i, // exception PC which we need to return to - input logic eret_i, // return from exception - input logic [riscv::VLEN-1:0] trap_vector_base_i, // base of trap vector - input logic ex_valid_i, // exception is valid - from commit - input logic set_debug_pc_i, // jump to debug address - // Instruction Fetch + // mispredict event and next PC - EXECUTE + input bp_resolve_t resolved_branch_i, + // Set the PC coming from COMMIT as next PC - CONTROLLER + input logic set_pc_commit_i, + // Next PC when flushing pipeline - COMMIT + input logic [riscv::VLEN-1:0] pc_commit_i, + // Next PC when returning from exception - CSR + input logic [riscv::VLEN-1:0] epc_i, + // Return from exception event - CSR + input logic eret_i, + // Next PC when jumping into exception - CSR + input logic [riscv::VLEN-1:0] trap_vector_base_i, + // Exception event - COMMIT + input logic ex_valid_i, + // Debug event - CSR + input logic set_debug_pc_i, + // Handshake between CACHE and FRONTEND (fetch) - CACHES output icache_dreq_t icache_dreq_o, + // Handshake between CACHE and FRONTEND (fetch) - CACHES input icache_drsp_t icache_dreq_i, - // instruction output port -> to processor back-end - output fetch_entry_t fetch_entry_o, // fetch entry containing all relevant data for the ID stage - output logic fetch_entry_valid_o, // instruction in IF is valid - input logic fetch_entry_ready_i // ID acknowledged this instruction + // Handshake's data between fetch and decode - DECODE + output fetch_entry_t fetch_entry_o, + // Handshake's valid between fetch and decode - DECODE + output logic fetch_entry_valid_o, + // Handshake's ready between fetch and decode - DECODE + input logic fetch_entry_ready_i ); // Instruction Cache Registers, from I$ logic [ FETCH_WIDTH-1:0] icache_data_q; diff --git a/core/frontend/instr_queue.sv b/core/frontend/instr_queue.sv index c4910cfca6..33f1873dc5 100644 --- a/core/frontend/instr_queue.sv +++ b/core/frontend/instr_queue.sv @@ -48,26 +48,39 @@ module instr_queue #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // Fetch flush request - CONTROLLER input logic flush_i, + // Instruction - instr_realign input logic [ariane_pkg::INSTR_PER_FETCH-1:0][31:0] instr_i, + // Instruction address - instr_realign input logic [ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] addr_i, + // Instruction is valid - instr_realign input logic [ariane_pkg::INSTR_PER_FETCH-1:0] valid_i, + // Handshake’s ready with CACHE - CACHE output logic ready_o, + // Indicates instructions consummed, or popped by DECODE - FRONTEND output logic [ariane_pkg::INSTR_PER_FETCH-1:0] consumed_o, - // we've encountered an exception, at this point the only possible exceptions are page-table faults + // Exception (which is page-table fault) - CACHE input ariane_pkg::frontend_exception_t exception_i, + // Exception address - CACHE input logic [riscv::VLEN-1:0] exception_addr_i, - // branch predict + // Branch predict - FRONTEND input logic [riscv::VLEN-1:0] predict_address_i, + // Instruction predict address - FRONTEND input ariane_pkg::cf_t [ariane_pkg::INSTR_PER_FETCH-1:0] cf_type_i, - // replay instruction because one of the FIFO was already full + // Replay instruction because one of the FIFO was full - FRONTEND output logic replay_o, - output logic [riscv::VLEN-1:0] replay_addr_o, // address at which to replay this instruction - // to processor backend + // Address at which to replay the fetch - FRONTEND + output logic [riscv::VLEN-1:0] replay_addr_o, + // Handshake’s data with DECODE - DECODE output ariane_pkg::fetch_entry_t fetch_entry_o, + // Handshake’s valid with DECODE - DECODE output logic fetch_entry_valid_o, + // Handshake’s ready with DECODE - DECODE input logic fetch_entry_ready_i ); diff --git a/core/frontend/instr_scan.sv b/core/frontend/instr_scan.sv index 592d5d34a4..2c585deb3b 100644 --- a/core/frontend/instr_scan.sv +++ b/core/frontend/instr_scan.sv @@ -18,19 +18,33 @@ module instr_scan #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( - input logic [ 31:0] instr_i, // expect aligned instruction, compressed or not - output logic rvi_return_o, - output logic rvi_call_o, - output logic rvi_branch_o, - output logic rvi_jalr_o, - output logic rvi_jump_o, + // Instruction to be predecoded - instr_realign + input logic [31:0] instr_i, + // Return instruction - FRONTEND + output logic rvi_return_o, + // JAL instruction - FRONTEND + output logic rvi_call_o, + // Branch instruction - FRONTEND + output logic rvi_branch_o, + // JALR instruction - FRONTEND + output logic rvi_jalr_o, + // Unconditional jump instruction - FRONTEND + output logic rvi_jump_o, + // Instruction immediat - FRONTEND output logic [riscv::VLEN-1:0] rvi_imm_o, - output logic rvc_branch_o, - output logic rvc_jump_o, - output logic rvc_jr_o, - output logic rvc_return_o, - output logic rvc_jalr_o, - output logic rvc_call_o, + // Branch compressed instruction - FRONTEND + output logic rvc_branch_o, + // Unconditional jump compressed instruction - FRONTEND + output logic rvc_jump_o, + // JR compressed instruction - FRONTEND + output logic rvc_jr_o, + // Return compressed instruction - FRONTEND + output logic rvc_return_o, + // JALR compressed instruction - FRONTEND + output logic rvc_jalr_o, + // JAL compressed instruction - FRONTEND + output logic rvc_call_o, + // Instruction compressed immediat - FRONTEND output logic [riscv::VLEN-1:0] rvc_imm_o ); logic is_rvc; diff --git a/core/frontend/ras.sv b/core/frontend/ras.sv index f092b50020..cac8f3edc8 100644 --- a/core/frontend/ras.sv +++ b/core/frontend/ras.sv @@ -18,13 +18,20 @@ module ras #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter int unsigned DEPTH = 2 ) ( - input logic clk_i, - input logic rst_ni, - input logic flush_i, - input logic push_i, - input logic pop_i, - input logic [riscv::VLEN-1:0] data_i, - output ariane_pkg::ras_t data_o + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Fetch flush request - CONTROLLER + input logic flush_i, + // Push address in RAS - FRONTEND + input logic push_i, + // Pop address from RAS - FRONTEND + input logic pop_i, + // Data to be pushed - FRONTEND + input logic [riscv::VLEN-1:0] data_i, + // Popped data - FRONTEND + output ariane_pkg::ras_t data_o ); ariane_pkg::ras_t [DEPTH-1:0] stack_d, stack_q; diff --git a/core/instr_realign.sv b/core/instr_realign.sv index 043a13116d..93d4382260 100644 --- a/core/instr_realign.sv +++ b/core/instr_realign.sv @@ -25,15 +25,25 @@ module instr_realign #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty ) ( + // Subsystem Clock - SUBSYSTEM input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM input logic rst_ni, + // Fetch flush request - CONTROLLER input logic flush_i, + // 32-bit block is valid - CACHE input logic valid_i, - output logic serving_unaligned_o, // we have an unaligned instruction in [0] + // Instruction is unaligned - FRONTEND + output logic serving_unaligned_o, + // 32-bit block address - CACHE input logic [riscv::VLEN-1:0] address_i, + // 32-bit block - CACHE input logic [FETCH_WIDTH-1:0] data_i, + // instruction is valid - FRONTEND output logic [INSTR_PER_FETCH-1:0] valid_o, + // Instruction address - FRONTEND output logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] addr_o, + // Instruction - instr_scan, instr_queue output logic [INSTR_PER_FETCH-1:0][31:0] instr_o ); // as a maximum we support a fetch width of 64-bit, hence there can be 4 compressed instructions diff --git a/docs/04_cv32a6_design/.gitignore b/docs/04_cv32a65x_design/.gitignore similarity index 100% rename from docs/04_cv32a6_design/.gitignore rename to docs/04_cv32a65x_design/.gitignore diff --git a/docs/04_cv32a6_design/Makefile b/docs/04_cv32a65x_design/Makefile similarity index 100% rename from docs/04_cv32a6_design/Makefile rename to docs/04_cv32a65x_design/Makefile diff --git a/docs/04_cv32a6_design/images/CVA6_subsystems.png b/docs/04_cv32a65x_design/images/CVA6_subsystems.png similarity index 100% rename from docs/04_cv32a6_design/images/CVA6_subsystems.png rename to docs/04_cv32a65x_design/images/CVA6_subsystems.png diff --git a/docs/04_cv32a6_design/images/LZC.png b/docs/04_cv32a65x_design/images/LZC.png similarity index 100% rename from docs/04_cv32a6_design/images/LZC.png rename to docs/04_cv32a65x_design/images/LZC.png diff --git a/docs/04_cv32a6_design/images/RR.png b/docs/04_cv32a65x_design/images/RR.png similarity index 100% rename from docs/04_cv32a6_design/images/RR.png rename to docs/04_cv32a65x_design/images/RR.png diff --git a/docs/04_cv32a6_design/images/ariane_overview.drawio.png b/docs/04_cv32a65x_design/images/ariane_overview.drawio.png similarity index 100% rename from docs/04_cv32a6_design/images/ariane_overview.drawio.png rename to docs/04_cv32a65x_design/images/ariane_overview.drawio.png diff --git a/docs/04_cv32a6_design/images/ariane_overview.png b/docs/04_cv32a65x_design/images/ariane_overview.png similarity index 100% rename from docs/04_cv32a6_design/images/ariane_overview.png rename to docs/04_cv32a65x_design/images/ariane_overview.png diff --git a/docs/04_cv32a6_design/images/bht.png b/docs/04_cv32a65x_design/images/bht.png similarity index 100% rename from docs/04_cv32a6_design/images/bht.png rename to docs/04_cv32a65x_design/images/bht.png diff --git a/docs/04_cv32a6_design/images/cva6_tlb_entry.png b/docs/04_cv32a65x_design/images/cva6_tlb_entry.png similarity index 100% rename from docs/04_cv32a6_design/images/cva6_tlb_entry.png rename to docs/04_cv32a65x_design/images/cva6_tlb_entry.png diff --git a/docs/04_cv32a6_design/images/cva6_tlb_hit.png b/docs/04_cv32a65x_design/images/cva6_tlb_hit.png similarity index 100% rename from docs/04_cv32a6_design/images/cva6_tlb_hit.png rename to docs/04_cv32a65x_design/images/cva6_tlb_hit.png diff --git a/docs/04_cv32a6_design/images/frontend_modules.png b/docs/04_cv32a65x_design/images/frontend_modules.png similarity index 100% rename from docs/04_cv32a6_design/images/frontend_modules.png rename to docs/04_cv32a65x_design/images/frontend_modules.png diff --git a/docs/04_cv32a6_design/images/in_out_tlb.png b/docs/04_cv32a65x_design/images/in_out_tlb.png similarity index 100% rename from docs/04_cv32a6_design/images/in_out_tlb.png rename to docs/04_cv32a65x_design/images/in_out_tlb.png diff --git a/docs/04_cv32a6_design/images/mmu_control_flow.png b/docs/04_cv32a65x_design/images/mmu_control_flow.png similarity index 100% rename from docs/04_cv32a6_design/images/mmu_control_flow.png rename to docs/04_cv32a65x_design/images/mmu_control_flow.png diff --git a/docs/04_cv32a6_design/images/mmu_in_out.png b/docs/04_cv32a65x_design/images/mmu_in_out.png similarity index 100% rename from docs/04_cv32a6_design/images/mmu_in_out.png rename to docs/04_cv32a65x_design/images/mmu_in_out.png diff --git a/docs/04_cv32a6_design/images/mmu_major_blocks.png b/docs/04_cv32a65x_design/images/mmu_major_blocks.png similarity index 100% rename from docs/04_cv32a6_design/images/mmu_major_blocks.png rename to docs/04_cv32a65x_design/images/mmu_major_blocks.png diff --git a/docs/04_cv32a6_design/images/openhw-landscape.svg b/docs/04_cv32a65x_design/images/openhw-landscape.svg similarity index 100% rename from docs/04_cv32a6_design/images/openhw-landscape.svg rename to docs/04_cv32a65x_design/images/openhw-landscape.svg diff --git a/docs/04_cv32a6_design/images/plru_tree_indexing.png b/docs/04_cv32a65x_design/images/plru_tree_indexing.png similarity index 100% rename from docs/04_cv32a6_design/images/plru_tree_indexing.png rename to docs/04_cv32a65x_design/images/plru_tree_indexing.png diff --git a/docs/04_cv32a6_design/images/ptw_dptw.png b/docs/04_cv32a65x_design/images/ptw_dptw.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_dptw.png rename to docs/04_cv32a65x_design/images/ptw_dptw.png diff --git a/docs/04_cv32a6_design/images/ptw_dptw_s.png b/docs/04_cv32a65x_design/images/ptw_dptw_s.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_dptw_s.png rename to docs/04_cv32a65x_design/images/ptw_dptw_s.png diff --git a/docs/04_cv32a6_design/images/ptw_idle.png b/docs/04_cv32a65x_design/images/ptw_idle.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_idle.png rename to docs/04_cv32a65x_design/images/ptw_idle.png diff --git a/docs/04_cv32a6_design/images/ptw_in_out.png b/docs/04_cv32a65x_design/images/ptw_in_out.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_in_out.png rename to docs/04_cv32a65x_design/images/ptw_in_out.png diff --git a/docs/04_cv32a6_design/images/ptw_iptw.png b/docs/04_cv32a65x_design/images/ptw_iptw.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_iptw.png rename to docs/04_cv32a65x_design/images/ptw_iptw.png diff --git a/docs/04_cv32a6_design/images/ptw_mis_sup.png b/docs/04_cv32a65x_design/images/ptw_mis_sup.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_mis_sup.png rename to docs/04_cv32a65x_design/images/ptw_mis_sup.png diff --git a/docs/04_cv32a6_design/images/ptw_nlvl.png b/docs/04_cv32a65x_design/images/ptw_nlvl.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_nlvl.png rename to docs/04_cv32a65x_design/images/ptw_nlvl.png diff --git a/docs/04_cv32a6_design/images/ptw_pte_1.png b/docs/04_cv32a65x_design/images/ptw_pte_1.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_pte_1.png rename to docs/04_cv32a65x_design/images/ptw_pte_1.png diff --git a/docs/04_cv32a6_design/images/ptw_pte_flowchart.png b/docs/04_cv32a65x_design/images/ptw_pte_flowchart.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_pte_flowchart.png rename to docs/04_cv32a65x_design/images/ptw_pte_flowchart.png diff --git a/docs/04_cv32a6_design/images/ptw_state_diagram.png b/docs/04_cv32a65x_design/images/ptw_state_diagram.png similarity index 100% rename from docs/04_cv32a6_design/images/ptw_state_diagram.png rename to docs/04_cv32a65x_design/images/ptw_state_diagram.png diff --git a/docs/04_cv32a6_design/images/replacement_entry.png b/docs/04_cv32a65x_design/images/replacement_entry.png similarity index 100% rename from docs/04_cv32a6_design/images/replacement_entry.png rename to docs/04_cv32a65x_design/images/replacement_entry.png diff --git a/docs/04_cv32a6_design/images/sfence_vaddr_asid.png b/docs/04_cv32a65x_design/images/sfence_vaddr_asid.png similarity index 100% rename from docs/04_cv32a6_design/images/sfence_vaddr_asid.png rename to docs/04_cv32a65x_design/images/sfence_vaddr_asid.png diff --git a/docs/04_cv32a6_design/images/sfence_vaddr_x0.png b/docs/04_cv32a65x_design/images/sfence_vaddr_x0.png similarity index 100% rename from docs/04_cv32a6_design/images/sfence_vaddr_x0.png rename to docs/04_cv32a65x_design/images/sfence_vaddr_x0.png diff --git a/docs/04_cv32a6_design/images/sfence_x0_asid.png b/docs/04_cv32a65x_design/images/sfence_x0_asid.png similarity index 100% rename from docs/04_cv32a6_design/images/sfence_x0_asid.png rename to docs/04_cv32a65x_design/images/sfence_x0_asid.png diff --git a/docs/04_cv32a6_design/images/sfence_x0_x0.png b/docs/04_cv32a65x_design/images/sfence_x0_x0.png similarity index 100% rename from docs/04_cv32a6_design/images/sfence_x0_x0.png rename to docs/04_cv32a65x_design/images/sfence_x0_x0.png diff --git a/docs/04_cv32a6_design/images/shared_tlb.png b/docs/04_cv32a65x_design/images/shared_tlb.png similarity index 100% rename from docs/04_cv32a6_design/images/shared_tlb.png rename to docs/04_cv32a65x_design/images/shared_tlb.png diff --git a/docs/04_cv32a6_design/images/shared_tlb_in_out.png b/docs/04_cv32a65x_design/images/shared_tlb_in_out.png similarity index 100% rename from docs/04_cv32a6_design/images/shared_tlb_in_out.png rename to docs/04_cv32a65x_design/images/shared_tlb_in_out.png diff --git a/docs/04_cv32a6_design/images/shared_tlb_set.png b/docs/04_cv32a65x_design/images/shared_tlb_set.png similarity index 100% rename from docs/04_cv32a6_design/images/shared_tlb_set.png rename to docs/04_cv32a65x_design/images/shared_tlb_set.png diff --git a/docs/04_cv32a6_design/images/subsystems.png b/docs/04_cv32a65x_design/images/subsystems.png similarity index 100% rename from docs/04_cv32a6_design/images/subsystems.png rename to docs/04_cv32a65x_design/images/subsystems.png diff --git a/docs/04_cv32a6_design/images/update_tree.png b/docs/04_cv32a65x_design/images/update_tree.png similarity index 100% rename from docs/04_cv32a6_design/images/update_tree.png rename to docs/04_cv32a65x_design/images/update_tree.png diff --git a/docs/04_cv32a6_design/make.bat b/docs/04_cv32a65x_design/make.bat similarity index 100% rename from docs/04_cv32a6_design/make.bat rename to docs/04_cv32a65x_design/make.bat diff --git a/docs/04_cv32a6_design/requirements.txt b/docs/04_cv32a65x_design/requirements.txt similarity index 100% rename from docs/04_cv32a6_design/requirements.txt rename to docs/04_cv32a65x_design/requirements.txt diff --git a/docs/04_cv32a6_design/source/AXI.rst b/docs/04_cv32a65x_design/source/AXI.rst similarity index 100% rename from docs/04_cv32a6_design/source/AXI.rst rename to docs/04_cv32a65x_design/source/AXI.rst diff --git a/docs/04_cv32a6_design/source/CSRs.rst b/docs/04_cv32a65x_design/source/CSRs.rst similarity index 100% rename from docs/04_cv32a6_design/source/CSRs.rst rename to docs/04_cv32a65x_design/source/CSRs.rst diff --git a/docs/04_cv32a6_design/source/CVXIF.rst b/docs/04_cv32a65x_design/source/CVXIF.rst similarity index 100% rename from docs/04_cv32a6_design/source/CVXIF.rst rename to docs/04_cv32a65x_design/source/CVXIF.rst diff --git a/docs/04_cv32a6_design/source/architecture.rst b/docs/04_cv32a65x_design/source/architecture.rst similarity index 100% rename from docs/04_cv32a6_design/source/architecture.rst rename to docs/04_cv32a65x_design/source/architecture.rst diff --git a/docs/04_cv32a6_design/source/conf.py b/docs/04_cv32a65x_design/source/conf.py similarity index 100% rename from docs/04_cv32a6_design/source/conf.py rename to docs/04_cv32a65x_design/source/conf.py diff --git a/docs/04_cv32a6_design/source/csr.rst b/docs/04_cv32a65x_design/source/csr.rst similarity index 100% rename from docs/04_cv32a6_design/source/csr.rst rename to docs/04_cv32a65x_design/source/csr.rst diff --git a/docs/04_cv32a6_design/source/csr_list.rst b/docs/04_cv32a65x_design/source/csr_list.rst similarity index 100% rename from docs/04_cv32a6_design/source/csr_list.rst rename to docs/04_cv32a65x_design/source/csr_list.rst diff --git a/docs/04_cv32a6_design/source/cv32a6_execute.rst b/docs/04_cv32a65x_design/source/cv32a6_execute.rst similarity index 100% rename from docs/04_cv32a6_design/source/cv32a6_execute.rst rename to docs/04_cv32a65x_design/source/cv32a6_execute.rst diff --git a/docs/04_cv32a6_design/source/cv32a6_frontend.rst b/docs/04_cv32a65x_design/source/cv32a6_frontend.rst similarity index 52% rename from docs/04_cv32a6_design/source/cv32a6_frontend.rst rename to docs/04_cv32a65x_design/source/cv32a6_frontend.rst index 89ffb0ec77..a7d9250849 100644 --- a/docs/04_cv32a6_design/source/cv32a6_frontend.rst +++ b/docs/04_cv32a65x_design/source/cv32a6_frontend.rst @@ -29,131 +29,7 @@ The module is connected to: * EXECUTE, CONTROLLER, CSR and COMMIT modules triggers PC jumping due to a branch mispredict, an exception, a return from exception, a debug entry or pipeline flush. They provides related PC next value. * CSR module states about debug mode. - -.. list-table:: FRONTEND interface signals - :header-rows: 1 - - * - Signal - - IO - - connection - - Type - - Description - - * - ``clk_i`` - - in - - SUBSYSTEM - - logic - - Subsystem Clock - - * - ``rst_ni`` - - in - - SUBSYSTEM - - logic - - Asynchronous reset active low - - * - ``debug_mode_i`` - - in - - CSR - - logic - - Debug mode state - - * - ``flush_i`` - - in - - CONTROLLER - - logic - - Fetch flush request - - * - ``flush_bp_i`` - - in - - tied at zero - - logic - - flush branch prediction - - * - ``boot_addr_i`` - - in - - SUBSYSTEM - - logic[VLEN-1:0] - - Next PC when reset - - * - ``resolved_branch_i`` - - in - - EXECUTE - - bp_resolve_t - - mispredict event and next PC - - * - ``eret_i`` - - in - - CSR - - logic - - Return from exception event - - * - ``epc_i`` - - in - - CSR - - logic[VLEN-1:0] - - Next PC when returning from exception - - * - ``ex_valid_i`` - - in - - COMMIT - - logic - - Exception event - - * - ``trap_vector_base_i`` - - in - - CSR - - logic[VLEN-1:0] - - Next PC when jumping into exception - - * - ``set_pc_commit_i`` - - in - - CONTROLLER - - logic - - Set the PC coming from COMMIT as next PC - - - * - ``pc_commit_i`` - - in - - COMMIT - - logic[VLEN-1:0] - - Next PC when flushing pipeline - - * - ``set_debug_pc_i`` - - in - - CSR - - logic - - Debug event - - * - ``icache_dreq_o`` - - out - - CACHES - - icache_dreq_t - - Handshake between CACHE and FRONTEND (fetch) - - * - ``icache_dreq_i`` - - in - - CACHES - - icache_drsp_t - - Handshake between CACHE and FRONTEND (fetch) - - * - ``fetch_entry_o`` - - out - - DECODE - - fetch_entry_t - - Handshake's data between FRONTEND (fetch) and DECODE - - * - ``fetch_entry_valid_o`` - - out - - DECODE - - logic - - Handshake's valid between FRONTEND (fetch) and DECODE - - * - ``fetch_entry_ready_i`` - - in - - DECODE - - logic - - Handshake's ready between FRONTEND (fetch) and DECODE - +.. include:: port_frontend.rst Functionality ------------- @@ -218,74 +94,7 @@ Architecture and Submodules Instr_realign submodule ~~~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: instr_realign interface signals - :header-rows: 1 - - * - Signal - - IO - - connection - - Type - - Description - - * - ``clk_i`` - - in - - SUBSYSTEM - - logic - - Subystem Clock - - * - ``rst_ni`` - - in - - SUBSYSTEM - - logic - - Asynchronous reset active low - - * - ``flush_i`` - - in - - FRONTEND - - logic - - Instr_align Flush - - * - ``valid_i`` - - in - - CACHES (reg) - - logic - - 32-bit block is valid - - * - ``address_i`` - - in - - CACHES (reg) - - logic[VLEN-1:0] - - 32-bit block address - - * - ``data_i`` - - in - - CACHES (reg) - - logic[31:0] - - 32-bit block - - * - ``valid_o`` - - out - - FRONTEND - - logic[1:0] - - instruction is valid - - * - ``addr_o`` - - out - - FRONTEND - - logic[1:0][VLEN-1:0] - - Instruction address - - * - ``instr_o`` - - out - - instr_scan, instr_queue - - logic[1:0][31:0] - - Instruction - - * - ``serving_unaligned_o`` - - out - - FRONTEND - - logic - - Instruction is unaligned +.. include:: port_instr_realign.rst The 32-bit aligned block coming from the CACHE module enters the instr_realign submodule. This submodule extracts the instructions from the 32-bit blocks, up to two instructions because it is possible to fetch two instructions when C extension is used. If the instructions are not compressed, it is possible that the instruction is not aligned on the block size but rather interleaved with two cache blocks. In that case, two cache accesses are needed. The instr_realign submodule provides at maximum one instruction per cycle. Not complete instruction is stored in instr_realign submodule before being provided in the next cycles. @@ -296,116 +105,7 @@ In case of mispredict, flush, replay or branch predict, the instr_realign is re- Instr_queue submodule ~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: instr_realign interface signals - :header-rows: 1 - - * - Signal - - IO - - connection - - Type - - Description - - * - ``clk_i`` - - in - - SUBSYSTEM - - logic - - Subystem Clock - - * - ``rst_ni`` - - in - - SUBSYSTEM - - logic - - Asynchronous reset active low - - * - ``flush_i`` - - in - - CONTROLLER - - logic - - Fetch flush request - - * - ``valid_i`` - - in - - instr_realign - - logic[1:0] - - Instruction is valid - - * - ``instr_i`` - - in - - instr_realign - - logic[1:0][31:0] - - Instruction - - * - ``addr_i`` - - in - - instr_realign - - logic[1:0][VLEN-1:0] - - Instruction address - - * - ``predict_address_i`` - - in - - FRONTEND - - logic[VLEN-1:0] - - Instruction predict address - - * - ``cf_type_i`` - - in - - FRONTEND - - logic[1:0] - - Instruction control flow type - - * - ``ready_o`` - - out - - CACHES - - logic - - Handshake's ready between CACHE and FRONTEND (fetch stage) - - * - ``consumed_o`` - - out - - FRONTEND - - logic[1:0] - - Indicates instructions consummed, that is to say popped by DECODE - - * - ``exception_i`` - - in - - CACHES (reg) - - logic - - Exception - - * - ``exception_addr_i`` - - in - - CACHES (reg) - - logic[VLEN-1:0] - - Exception address - - * - ``replay_o`` - - out - - FRONTEND - - logic - - Replay instruction because one of the FIFO was already full - - * - ``replay_addr_o`` - - out - - FRONTEND - - logic[VLEN-1:0] - - Address at which to replay the fetch - - * - ``fetch_entry_o`` - - out - - DECODE - - fetch_entry_t - - Handshake's data between FRONTEND (fetch stage) and DECODE - - * - ``fetch_entry_valid_o`` - - out - - DECODE - - logic - - Handshake's valid between FRONTEND (fetch stage) and DECODE - - * - ``fetch_entry_ready_i`` - - in - - DECODE - - logic - - Handshake's ready between FRONTEND (fetch stage) and DECODE +.. include:: port_instr_queue.rst The instr_queue receives 32bit block from CACHES to create a valid stream of instructions to be decoded (by DECODE), to be issued (by ISSUE) and executed (by EXECUTE). FRONTEND pushes in FIFO to store the instructions and related information needed in case of mispredict or exception: instructions, instruction control flow type, exception, exception address and predicted address. DECODE pops them when decode stage is ready and indicates to the FRONTEND the instruction has been consummed. @@ -423,98 +123,7 @@ The instruction queue can be flushed by CONTROLLER. Instr_scan submodule ~~~~~~~~~~~~~~~~~~~~ -.. list-table:: instr_scan interface signals - :header-rows: 1 - - * - Signal - - IO - - Connection - - Type - - Description - - * - ``instr_i`` - - in - - instr_realign - - logic[31:0] - - Instruction to be predecoded - - * - ``rvi_return_o`` - - out - - FRONTEND - - logic - - Return instruction - - * - ``rvi_call_o`` - - out - - FRONTEND - - logic - - JAL instruction - - * - ``rvi_branch_o`` - - out - - FRONTEND - - logic - - Branch instruction - - * - ``rvi_jalr_o`` - - out - - FRONTEND - - logic - - JALR instruction - - * - ``rvi_jump_o`` - - out - - FRONTEND - - logic - - unconditional jump instruction - - * - ``rvi_imm_o`` - - out - - FRONTEND - - logic[VLEN-1:0] - - Instruction immediat - - * - ``rvc_branch_o`` - - out - - FRONTEND - - logic - - Branch compressed instruction - - * - ``rvc_jump_o`` - - out - - FRONTEND - - logic - - unconditional jump compressed instruction - - * - ``rvc_jr_o`` - - out - - FRONTEND - - logic - - JR compressed instruction - - * - ``rvc_return_o`` - - out - - FRONTEND - - logic - - Return compressed instruction - - * - ``rvc_jalr_o`` - - out - - FRONTEND - - logic - - JALR compressed instruction - - * - ``rvc_call_o`` - - out - - FRONTEND - - logic - - JAL compressed instruction - - * - ``rvc_imm_o`` - - out - - FRONTEND - - logic[VLEN-1:0] - - Instruction compressed immediat +.. include:: port_instr_scan.rst The instr_scan submodule pre-decodes the fetched instructions, instructions could be compressed or not. The outputs are used by the branch prediction feature. The instr_scan submodule tells if the instruction is compressed and provides the intruction type: branch, jump, return, jalr, imm, call or others. @@ -523,56 +132,7 @@ The instr_scan submodule pre-decodes the fetched instructions, instructions coul BHT (Branch History Table) submodule ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: BHT interface signals - :header-rows: 1 - - * - Signal - - IO - - Connection - - Type - - Description - - * - ``clk_i`` - - in - - SUBSYSTEM - - logic - - Subystem clock - - * - ``rst_ni`` - - in - - SUBSYSTEM - - logic - - Asynchronous reset active low - - * - ``flush_i`` - - in - - tied at zero - - logic - - Flush request - - * - ``debug_mode_i`` - - in - - CSR - - logic - - Debug mode state - - * - ``vpc_i`` - - in - - CACHES (reg) - - logic[VLEN-1:0] - - Virtual PC - - * - ``bht_update_i`` - - in - - EXECUTE - - bht_update_t - - Update bht with resolved address - - * - ``bht_prediction_o`` - - out - - FRONTEND - - bht_prediction_t - - Prediction from bht +.. include:: port_bht.rst When a branch instruction is resolved by the EXECUTE, the relative information is stored in the Branch History Table. @@ -598,56 +158,7 @@ The BHT is never flushed. BTB (Branch Target Buffer) submodule ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: BTB interface signals - :header-rows: 1 - - * - Signal - - IO - - Connection - - Type - - Description - - * - ``clk_i`` - - in - - SUBSYSTEM - - logic - - Subystem clock - - * - ``rst_ni`` - - in - - SUBSYSTEM - - logic - - Asynchronous reset active low - - * - ``flush_i`` - - in - - tied at zero - - logic - - Flush request state - - * - ``debug_mode_i`` - - in - - CSR - - logic - - Debug mode - - * - ``vpc_i`` - - in - - CACHES (reg) - - logic - - Virtual PC - - * - ``btb_update_i`` - - in - - EXECUTE - - btb_update_t - - Update BTB with resolved address - - * - ``btb_prediction_o`` - - out - - FRONTEND - - btb_prediction_t - - BTB Prediction +.. include:: port_btb.rst When a unconditional jumps to a register (JALR instruction) is mispredicted by the EXECUTE, the relative information is stored into the BTB, that is to say the JALR PC and the target address. @@ -665,56 +176,7 @@ The BTB is never flushed. RAS (Return Address Stack) submodule ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: RAS interface signals - :header-rows: 1 - - * - Signal - - IO - - Connection - - Type - - Description - - * - ``clk_i`` - - in - - SUBSYSTEM - - logic - - Subystem clock - - * - ``rst_ni`` - - in - - SUBSYSTEM - - logic - - Asynchronous reset active low - - * - ``flush_i`` - - in - - tied at zero - - logic - - Flush request - - * - ``push_i`` - - in - - FRONTEND - - logic - - Push address in RAS - - * - ``pop_i`` - - in - - FRONTEND - - logic - - Pop address from RAS - - * - ``data_i`` - - in - - FRONTEND - - logic[VLEN-1:0] - - Data to be pushed - - * - ``data_o`` - - out - - FRONTEND - - ras_t - - Popped data +.. include:: port_ras.rst When an unconditional jumps to a known target address (JAL instruction) is consummed by the instr_queue, the next pc after the JAL instruction and the return address are stored into a FIFO. diff --git a/docs/04_cv32a6_design/source/cv32a6_glossary.rst b/docs/04_cv32a65x_design/source/cv32a6_glossary.rst similarity index 100% rename from docs/04_cv32a6_design/source/cv32a6_glossary.rst rename to docs/04_cv32a65x_design/source/cv32a6_glossary.rst diff --git a/docs/04_cv32a6_design/source/functionality.rst b/docs/04_cv32a65x_design/source/functionality.rst similarity index 100% rename from docs/04_cv32a6_design/source/functionality.rst rename to docs/04_cv32a65x_design/source/functionality.rst diff --git a/docs/04_cv32a6_design/source/index.rst b/docs/04_cv32a65x_design/source/index.rst similarity index 95% rename from docs/04_cv32a6_design/source/index.rst rename to docs/04_cv32a65x_design/source/index.rst index 90b5a6f884..13cab6d172 100644 --- a/docs/04_cv32a6_design/source/index.rst +++ b/docs/04_cv32a65x_design/source/index.rst @@ -8,7 +8,7 @@ Original Author: Jean-Roch COULON - Thales -CV32A60X Design Document +CV32A65X Design Document ======================== Editor: **Jean Roch Coulon** diff --git a/docs/04_cv32a6_design/source/instructions.rst b/docs/04_cv32a65x_design/source/instructions.rst similarity index 100% rename from docs/04_cv32a6_design/source/instructions.rst rename to docs/04_cv32a65x_design/source/instructions.rst diff --git a/docs/04_cv32a6_design/source/intro.rst b/docs/04_cv32a65x_design/source/intro.rst similarity index 98% rename from docs/04_cv32a6_design/source/intro.rst rename to docs/04_cv32a65x_design/source/intro.rst index 58898f9d79..20e808b01f 100644 --- a/docs/04_cv32a6_design/source/intro.rst +++ b/docs/04_cv32a65x_design/source/intro.rst @@ -13,7 +13,7 @@ Introduction ============ The OpenHW Group uses `semantic versioning `_ to describe the release status of its IP. -This document describes the CV32A60X configuration version of CVA6. +This document describes the CV32A65X configuration version of CVA6. This intends to be the first formal release of CVA6. CVA6 is a 6-stage in-order and single issue processor core which implements the RISC-V instruction set. diff --git a/docs/04_cv32a6_design/source/overview.rst b/docs/04_cv32a65x_design/source/overview.rst similarity index 100% rename from docs/04_cv32a6_design/source/overview.rst rename to docs/04_cv32a65x_design/source/overview.rst diff --git a/docs/04_cv32a65x_design/source/port_bht.rst b/docs/04_cv32a65x_design/source/port_bht.rst new file mode 100644 index 0000000000..07b889767e --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_bht.rst @@ -0,0 +1,61 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_bht: + +.. list-table:: bht module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``flush_i`` + - in + - CONTROLLER + - logic + - Fetch flush request + + * - ``debug_mode_i`` + - in + - CSR + - logic + - Debug mode state + + * - ``vpc_i`` + - in + - CACHE + - logic [riscv::VLEN-1:0] + - Virtual PC + + * - ``bht_update_i`` + - in + - EXECUTE + - ariane_pkg::bht_update_t + - Update bht with resolved address + + * - ``bht_prediction_o`` + - out + - FRONTEND + - ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - Prediction from bht diff --git a/docs/04_cv32a65x_design/source/port_btb.rst b/docs/04_cv32a65x_design/source/port_btb.rst new file mode 100644 index 0000000000..b06f6ea616 --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_btb.rst @@ -0,0 +1,61 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_btb: + +.. list-table:: btb module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``flush_i`` + - in + - CONTROLLER + - logic + - Fetch flush request + + * - ``debug_mode_i`` + - in + - CSR + - logic + - Debug mode state + + * - ``vpc_i`` + - in + - CACHE + - logic [riscv::VLEN-1:0] + - Virtual PC + + * - ``btb_update_i`` + - in + - EXECUTE + - ariane_pkg::btb_update_t + - Update BTB with resolved address + + * - ``btb_prediction_o`` + - out + - FRONTEND + - ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - BTB Prediction diff --git a/docs/04_cv32a65x_design/source/port_cva6.rst b/docs/04_cv32a65x_design/source/port_cva6.rst new file mode 100644 index 0000000000..6880c67826 --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_cva6.rst @@ -0,0 +1,97 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_cva6: + +.. list-table:: cva6 module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``boot_addr_i`` + - in + - SUBSYSTEM + - logic [riscv::VLEN-1:0] + - Reset boot address + + * - ``hart_id_i`` + - in + - SUBSYSTEM + - logic [riscv::XLEN-1:0] + - Hard ID reflected as CSR + + * - ``irq_i`` + - in + - SUBSYSTEM + - logic [1:0] + - Level sensitive (async) interrupts + + * - ``ipi_i`` + - in + - SUBSYSTEM + - logic + - Inter-processor (async) interrupt + + * - ``time_irq_i`` + - in + - SUBSYSTEM + - logic + - Timer (async) interrupt + + * - ``debug_req_i`` + - in + - SUBSYSTEM + - logic + - Debug (async) request + + * - ``rvfi_probes_o`` + - out + - SUBSYSTEM + - rvfi_probes_t + - Probes to build RVFI, can be left open when not used + + * - ``cvxif_req_o`` + - out + - SUBSYSTEM + - cvxif_req_t + - CVXIF request + + * - ``cvxif_resp_i`` + - in + - SUBSYSTEM + - cvxif_resp_t + - CVXIF response + + * - ``noc_req_o`` + - out + - SUBSYSTEM + - noc_req_t + - noc request, can be AXI or OpenPiton + + * - ``noc_resp_i`` + - in + - SUBSYSTEM + - noc_resp_t + - noc response, can be AXI or OpenPiton diff --git a/docs/04_cv32a65x_design/source/port_frontend.rst b/docs/04_cv32a65x_design/source/port_frontend.rst new file mode 100644 index 0000000000..acaf07d8fb --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_frontend.rst @@ -0,0 +1,139 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_frontend: + +.. list-table:: frontend module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``flush_i`` + - in + - CONTROLLER + - logic + - Fetch flush request + + * - ``flush_bp_i`` + - in + - zero + - logic + - flush branch prediction + + * - ``halt_i`` + - in + - CONTROLLER + - logic + - halt commit stage + + * - ``debug_mode_i`` + - in + - CSR + - logic + - Debug mode state + + * - ``boot_addr_i`` + - in + - SUBSYSTEM + - logic [riscv::VLEN-1:0] + - Next PC when reset + + * - ``resolved_branch_i`` + - in + - EXECUTE + - bp_resolve_t + - mispredict event and next PC + + * - ``set_pc_commit_i`` + - in + - CONTROLLER + - logic + - Set the PC coming from COMMIT as next PC + + * - ``pc_commit_i`` + - in + - COMMIT + - logic [riscv::VLEN-1:0] + - Next PC when flushing pipeline + + * - ``epc_i`` + - in + - CSR + - logic [riscv::VLEN-1:0] + - Next PC when returning from exception + + * - ``eret_i`` + - in + - CSR + - logic + - Return from exception event + + * - ``trap_vector_base_i`` + - in + - CSR + - logic [riscv::VLEN-1:0] + - Next PC when jumping into exception + + * - ``ex_valid_i`` + - in + - COMMIT + - logic + - Exception event + + * - ``set_debug_pc_i`` + - in + - CSR + - logic + - Debug event + + * - ``icache_dreq_o`` + - out + - CACHES + - icache_dreq_t + - Handshake between CACHE and FRONTEND (fetch) + + * - ``icache_dreq_i`` + - in + - CACHES + - icache_drsp_t + - Handshake between CACHE and FRONTEND (fetch) + + * - ``fetch_entry_o`` + - out + - DECODE + - fetch_entry_t + - Handshake's data between fetch and decode + + * - ``fetch_entry_valid_o`` + - out + - DECODE + - logic + - Handshake's valid between fetch and decode + + * - ``fetch_entry_ready_i`` + - in + - DECODE + - logic + - Handshake's ready between fetch and decode diff --git a/docs/04_cv32a65x_design/source/port_instr_queue.rst b/docs/04_cv32a65x_design/source/port_instr_queue.rst new file mode 100644 index 0000000000..a6042c2d53 --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_instr_queue.rst @@ -0,0 +1,121 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_instr_queue: + +.. list-table:: instr_queue module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``flush_i`` + - in + - CONTROLLER + - logic + - Fetch flush request + + * - ``instr_i`` + - in + - instr_realign + - logic [ariane_pkg::INSTR_PER_FETCH-1:0][31:0] + - Instruction + + * - ``addr_i`` + - in + - instr_realign + - logic [ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - Instruction address + + * - ``valid_i`` + - in + - instr_realign + - logic [ariane_pkg::INSTR_PER_FETCH-1:0] + - Instruction is valid + + * - ``ready_o`` + - out + - CACHE + - logic + - Handshake’s ready with CACHE + + * - ``consumed_o`` + - out + - FRONTEND + - logic [ariane_pkg::INSTR_PER_FETCH-1:0] + - Indicates instructions consummed, or popped by DECODE + + * - ``exception_i`` + - in + - CACHE + - ariane_pkg::frontend_exception_t + - Exception (which is page-table fault) + + * - ``exception_addr_i`` + - in + - CACHE + - logic [riscv::VLEN-1:0] + - Exception address + + * - ``predict_address_i`` + - in + - FRONTEND + - logic [riscv::VLEN-1:0] + - Branch predict + + * - ``cf_type_i`` + - in + - FRONTEND + - ariane_pkg::cf_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - Instruction predict address + + * - ``replay_o`` + - out + - FRONTEND + - logic + - Replay instruction because one of the FIFO was full + + * - ``replay_addr_o`` + - out + - FRONTEND + - logic [riscv::VLEN-1:0] + - Address at which to replay the fetch + + * - ``fetch_entry_o`` + - out + - DECODE + - ariane_pkg::fetch_entry_t + - Handshake’s data with DECODE + + * - ``fetch_entry_valid_o`` + - out + - DECODE + - logic + - Handshake’s valid with DECODE + + * - ``fetch_entry_ready_i`` + - in + - DECODE + - logic + - Handshake’s ready with DECODE diff --git a/docs/04_cv32a65x_design/source/port_instr_realign.rst b/docs/04_cv32a65x_design/source/port_instr_realign.rst new file mode 100644 index 0000000000..754ada7c52 --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_instr_realign.rst @@ -0,0 +1,79 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_instr_realign: + +.. list-table:: instr_realign module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``flush_i`` + - in + - CONTROLLER + - logic + - Fetch flush request + + * - ``valid_i`` + - in + - CACHE + - logic + - 32-bit block is valid + + * - ``serving_unaligned_o`` + - out + - FRONTEND + - logic + - Instruction is unaligned + + * - ``address_i`` + - in + - CACHE + - logic [riscv::VLEN-1:0] + - 32-bit block address + + * - ``data_i`` + - in + - CACHE + - logic [FETCH_WIDTH-1:0] + - 32-bit block + + * - ``valid_o`` + - out + - FRONTEND + - logic [INSTR_PER_FETCH-1:0] + - instruction is valid + + * - ``addr_o`` + - out + - FRONTEND + - logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - Instruction address + + * - ``instr_o`` + - out + - none + - logic [INSTR_PER_FETCH-1:0][31:0] + - none diff --git a/docs/04_cv32a65x_design/source/port_instr_scan.rst b/docs/04_cv32a65x_design/source/port_instr_scan.rst new file mode 100644 index 0000000000..cf8b5d5b6b --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_instr_scan.rst @@ -0,0 +1,103 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_instr_scan: + +.. list-table:: instr_scan module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``instr_i`` + - in + - instr_realign + - logic [31:0] + - Instruction to be predecoded + + * - ``rvi_return_o`` + - out + - FRONTEND + - logic + - Return instruction + + * - ``rvi_call_o`` + - out + - FRONTEND + - logic + - JAL instruction + + * - ``rvi_branch_o`` + - out + - FRONTEND + - logic + - Branch instruction + + * - ``rvi_jalr_o`` + - out + - FRONTEND + - logic + - JALR instruction + + * - ``rvi_jump_o`` + - out + - FRONTEND + - logic + - Unconditional jump instruction + + * - ``rvi_imm_o`` + - out + - FRONTEND + - logic [riscv::VLEN-1:0] + - Instruction immediat + + * - ``rvc_branch_o`` + - out + - FRONTEND + - logic + - Branch compressed instruction + + * - ``rvc_jump_o`` + - out + - FRONTEND + - logic + - Unconditional jump compressed instruction + + * - ``rvc_jr_o`` + - out + - FRONTEND + - logic + - JR compressed instruction + + * - ``rvc_return_o`` + - out + - FRONTEND + - logic + - Return compressed instruction + + * - ``rvc_jalr_o`` + - out + - FRONTEND + - logic + - JALR compressed instruction + + * - ``rvc_call_o`` + - out + - FRONTEND + - logic + - JAL compressed instruction + + * - ``rvc_imm_o`` + - out + - FRONTEND + - logic [riscv::VLEN-1:0] + - Instruction compressed immediat diff --git a/docs/04_cv32a65x_design/source/port_ras.rst b/docs/04_cv32a65x_design/source/port_ras.rst new file mode 100644 index 0000000000..b50978d61f --- /dev/null +++ b/docs/04_cv32a65x_design/source/port_ras.rst @@ -0,0 +1,61 @@ +.. + Copyright 2024 Thales DIS France SAS + Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); + you may not use this file except in compliance with the License. + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + You may obtain a copy of the License at https://solderpad.org/licenses/ + + Original Author: Jean-Roch COULON - Thales + +.. _CVA6_ras: + +.. list-table:: ras module IO ports + :header-rows: 1 + + * - Signal + - IO + - Connection + - Type + - Description + + * - ``clk_i`` + - in + - SUBSYSTEM + - logic + - Subsystem Clock + + * - ``rst_ni`` + - in + - SUBSYSTEM + - logic + - Asynchronous reset active low + + * - ``flush_i`` + - in + - CONTROLLER + - logic + - Fetch flush request + + * - ``push_i`` + - in + - FRONTEND + - logic + - Push address in RAS + + * - ``pop_i`` + - in + - FRONTEND + - logic + - Pop address from RAS + + * - ``data_i`` + - in + - FRONTEND + - logic [riscv::VLEN-1:0] + - Data to be pushed + + * - ``data_o`` + - out + - FRONTEND + - ariane_pkg::ras_t + - Popped data diff --git a/docs/04_cv32a6_design/source/subsystem.rst b/docs/04_cv32a65x_design/source/subsystem.rst similarity index 65% rename from docs/04_cv32a6_design/source/subsystem.rst rename to docs/04_cv32a65x_design/source/subsystem.rst index 100e9f46bb..510c7cc814 100644 --- a/docs/04_cv32a6_design/source/subsystem.rst +++ b/docs/04_cv32a65x_design/source/subsystem.rst @@ -133,88 +133,4 @@ Parameter configuration IO ports -------- -.. list-table:: CV32A6 v0.1.0 parameterization - :header-rows: 1 - - * - Parameter - - Type - - Value - - Description - - * - ``CVA6Cfg`` - - ariane_pkg::cva6_cfg_t - - ariane_pkg::v0.1.0_Config - - CVA6 v0.1.0 configuration - -.. list-table:: CV32A6 v0.1.0 interface signals - :header-rows: 1 - - * - Signal - - IO - - Type - - Description - - * - ``clk_i`` - - in - - logic - - subsystem clock - - * - ``rst_ni`` - - in - - logic - - Asynchronous reset active low - - * - ``boot_addr_i`` - - in - - logic[VLEN-1:0] - - Reset boot address - - * - ``hart_id_i`` - - in - - logic[XLEN-1:0] - - Hart id in a multicore environment (reflected in a CSR) - - * - ``irq_i`` - - in - - logic[1:0] - - Level sensitive IR lines, mip & sip (async) - - * - ``ipi_i`` - - in - - logic - - Inter-processor interrupts (async) - - * - ``time_irq_i`` - - in - - logic - - Timer interrupt in (async) - - * - ``debug_req_i`` - - in - - logic - - Debug request (async) - - * - ``rvfi_o`` - - out - - trace_port_t - - RISC-V Formal Interface port (RVFI) - - * - ``cvxif_req_o`` - - out - - cvxif_req_t - - Coprocessor Interface request interface port (CV-X-IF) - - * - ``cvxif_resp_i`` - - in - - cvxif_resp_t - - Coprocessor Interface response interface port (CV-X-IF) - - * - ``axi_req_o`` - - out - - req_t - - AXI master request interface port - - * - ``axi_resp_i`` - - in - - resp_t - - AXI master response interface port +.. include:: port_cva6.rst diff --git a/docs/04_cv32a6_design/source/traps.rst b/docs/04_cv32a65x_design/source/traps.rst similarity index 100% rename from docs/04_cv32a6_design/source/traps.rst rename to docs/04_cv32a65x_design/source/traps.rst diff --git a/docs/index.rst b/docs/index.rst index 68b418057f..6f6ce1d30c 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -54,10 +54,10 @@ One of the key attributes of this document is to specify the feature set of spec This document focuses on _what_ the CVA6 does, without detailed consideration of _how_ a specific requirement is implemented. The target audience of this document is current and existing members of the OpenHW Group who wish to participate in the definition of future cores based on the CVA6. -The :doc:`CVA6 Design Document <03_cva6_design/index>` describes in detail the **CVA6**, the code base that can be used to compile/synthesize a specific core instance (e.g. cv32a6). +The :doc:`CVA6 Design Document <03_cva6_design/index>` describes in detail the **CVA6**, the code base that can be used to compile/synthesize a specific core instance (e.g. cv32a65x). -The :doc:`CV32A6 Design Document <04_cv32a6_design/source/index>` describes in detail the **CV32A6**, a specific core based on the CVA6 and the first production quality 32-bit application processor derived from the CVA6. -The primary audience for this documentation are design and verification engineers working to bring the CV32A6 to TRL-5. +The :doc:`CV32A65X Design Document <04_cv32a65x_design/source/index>` describes in detail the **CV32A65X**, a specific core based on the CVA6 and the first production quality 32-bit application processor derived from the CVA6. +The primary audience for this documentation are design and verification engineers working to bring the CV32A65X to TRL-5. The :doc:`CVA6 APU <05_cva6_apu/index>` describes an Application Processor Unit built around the CVA6. @@ -68,6 +68,6 @@ The :doc:`CVA6 APU <05_cva6_apu/index>` describes an Application Processor Unit 01_cva6_user/index.rst 02_cva6_requirements/cva6_requirements_specification.rst 03_cva6_design/index.rst - 04_cv32a6_design/source/index.rst + 04_cv32a65x_design/source/index.rst 05_cva6_apu/index.rst diff --git a/docs/scripts/table_port_builder.py b/docs/scripts/table_port_builder.py new file mode 100755 index 0000000000..101aeb6e38 --- /dev/null +++ b/docs/scripts/table_port_builder.py @@ -0,0 +1,96 @@ +# Copyright 2024 Thales DIS France SAS +# +# Licensed under the Solderpad Hardware License, Version 2.1 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Jean-Roch COULON - Thales + +#!/usr/bin/python3 + +import re + + +class PortIO: + def __init__( + self, + name, + direction, + data_type, + description, + connection, + ): + self.name = name + self.direction = direction + self.data_type = data_type + self.description = description + self.connection = connection + + +if __name__ == "__main__": + file = [] + file.append("../core/cva6.sv") + file.append("../core/frontend/frontend.sv") + file.append("../core/frontend/bht.sv") + file.append("../core/frontend/btb.sv") + file.append("../core/frontend/ras.sv") + file.append("../core/frontend/instr_queue.sv") + file.append("../core/frontend/instr_scan.sv") + file.append("../core/instr_realign.sv") + + for filein in file: + a = re.match(r".*\/(.*).sv", filein) + module = a.group(1) + fileout = "./04_cv32a65x_design/source/port_" + module + ".rst" + print("Input file " + filein) + print("Output file " + fileout) + ports = [] + with open(filein, "r", encoding="utf-8") as fin: + description = "none" + connection = "none" + for line in fin: + e = re.match(r"^ +(?:(in|out))put ([\S]*(?: [\S]*|)) ([\S]*)\n", line) + d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line) + if d: + description = d.group(1) + connection = d.group(2) + if e: + name = e.group(3) + name = name.split(",") + ports.append( + PortIO(name[0], e.group(1), e.group(2), description, connection) + ) + description = "none" + connection = "none" + + with open(fileout, "w", encoding="utf-8") as fout: + fout.write("..\n") + fout.write(" Copyright 2024 Thales DIS France SAS\n") + fout.write( + ' Licensed under the Solderpad Hardware License, Version 2.1 (the "License");\n' + ) + fout.write( + " you may not use this file except in compliance with the License.\n" + ) + fout.write(" SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n") + fout.write( + " You may obtain a copy of the License at https://solderpad.org/licenses/\n\n" + ) + fout.write(" Original Author: Jean-Roch COULON - Thales\n\n") + fout.write(f".. _CVA6_{module}:\n\n") + fout.write(f".. list-table:: {module} module IO ports\n") + fout.write(" :header-rows: 1\n") + fout.write("\n") + fout.write(" * - Signal\n") + fout.write(" - IO\n") + fout.write(" - Connection\n") + fout.write(" - Type\n") + fout.write(" - Description\n") + for i, port in enumerate(ports): + fout.write("\n") + fout.write(f" * - ``{port.name}``\n") + fout.write(f" - {port.direction}\n") + fout.write(f" - {port.connection}\n") + fout.write(f" - {port.data_type}\n") + fout.write(f" - {port.description}\n")