From 9c3960ebba75aa427fb3c0d156b0005bf37b4c7e Mon Sep 17 00:00:00 2001 From: takeshiho0531 Date: Fri, 9 Aug 2024 19:21:27 +0900 Subject: [PATCH] wip: unified hpdcache_req_o.addr_offset --- .../cva6_hpdcache_icache_if_adapter.sv | 35 +++++-------------- 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/core/cache_subsystem/cva6_hpdcache_icache_if_adapter.sv b/core/cache_subsystem/cva6_hpdcache_icache_if_adapter.sv index 21e0ae59a7..64d979745c 100644 --- a/core/cache_subsystem/cva6_hpdcache_icache_if_adapter.sv +++ b/core/cache_subsystem/cva6_hpdcache_icache_if_adapter.sv @@ -95,25 +95,9 @@ module cva6_hpdcache_icache_if_adapter } ); - - logic [CVA6Cfg.VLEN-1:0] vaddr_d, vaddr_q; - assign vaddr_d = (dreq_o.ready & dreq_i.req) ? dreq_i.vaddr : vaddr_q; - - - - always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs - if (!rst_ni) begin - vaddr_q <= '0; - end else begin - vaddr_q <= vaddr_d; - end - end - // Request forwarding assign hpdcache_req_valid_o = dreq_i.req, - hpdcache_req_o.addr_offset = hpdcache_req_is_uncacheable ?{ - vaddr_d[CVA6Cfg.ICACHE_INDEX_WIDTH-1:3], 3'b0 - }:{ vaddr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH], {ICACHE_OFFSET_WIDTH{1'b0}}}, + hpdcache_req_o.addr_offset = dreq_i.vaddr[CVA6Cfg.ICACHE_INDEX_WIDTH-1:0], hpdcache_req_o.wdata = '0, hpdcache_req_o.op = hpdcache_pkg::HPDCACHE_REQ_LOAD, hpdcache_req_o.be = fetch_obi_req_i.a.be, @@ -135,7 +119,7 @@ module cva6_hpdcache_icache_if_adapter // dreq_o.invalid_data = hpdcache_req_ready_i; // need this? (valid or killed) logic obi_gnt; // TODO, need to fix - always_ff @(posedge clk_i or negedge rst_ni) begin : obi_gnt_gen + always_ff @(posedge clk_i or negedge rst_ni) begin : obi_gnt_gen // TODO if (!rst_ni) begin obi_gnt <= '0; end else begin @@ -143,17 +127,17 @@ module cva6_hpdcache_icache_if_adapter end end - logic [ICACHE_OFFSET_WIDTH-1:0] cl_offset_d, cl_offset_q; + logic [ICACHE_OFFSET_WIDTH-1:0] which_half_d, which_half_q; - assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? (dreq_i.vaddr >> CVA6Cfg.FETCH_ALIGN_BITS) << CVA6Cfg.FETCH_ALIGN_BITS : - ( hpdcache_req_is_uncacheable & fetch_obi_req_i.req ) ? {{ICACHE_OFFSET_WIDTH-1{1'b0}}, cl_offset_q[2]} <<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case - cl_offset_q; + assign which_half_d = ( dreq_o.ready & dreq_i.req) ? (dreq_i.vaddr >> CVA6Cfg.FETCH_ALIGN_BITS) << CVA6Cfg.FETCH_ALIGN_BITS : + ( hpdcache_req_is_uncacheable & fetch_obi_req_i.req ) ? {{ICACHE_OFFSET_WIDTH-1{1'b0}}, which_half_q[2]} <<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case + which_half_q; always_ff @(posedge clk_i or negedge rst_ni) begin : gen_offset if (!rst_ni) begin - cl_offset_q <= '0; + which_half_q <= '0; end else begin - cl_offset_q <= cl_offset_d; + which_half_q <= which_half_d; end end @@ -165,9 +149,8 @@ module cva6_hpdcache_icache_if_adapter fetch_obi_rsp_o.r.r_optional.exokay = '0, // need this? fetch_obi_rsp_o.r.r_optional.rchk = '0, // need this? fetch_obi_rsp_o.r.err = hpdcache_rsp_i.error, // need this? - // fetch_obi_rsp_o.r.rdata = hpdcache_rsp_i.rdata[0][{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH], // data_d = mem_rtrn_i.data[{cl_offset_q, 3'b0}+:CVA6Cfg.FETCH_WIDTH]; fetch_obi_rsp_o.r.rdata = hpdcache_rsp_i.rdata[0][{ - cl_offset_q, 3'b0 + which_half_q, 3'b0 }+:CVA6Cfg.FETCH_WIDTH], fetch_obi_rsp_o.r.r_optional.ruser = '0; // TODO // }}}