diff --git a/core/mmu_unify/cva6_mmu.sv b/core/mmu_unify/cva6_mmu.sv
index d7b94d6aed..f712df6234 100644
--- a/core/mmu_unify/cva6_mmu.sv
+++ b/core/mmu_unify/cva6_mmu.sv
@@ -361,45 +361,45 @@ module cva6_mmu
 
   endgenerate
 
-    // The instruction interface is a simple request response interface
-    always_comb begin : instr_interface
-        // MMU disabled: just pass through
-        icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
-        // icache_areq_o.fetch_paddr  = icache_areq_i.fetch_vaddr[riscv::PLEN-1:0]; // play through in case we disabled address translation
-        // // two potential exception sources:
-        // 1. HPTW threw an exception -> signal with a page fault exception
-        // 2. We got an access error because of insufficient permissions -> throw an access exception
-        icache_areq_o.fetch_exception = '0;
-        // Check whether we are allowed to access this memory region from a fetch perspective
-        iaccess_err[0]   = icache_areq_i.fetch_req && (enable_translation_i[0] || HYP_EXT==0) && (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content[0].u)
+  // The instruction interface is a simple request response interface
+  always_comb begin : instr_interface
+    // MMU disabled: just pass through
+    icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
+    // icache_areq_o.fetch_paddr  = icache_areq_i.fetch_vaddr[riscv::PLEN-1:0]; // play through in case we disabled address translation
+    // // two potential exception sources:
+    // 1. HPTW threw an exception -> signal with a page fault exception
+    // 2. We got an access error because of insufficient permissions -> throw an access exception
+    icache_areq_o.fetch_exception = '0;
+    // Check whether we are allowed to access this memory region from a fetch perspective
+    iaccess_err[0]   = icache_areq_i.fetch_req && (enable_translation_i[0] || HYP_EXT==0) && (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content[0].u)
                                                         || ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content[0].u));
 
-        if (HYP_EXT == 1)
-        iaccess_err[HYP_EXT] = icache_areq_i.fetch_req && enable_translation_i[HYP_EXT] && !itlb_content[HYP_EXT].u;
-        // MMU enabled: address from TLB, request delayed until hit. Error when TLB
-        // hit and no access right or TLB hit and translated address not valid (e.g.
-        // AXI decode error), or when PTW performs walk due to ITLB miss and raises
-        // an error.
-        if ((|enable_translation_i[HYP_EXT:0])) begin
-        // we work with SV39 or SV32, so if VM is enabled, check that all bits [riscv::VLEN-1:riscv::SV-1] are equal
-            if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b0)) begin
-                if (HYP_EXT == 1) begin
-                icache_areq_o.fetch_exception = {
-                    riscv::INSTR_ACCESS_FAULT,
-                    {{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
-                    {riscv::GPLEN{1'b0}},
-                    {{riscv::XLEN{1'b0}}},
-                    enable_translation_i[HYP_EXT*2],
-                    1'b1
-                };
-                end else begin
-                icache_areq_o.fetch_exception = {
-                    riscv::INSTR_ACCESS_FAULT,
-                    {{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
-                    1'b1
-                };
-                end
-            end
+    if (HYP_EXT == 1)
+      iaccess_err[HYP_EXT] = icache_areq_i.fetch_req && enable_translation_i[HYP_EXT] && !itlb_content[HYP_EXT].u;
+    // MMU enabled: address from TLB, request delayed until hit. Error when TLB
+    // hit and no access right or TLB hit and translated address not valid (e.g.
+    // AXI decode error), or when PTW performs walk due to ITLB miss and raises
+    // an error.
+    if ((|enable_translation_i[HYP_EXT:0])) begin
+      // we work with SV39 or SV32, so if VM is enabled, check that all bits [riscv::VLEN-1:riscv::SV-1] are equal
+      if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[riscv::VLEN-1:riscv::SV-1]) == 1'b0)) begin
+        if (HYP_EXT == 1) begin
+          icache_areq_o.fetch_exception = {
+            riscv::INSTR_ACCESS_FAULT,
+            {{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
+            {riscv::GPLEN{1'b0}},
+            {{riscv::XLEN{1'b0}}},
+            enable_translation_i[HYP_EXT*2],
+            1'b1
+          };
+        end else begin
+          icache_areq_o.fetch_exception = {
+            riscv::INSTR_ACCESS_FAULT,
+            {{riscv::XLEN - riscv::VLEN{1'b0}}, icache_areq_i.fetch_vaddr},
+            1'b1
+          };
+        end
+      end
 
             icache_areq_o.fetch_valid = 1'b0;