diff --git a/docs/scripts/table_port_builder.py b/docs/scripts/table_port_builder.py
index 432783a80b..101aeb6e38 100755
--- a/docs/scripts/table_port_builder.py
+++ b/docs/scripts/table_port_builder.py
@@ -12,24 +12,23 @@
 import re
 
 
-class portIO:
+class PortIO:
     def __init__(
         self,
         name,
         direction,
-        type,
+        data_type,
         description,
         connection,
     ):
         self.name = name
         self.direction = direction
-        self.type = type
+        self.data_type = data_type
         self.description = description
         self.connection = connection
 
 
 if __name__ == "__main__":
-
     file = []
     file.append("../core/cva6.sv")
     file.append("../core/frontend/frontend.sv")
@@ -41,31 +40,31 @@ def __init__(
     file.append("../core/instr_realign.sv")
 
     for filein in file:
-        a = re.match(".*\/(.*).sv", filein)
+        a = re.match(r".*\/(.*).sv", filein)
         module = a.group(1)
         fileout = "./04_cv32a65x_design/source/port_" + module + ".rst"
         print("Input file " + filein)
         print("Output file " + fileout)
-        port = []
-        with open(filein, "r") as fin:
+        ports = []
+        with open(filein, "r", encoding="utf-8") as fin:
             description = "none"
             connection = "none"
-            for l1 in fin:
-                e = re.match("^ +(?:(in|out))put ([\S]*(?: [\S]*|)) ([\S]*)\n", l1)
-                d = re.match("^ +\/\/ (.*) - ([\S]*)\n", l1)
+            for line in fin:
+                e = re.match(r"^ +(?:(in|out))put ([\S]*(?: [\S]*|)) ([\S]*)\n", line)
+                d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line)
                 if d:
                     description = d.group(1)
                     connection = d.group(2)
                 if e:
                     name = e.group(3)
                     name = name.split(",")
-                    port.append(
-                        portIO(name[0], e.group(1), e.group(2), description, connection)
+                    ports.append(
+                        PortIO(name[0], e.group(1), e.group(2), description, connection)
                     )
                     description = "none"
                     connection = "none"
 
-        with open(fileout, "w") as fout:
+        with open(fileout, "w", encoding="utf-8") as fout:
             fout.write("..\n")
             fout.write("   Copyright 2024 Thales DIS France SAS\n")
             fout.write(
@@ -79,8 +78,8 @@ def __init__(
                 "   You may obtain a copy of the License at https://solderpad.org/licenses/\n\n"
             )
             fout.write("   Original Author: Jean-Roch COULON - Thales\n\n")
-            fout.write(".. _CVA6_%s:\n\n" % (module))
-            fout.write(".. list-table:: %s module IO ports\n" % (module))
+            fout.write(f".. _CVA6_{module}:\n\n")
+            fout.write(f".. list-table:: {module} module IO ports\n")
             fout.write("   :header-rows: 1\n")
             fout.write("\n")
             fout.write("   * - Signal\n")
@@ -88,10 +87,10 @@ def __init__(
             fout.write("     - Connection\n")
             fout.write("     - Type\n")
             fout.write("     - Description\n")
-            for i in range(len(port)):
+            for i, port in enumerate(ports):
                 fout.write("\n")
-                fout.write("   * - ``%s``\n" % (port[i].name))
-                fout.write("     - %s\n" % (port[i].direction))
-                fout.write("     - %s\n" % (port[i].connection))
-                fout.write("     - %s\n" % (port[i].type))
-                fout.write("     - %s\n" % (port[i].description))
+                fout.write(f"   * - ``{port.name}``\n")
+                fout.write(f"     - {port.direction}\n")
+                fout.write(f"     - {port.connection}\n")
+                fout.write(f"     - {port.data_type}\n")
+                fout.write(f"     - {port.description}\n")