diff --git a/core/commit_stage.sv b/core/commit_stage.sv
index 551b8a296f4..c8c6e74f52b 100644
--- a/core/commit_stage.sv
+++ b/core/commit_stage.sv
@@ -33,7 +33,7 @@ module commit_stage
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic single_step_i,
     // The instruction we want to commit - ISSUE_STAGE
-    input  scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
+    input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     // Acknowledge that we are indeed committing - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o,
     // Register file write address - ID_STAGE