diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv
index e6d6a9484f..da1ebe00eb 100644
--- a/core/include/riscv_pkg.sv
+++ b/core/include/riscv_pkg.sv
@@ -39,9 +39,9 @@ package riscv;
   // Warning: VLEN must be superior or equal to PLEN
   localparam VLEN = (XLEN == 32) ? 32 : 64;  // virtual address length
   localparam PLEN = (XLEN == 32) ? 34 : 56;  // physical address length
-  localparam GPLEN = (XLEN == 32) ? 34 : 41; 
+  localparam GPLEN = (XLEN == 32) ? 34 : 41;
   localparam GPPNW = (XLEN == 32) ? 22 : 29;
-  localparam GPPN2 = (XLEN == 32) ? riscv::VLEN-33 : 10;
+  localparam GPPN2 = (XLEN == 32) ? riscv::VLEN - 33 : 10;
   localparam IS_XLEN32 = (XLEN == 32) ? 1'b1 : 1'b0;
   localparam IS_XLEN64 = (XLEN == 32) ? 1'b0 : 1'b1;
   localparam ModeW = (XLEN == 32) ? 1 : 4;
@@ -368,12 +368,12 @@ package riscv;
   localparam logic [XLEN-1:0] S_EXT_INTERRUPT = (1 << (XLEN - 1)) | XLEN'(IRQ_S_EXT);
   localparam logic [XLEN-1:0] M_EXT_INTERRUPT = (1 << (XLEN - 1)) | XLEN'(IRQ_M_EXT);
 
-    // ----------------------
-    // PseudoInstructions Codes
-    // ----------------------
-  localparam logic [XLEN-1:0] READ_32_PSEUDOINSTRUCTION  = 32'h00002000;
+  // ----------------------
+  // PseudoInstructions Codes
+  // ----------------------
+  localparam logic [XLEN-1:0] READ_32_PSEUDOINSTRUCTION = 32'h00002000;
   localparam logic [XLEN-1:0] WRITE_32_PSEUDOINSTRUCTION = 32'h00002020;
-  localparam logic [XLEN-1:0] READ_64_PSEUDOINSTRUCTION  = 64'h00003000;
+  localparam logic [XLEN-1:0] READ_64_PSEUDOINSTRUCTION = 64'h00003000;
   localparam logic [XLEN-1:0] WRITE_64_PSEUDOINSTRUCTION = 64'h00003020;
 
   // -----
diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv
index 7db44be9a1..5abed4452e 100644
--- a/core/load_store_unit.sv
+++ b/core/load_store_unit.sv
@@ -140,7 +140,6 @@ module load_store_unit
   // -------------------
   // MMU e.g.: TLBs/PTW
   // -------------------
- 
   if (MMU_PRESENT) begin : gen_mmu
 
     localparam HYP_EXT = 0;  //CVA6Cfg.CVA6ConfigHExtEn
@@ -166,38 +165,38 @@ module load_store_unit
         .icache_areq_i         (icache_areq_i),
         .icache_areq_o         (icache_areq_o),
         // misaligned bypass
-        .misaligned_ex_i        ( misaligned_exception   ),
-        .lsu_req_i              ( translation_req        ),
-        .lsu_vaddr_i            ( mmu_vaddr              ),
-        .lsu_tinst_i            ( 0              ),
-        .lsu_is_store_i         ( st_translation_req     ),
-        .csr_hs_ld_st_inst_o    (     ),
-        .lsu_dtlb_hit_o         ( dtlb_hit               ), // send in the same cycle as the request
-        .lsu_dtlb_ppn_o         ( dtlb_ppn               ), // send in the same cycle as the request
-        
-        .lsu_valid_o            ( translation_valid      ),
-        .lsu_paddr_o            ( mmu_paddr              ),
-        .lsu_exception_o        ( mmu_exception          ),
-        
-        .priv_lvl_i             (priv_lvl_i              ),
-        .ld_st_priv_lvl_i       (ld_st_priv_lvl_i        ),
-
-        .sum_i                  ({sum_i}),
-        .mxr_i                  ({mxr_i}),
-        .hlvx_inst_i            ( 0          ),
-        .hs_ld_st_inst_i        ( 0      ),    
-        
-        .satp_ppn_i             ({satp_ppn_i}),
-        .asid_i                 ({asid_i}),
-        .asid_to_be_flushed_i   ({asid_to_be_flushed_i}),
-        .vaddr_to_be_flushed_i  ({vaddr_to_be_flushed_i}),
-        .flush_tlb_i            ({flush_tlb_i}),
-
-        .itlb_miss_o            (itlb_miss_o),
-        .dtlb_miss_o            (dtlb_miss_o),
-
-        .req_port_i             ( dcache_req_ports_i [0] ),
-        .req_port_o             ( dcache_req_ports_o [0] ),
+        .misaligned_ex_i       (misaligned_exception),
+        .lsu_req_i             (translation_req),
+        .lsu_vaddr_i           (mmu_vaddr),
+        .lsu_tinst_i           (0),
+        .lsu_is_store_i        (st_translation_req),
+        .csr_hs_ld_st_inst_o   (),
+        .lsu_dtlb_hit_o        (dtlb_hit),                  // send in the same cycle as the request
+        .lsu_dtlb_ppn_o        (dtlb_ppn),                  // send in the same cycle as the request
+
+        .lsu_valid_o    (translation_valid),
+        .lsu_paddr_o    (mmu_paddr),
+        .lsu_exception_o(mmu_exception),
+
+        .priv_lvl_i      (priv_lvl_i),
+        .ld_st_priv_lvl_i(ld_st_priv_lvl_i),
+
+        .sum_i          ({sum_i}),
+        .mxr_i          ({mxr_i}),
+        .hlvx_inst_i    (0),
+        .hs_ld_st_inst_i(0),
+
+        .satp_ppn_i           ({satp_ppn_i}),
+        .asid_i               ({asid_i}),
+        .asid_to_be_flushed_i ({asid_to_be_flushed_i}),
+        .vaddr_to_be_flushed_i({vaddr_to_be_flushed_i}),
+        .flush_tlb_i          ({flush_tlb_i}),
+
+        .itlb_miss_o(itlb_miss_o),
+        .dtlb_miss_o(dtlb_miss_o),
+
+        .req_port_i(dcache_req_ports_i[0]),
+        .req_port_o(dcache_req_ports_o[0]),
         .pmpcfg_i,
         .pmpaddr_i
     );