From aad93781e5bc4236b15ac6fe0a823934754b24fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Domenic=20W=C3=BCthrich?= Date: Wed, 16 Aug 2023 14:40:09 +0000 Subject: [PATCH 1/4] [wt_cache] Add third read port --- core/cache_subsystem/wt_cache_subsystem.sv | 12 +-- core/cache_subsystem/wt_dcache.sv | 88 +++++++++++----------- core/cache_subsystem/wt_dcache_missunit.sv | 2 +- 3 files changed, 51 insertions(+), 51 deletions(-) diff --git a/core/cache_subsystem/wt_cache_subsystem.sv b/core/cache_subsystem/wt_cache_subsystem.sv index efecfdcf3c..9182a4a511 100644 --- a/core/cache_subsystem/wt_cache_subsystem.sv +++ b/core/cache_subsystem/wt_cache_subsystem.sv @@ -22,7 +22,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions - parameter int unsigned NumPorts = 3, + parameter int unsigned NumPorts = 4, parameter type noc_req_t = logic, parameter type noc_resp_t = logic ) ( @@ -50,8 +50,8 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( input amo_req_t dcache_amo_req_i, output amo_resp_t dcache_amo_resp_o, // Request ports - input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU - output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU // writebuffer status output logic wbuffer_empty_o, output logic wbuffer_not_ni_o, @@ -193,13 +193,13 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #( for (genvar j=0; j dcache_req_ports_i[2].data_be[j] |-> (|dcache_req_ports_i[2].data_wdata[j*8+:8] !== 1'hX)) + @(posedge clk_i) disable iff (!rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> dcache_req_ports_i[NumPorts-1].data_be[j] |-> (|dcache_req_ports_i[NumPorts-1].data_wdata[j*8+:8] !== 1'hX)) else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X, databe=%016X", - {dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata, dcache_req_ports_i[2].data_be & dcache_req_ports_i[2].data_wdata); + {dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata, dcache_req_ports_i[NumPorts-1].data_be & dcache_req_ports_i[NumPorts-1].data_wdata); end - for (genvar j=0; j<2; j++) begin : gen_assertion + for (genvar j=0; j (|dcache_req_ports_o[j].data_rdata) !== 1'hX) else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X", diff --git a/core/cache_subsystem/wt_dcache.sv b/core/cache_subsystem/wt_dcache.sv index bb192a41c9..a76e5ad5fe 100644 --- a/core/cache_subsystem/wt_dcache.sv +++ b/core/cache_subsystem/wt_dcache.sv @@ -15,7 +15,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned NumPorts = 3, // number of miss ports + parameter int unsigned NumPorts = 4, // number of miss ports // ID to be used for read and AMO transactions. // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1, @@ -38,8 +38,8 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( output amo_resp_t amo_resp_o, // Request ports - input dcache_req_i_t [2:0] req_ports_i, - output dcache_req_o_t [2:0] req_ports_o, + input dcache_req_i_t [NumPorts-1:0] req_ports_i, + output dcache_req_o_t [NumPorts-1:0] req_ports_o, output logic [NumPorts-1:0][DCACHE_SET_ASSOC-1:0] miss_vld_bits_o, @@ -217,60 +217,60 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #( /////////////////////////////////////////////////////// // set read port to low priority - assign rd_prio[2] = 1'b0; + assign rd_prio[NumPorts-1] = 1'b0; wt_dcache_wbuffer #( .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ) ) i_wt_dcache_wbuffer ( - .clk_i ( clk_i ), - .rst_ni ( rst_ni ), - .empty_o ( wbuffer_empty_o ), - .not_ni_o ( wbuffer_not_ni_o ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .empty_o ( wbuffer_empty_o ), + .not_ni_o ( wbuffer_not_ni_o ), // TODO: fix this - .cache_en_i ( cache_en ), + .cache_en_i ( cache_en ), // .cache_en_i ( '0 ), // request ports from core (store unit) - .req_port_i ( req_ports_i [2] ), - .req_port_o ( req_ports_o [2] ), + .req_port_i ( req_ports_i [NumPorts-1] ), + .req_port_o ( req_ports_o [NumPorts-1] ), // miss unit interface - .miss_req_o ( miss_req [2] ), - .miss_ack_i ( miss_ack [2] ), - .miss_we_o ( miss_we [2] ), - .miss_wdata_o ( miss_wdata [2] ), - .miss_wuser_o ( miss_wuser [2] ), - .miss_vld_bits_o ( miss_vld_bits_o[2] ), - .miss_paddr_o ( miss_paddr [2] ), - .miss_nc_o ( miss_nc [2] ), - .miss_size_o ( miss_size [2] ), - .miss_id_o ( miss_id [2] ), - .miss_rtrn_vld_i ( miss_rtrn_vld [2] ), - .miss_rtrn_id_i ( miss_rtrn_id ), + .miss_req_o ( miss_req [NumPorts-1] ), + .miss_ack_i ( miss_ack [NumPorts-1] ), + .miss_we_o ( miss_we [NumPorts-1] ), + .miss_wdata_o ( miss_wdata [NumPorts-1] ), + .miss_wuser_o ( miss_wuser [NumPorts-1] ), + .miss_vld_bits_o ( miss_vld_bits_o[NumPorts-1] ), + .miss_paddr_o ( miss_paddr [NumPorts-1] ), + .miss_nc_o ( miss_nc [NumPorts-1] ), + .miss_size_o ( miss_size [NumPorts-1] ), + .miss_id_o ( miss_id [NumPorts-1] ), + .miss_rtrn_vld_i ( miss_rtrn_vld [NumPorts-1] ), + .miss_rtrn_id_i ( miss_rtrn_id ), // cache read interface - .rd_tag_o ( rd_tag [2] ), - .rd_idx_o ( rd_idx [2] ), - .rd_off_o ( rd_off [2] ), - .rd_req_o ( rd_req [2] ), - .rd_tag_only_o ( rd_tag_only [2] ), - .rd_ack_i ( rd_ack [2] ), - .rd_data_i ( rd_data ), - .rd_vld_bits_i ( rd_vld_bits ), - .rd_hit_oh_i ( rd_hit_oh ), + .rd_tag_o ( rd_tag [NumPorts-1] ), + .rd_idx_o ( rd_idx [NumPorts-1] ), + .rd_off_o ( rd_off [NumPorts-1] ), + .rd_req_o ( rd_req [NumPorts-1] ), + .rd_tag_only_o ( rd_tag_only [NumPorts-1] ), + .rd_ack_i ( rd_ack [NumPorts-1] ), + .rd_data_i ( rd_data ), + .rd_vld_bits_i ( rd_vld_bits ), + .rd_hit_oh_i ( rd_hit_oh ), // incoming invalidations/cache refills - .wr_cl_vld_i ( wr_cl_vld ), - .wr_cl_idx_i ( wr_cl_idx ), + .wr_cl_vld_i ( wr_cl_vld ), + .wr_cl_idx_i ( wr_cl_idx ), // single word write interface - .wr_req_o ( wr_req ), - .wr_ack_i ( wr_ack ), - .wr_idx_o ( wr_idx ), - .wr_off_o ( wr_off ), - .wr_data_o ( wr_data ), - .wr_user_o ( wr_user ), - .wr_data_be_o ( wr_data_be ), + .wr_req_o ( wr_req ), + .wr_ack_i ( wr_ack ), + .wr_idx_o ( wr_idx ), + .wr_off_o ( wr_off ), + .wr_data_o ( wr_data ), + .wr_user_o ( wr_user ), + .wr_data_be_o ( wr_data_be ), // write buffer forwarding - .wbuffer_data_o ( wbuffer_data ), - .tx_paddr_o ( tx_paddr ), - .tx_vld_o ( tx_vld ) + .wbuffer_data_o ( wbuffer_data ), + .tx_paddr_o ( tx_paddr ), + .tx_vld_o ( tx_vld ) ); /////////////////////////////////////////////////////// diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv index 23b9df6c14..9d63224f91 100644 --- a/core/cache_subsystem/wt_dcache_missunit.sv +++ b/core/cache_subsystem/wt_dcache_missunit.sv @@ -18,7 +18,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs - parameter int unsigned NumPorts = 3 // number of miss ports + parameter int unsigned NumPorts = 4 // number of miss ports ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low From 570c52992f29d48f5a6883e5114a6ff57bc57c81 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Domenic=20W=C3=BCthrich?= Date: Wed, 16 Aug 2023 14:44:07 +0000 Subject: [PATCH 2/4] [std_cache_subsystem] Add fourth dcache request port --- core/cache_subsystem/miss_handler.sv | 6 +-- core/cache_subsystem/std_cache_subsystem.sv | 49 +++++++++--------- core/cache_subsystem/std_nbdcache.sv | 56 +++++++++++---------- 3 files changed, 58 insertions(+), 53 deletions(-) diff --git a/core/cache_subsystem/miss_handler.sv b/core/cache_subsystem/miss_handler.sv index 7fe7cd6b1d..c8f220d0e1 100644 --- a/core/cache_subsystem/miss_handler.sv +++ b/core/cache_subsystem/miss_handler.sv @@ -18,7 +18,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter int unsigned NR_PORTS = 3, + parameter int unsigned NR_PORTS = 4, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic )( @@ -524,7 +524,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( bypass_ports_req[id].req = miss_req_valid[id] & miss_req_bypass[id]; bypass_ports_req[id].reqtype = ariane_pkg::SINGLE_REQ; bypass_ports_req[id].amo = AMO_NONE; - bypass_ports_req[id].id = {2'b10, id}; + bypass_ports_req[id].id = 4'b1000 | 4'(id); bypass_ports_req[id].addr = miss_req_addr[id]; bypass_ports_req[id].wdata = miss_req_wdata[id]; bypass_ports_req[id].we = miss_req_we[id]; @@ -619,7 +619,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #( .wdata_i ( req_fsm_miss_wdata ), .be_i ( req_fsm_miss_be ), .size_i ( req_fsm_miss_size ), - .id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b1100} ), + .id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b0111} ), .valid_o ( valid_miss_fsm ), .rdata_o ( data_miss_fsm ), .id_o ( ), diff --git a/core/cache_subsystem/std_cache_subsystem.sv b/core/cache_subsystem/std_cache_subsystem.sv index e404e920ca..47f7521626 100644 --- a/core/cache_subsystem/std_cache_subsystem.sv +++ b/core/cache_subsystem/std_cache_subsystem.sv @@ -18,6 +18,7 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions + parameter int unsigned NumPorts = 4, parameter type axi_ar_chan_t = logic, parameter type axi_aw_chan_t = logic, parameter type axi_w_chan_t = logic, @@ -48,8 +49,8 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( output logic dcache_miss_o, // we missed on a ld/st output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system // Request ports - input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU - output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU + input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU + output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU // memory side output axi_req_t axi_req_o, input axi_rsp_t axi_resp_i @@ -87,10 +88,12 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( // decreasing priority // Port 0: PTW // Port 1: Load Unit - // Port 2: Store Unit + // Port 2: Accelerator + // Port 3: Store Unit std_nbdcache #( .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ), + .NumPorts ( NumPorts ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_nbdcache ( @@ -151,10 +154,10 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( // to forward the correct write data. always_comb begin w_select = 0; - unique case (axi_req_o.aw.id) - 4'b1100: w_select = 2; // dcache - 4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass - default: w_select = 0; // icache + unique casez (axi_req_o.aw.id) + 4'b0111: w_select = 2; // dcache + 4'b1???: w_select = 1; // bypass + default: w_select = 0; // icache endcase end @@ -199,9 +202,9 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( ); // Route responses based on ID - // 0000 -> I$ - // 10[00|10|01|11] -> Bypass - // 1100 -> D$ + // 0000 -> I$ + // 0111 -> D$ + // 1??? -> Bypass // R Channel assign axi_resp_icache.r = axi_resp_i.r; assign axi_resp_bypass.r = axi_resp_i.r; @@ -211,11 +214,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( always_comb begin r_select = 0; - unique case (axi_resp_i.r.id) - 4'b1100: r_select = 0; // dcache - 4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass - 4'b0000: r_select = 2; // icache - default: r_select = 0; + unique casez (axi_resp_i.r.id) + 4'b0111: r_select = 0; // dcache + 4'b1???: r_select = 1; // bypass + 4'b0000: r_select = 2; // icache + default: r_select = 0; endcase end @@ -238,11 +241,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( always_comb begin b_select = 0; - unique case (axi_resp_i.b.id) - 4'b1100: b_select = 0; // dcache - 4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass - 4'b0000: b_select = 2; // icache - default: b_select = 0; + unique casez (axi_resp_i.b.id) + 4'b0111: b_select = 0; // dcache + 4'b1???: b_select = 1; // bypass + 4'b0000: b_select = 2; // icache + default: b_select = 0; endcase end @@ -269,11 +272,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #( icache_dreq_o.vaddr, icache_dreq_o.data); a_invalid_write_data: assert property ( - @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX) + @(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> |dcache_req_ports_i[NumPorts-1].data_be |-> (|dcache_req_ports_i[NumPorts-1].data_wdata) !== 1'hX) else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X", - {dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata); + {dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata); generate - for(genvar j=0; j<2; j++) begin + for(genvar j=0; j (|dcache_req_ports_o[j].data_rdata) !== 1'hX) else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X", diff --git a/core/cache_subsystem/std_nbdcache.sv b/core/cache_subsystem/std_nbdcache.sv index a2ab971b1f..a48bc9b31f 100644 --- a/core/cache_subsystem/std_nbdcache.sv +++ b/core/cache_subsystem/std_nbdcache.sv @@ -16,6 +16,7 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions + parameter int unsigned NumPorts = 4, parameter type axi_req_t = logic, parameter type axi_rsp_t = logic )( @@ -30,8 +31,8 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #( input amo_req_t amo_req_i, output amo_resp_t amo_resp_o, // Request ports - input dcache_req_i_t [2:0] req_ports_i, // request ports - output dcache_req_o_t [2:0] req_ports_o, // request ports + input dcache_req_i_t [NumPorts-1:0] req_ports_i, // request ports + output dcache_req_o_t [NumPorts-1:0] req_ports_o, // request ports // Cache AXI refill port output axi_req_t axi_data_o, input axi_rsp_t axi_data_i, @@ -47,34 +48,35 @@ import std_cache_pkg::*; // 1. Miss handler // 2. PTW // 3. Load Unit - // 4. Store unit - logic [3:0][DCACHE_SET_ASSOC-1:0] req; - logic [3:0][DCACHE_INDEX_WIDTH-1:0]addr; - logic [3:0] gnt; - cache_line_t [DCACHE_SET_ASSOC-1:0] rdata; - logic [3:0][DCACHE_TAG_WIDTH-1:0] tag; + // 4. Accelerator + // 5. Store unit + logic [NumPorts:0][DCACHE_SET_ASSOC-1:0] req; + logic [NumPorts:0][DCACHE_INDEX_WIDTH-1:0]addr; + logic [NumPorts:0] gnt; + cache_line_t [DCACHE_SET_ASSOC-1:0] rdata; + logic [NumPorts:0][DCACHE_TAG_WIDTH-1:0] tag; - cache_line_t [3:0] wdata; - logic [3:0] we; - cl_be_t [3:0] be; - logic [DCACHE_SET_ASSOC-1:0] hit_way; + cache_line_t [NumPorts:0] wdata; + logic [NumPorts:0] we; + cl_be_t [NumPorts:0] be; + logic [DCACHE_SET_ASSOC-1:0] hit_way; // ------------------------------- // Controller <-> Miss unit // ------------------------------- - logic [2:0] busy; - logic [2:0][55:0] mshr_addr; - logic [2:0] mshr_addr_matches; - logic [2:0] mshr_index_matches; - logic [63:0] critical_word; - logic critical_word_valid; + logic [NumPorts-1:0] busy; + logic [NumPorts-1:0][55:0] mshr_addr; + logic [NumPorts-1:0] mshr_addr_matches; + logic [NumPorts-1:0] mshr_index_matches; + logic [63:0] critical_word; + logic critical_word_valid; - logic [2:0][$bits(miss_req_t)-1:0] miss_req; - logic [2:0] miss_gnt; - logic [2:0] active_serving; + logic [NumPorts-1:0][$bits(miss_req_t)-1:0] miss_req; + logic [NumPorts-1:0] miss_gnt; + logic [NumPorts-1:0] active_serving; - logic [2:0] bypass_gnt; - logic [2:0] bypass_valid; - logic [2:0][63:0] bypass_data; + logic [NumPorts-1:0] bypass_gnt; + logic [NumPorts-1:0] bypass_valid; + logic [NumPorts-1:0][63:0] bypass_data; // ------------------------------- // Arbiter <-> Datram, // ------------------------------- @@ -89,7 +91,7 @@ import std_cache_pkg::*; // Cache Controller // ------------------ generate - for (genvar i = 0; i < 3; i++) begin : master_ports + for (genvar i = 0; i < NumPorts; i++) begin : master_ports cache_ctrl #( .CVA6Cfg ( CVA6Cfg ), .ArianeCfg ( ArianeCfg ) @@ -132,7 +134,7 @@ import std_cache_pkg::*; // ------------------ miss_handler #( .CVA6Cfg ( CVA6Cfg ), - .NR_PORTS ( 3 ), + .NR_PORTS ( NumPorts ), .axi_req_t ( axi_req_t ), .axi_rsp_t ( axi_rsp_t ) ) i_miss_handler ( @@ -243,7 +245,7 @@ import std_cache_pkg::*; // ------------------------------------------------ tag_cmp #( .CVA6Cfg ( CVA6Cfg ), - .NR_PORTS ( 4 ), + .NR_PORTS ( NumPorts+1 ), .ADDR_WIDTH ( DCACHE_INDEX_WIDTH ), .DCACHE_SET_ASSOC ( DCACHE_SET_ASSOC ) ) i_tag_cmp ( From 7092e4a81e6d786262f2e76d082d971856e0f1b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Domenic=20W=C3=BCthrich?= Date: Fri, 18 Aug 2023 12:49:46 +0000 Subject: [PATCH 3/4] [cva6] Connect acc dipatcher d$ ports to cache subsystem --- core/cva6.sv | 43 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/core/cva6.sv b/core/cva6.sv index cfa1afbcc1..270211554d 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -205,7 +205,7 @@ module cva6 import ariane_pkg::*; #( logic eret; logic [CVA6ExtendCfg.NrCommitPorts-1:0] commit_ack; - localparam NumPorts = 3; + localparam NumPorts = 4; cvxif_pkg::cvxif_req_t cvxif_req; cvxif_pkg::cvxif_resp_t cvxif_resp; @@ -408,6 +408,8 @@ module cva6 import ariane_pkg::*; #( // ---------------- dcache_req_i_t [2:0] dcache_req_ports_ex_cache; dcache_req_o_t [2:0] dcache_req_ports_cache_ex; + dcache_req_i_t [1:0] dcache_req_ports_acc_cache; + dcache_req_o_t [1:0] dcache_req_ports_cache_acc; logic dcache_commit_wbuffer_empty; logic dcache_commit_wbuffer_not_ni; @@ -888,6 +890,31 @@ module cva6 import ariane_pkg::*; #( // Cache Subsystem // ------------------- + // Acc dispatcher and store buffer share a dcache request port. + // Store buffer always has priority access over acc dipsatcher. + dcache_req_i_t [NumPorts-1:0] dcache_req_to_cache; + dcache_req_o_t [NumPorts-1:0] dcache_req_from_cache; + + // D$ request + assign dcache_req_to_cache[0] = dcache_req_ports_ex_cache[0]; + assign dcache_req_to_cache[1] = dcache_req_ports_ex_cache[1]; + assign dcache_req_to_cache[2] = dcache_req_ports_acc_cache[0]; + assign dcache_req_to_cache[3] = dcache_req_ports_ex_cache[2].data_req ? dcache_req_ports_ex_cache [2] : + dcache_req_ports_acc_cache[1]; + + // D$ response + assign dcache_req_ports_cache_ex [0] = dcache_req_from_cache[0]; + assign dcache_req_ports_cache_ex [1] = dcache_req_from_cache[1]; + assign dcache_req_ports_cache_acc[0] = dcache_req_from_cache[2]; + always_comb begin : gen_dcache_req_store_data_gnt + dcache_req_ports_cache_ex [2] = dcache_req_from_cache[3]; + dcache_req_ports_cache_acc[1] = dcache_req_from_cache[3]; + + // Set gnt signal + dcache_req_ports_cache_ex [2].data_gnt &= dcache_req_ports_ex_cache[2].data_req; + dcache_req_ports_cache_acc[1].data_gnt &= !dcache_req_ports_ex_cache[2].data_req; + end + if (DCACHE_TYPE == int'(cva6_config_pkg::WT)) begin : gen_cache_wt // this is a cache subsystem that is compatible with OpenPiton wt_cache_subsystem #( @@ -918,8 +945,8 @@ module cva6 import ariane_pkg::*; #( // from PTW, Load Unit and Store Unit .dcache_miss_o ( dcache_miss_cache_perf ), .miss_vld_bits_o ( miss_vld_bits ), - .dcache_req_ports_i ( dcache_req_ports_ex_cache ), - .dcache_req_ports_o ( dcache_req_ports_cache_ex ), + .dcache_req_ports_i ( dcache_req_to_cache ), + .dcache_req_ports_o ( dcache_req_from_cache ), // write buffer status .wbuffer_empty_o ( dcache_commit_wbuffer_empty ), .wbuffer_not_ni_o ( dcache_commit_wbuffer_not_ni ), @@ -938,6 +965,7 @@ module cva6 import ariane_pkg::*; #( // deprecated .CVA6Cfg ( CVA6ExtendCfg ), .ArianeCfg ( ArianeCfg ), + .NumPorts ( NumPorts ), .axi_ar_chan_t ( axi_ar_chan_t ), .axi_aw_chan_t ( axi_aw_chan_t ), .axi_w_chan_t ( axi_w_chan_t ), @@ -967,8 +995,8 @@ module cva6 import ariane_pkg::*; #( // this is statically set to 1 as the std_cache does not have a wbuffer .wbuffer_empty_o ( dcache_commit_wbuffer_empty ), // from PTW, Load Unit and Store Unit - .dcache_req_ports_i ( dcache_req_ports_ex_cache ), - .dcache_req_ports_o ( dcache_req_ports_cache_ex ), + .dcache_req_ports_i ( dcache_req_to_cache ), + .dcache_req_ports_o ( dcache_req_from_cache ), // memory side .axi_req_o ( noc_req_o ), .axi_resp_i ( noc_resp_i ) @@ -1015,6 +1043,8 @@ module cva6 import ariane_pkg::*; #( .acc_no_st_pending_i ( no_st_pending_commit ), .dcache_req_ports_i ( dcache_req_ports_ex_cache ), .ctrl_halt_o ( halt_acc_ctrl ), + .acc_dcache_req_ports_o ( dcache_req_ports_acc_cache ), + .acc_dcache_req_ports_i ( dcache_req_ports_cache_acc ), .inval_ready_i ( inval_ready ), .inval_valid_o ( inval_valid ), .inval_addr_o ( inval_addr ), @@ -1035,6 +1065,9 @@ module cva6 import ariane_pkg::*; #( assign stall_st_pending_ex = '0; assign flush_acc = '0; + // D$ connection is unused + assign dcache_req_ports_acc_cache = '0; + // No invalidation interface assign inval_valid = '0; assign inval_addr = '0; From d45fda617923ccef6847d36c92fdefe401c8e1fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Domenic=20W=C3=BCthrich?= Date: Fri, 18 Aug 2023 12:51:10 +0000 Subject: [PATCH 4/4] [acc_dipsatcher] Add dcache request ports --- core/acc_dispatcher.sv | 3 +++ 1 file changed, 3 insertions(+) diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv index 6de6dd65ac..4c0aefd027 100644 --- a/core/acc_dispatcher.sv +++ b/core/acc_dispatcher.sv @@ -54,6 +54,8 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #( input logic flush_ex_i, output logic flush_pipeline_o, // Interface with cache subsystem + output dcache_req_i_t [1:0] acc_dcache_req_ports_o, + input dcache_req_o_t [1:0] acc_dcache_req_ports_i, input logic inval_ready_i, output logic inval_valid_o, output logic [63:0] inval_addr_o, @@ -412,5 +414,6 @@ module acc_dispatcher import ariane_pkg::*; import riscv::*; #( assign acc_stall_st_pending_o = 1'b0; assign flush_pipeline_o = 1'b0; + assign acc_dcache_req_ports_o = '0; endmodule : acc_dispatcher