From 7f5870bc2507b83dc134d6112498d6afd5c4a15f Mon Sep 17 00:00:00 2001 From: Jean-Roch Coulon Date: Wed, 7 Feb 2024 18:28:01 +0100 Subject: [PATCH] Fix Verible and co --- core/commit_stage.sv | 4 +- core/csr_regfile.sv | 114 +++++++++--------- core/ex_stage.sv | 2 +- core/include/cv32a65x_config_pkg.sv | 4 - core/issue_stage.sv | 2 +- docs/04_cv32a65x_design/source/port_bht.rst | 4 +- docs/04_cv32a65x_design/source/port_btb.rst | 4 +- .../source/port_commit_stage.rst | 22 ++-- .../source/port_csr_regfile.rst | 66 ++++++---- docs/04_cv32a65x_design/source/port_cva6.rst | 6 +- .../source/port_ex_stage.rst | 44 +++---- .../source/port_frontend.rst | 8 +- .../source/port_id_stage.rst | 6 +- .../source/port_instr_queue.rst | 16 +-- .../source/port_instr_realign.rst | 10 +- .../source/port_instr_scan.rst | 6 +- .../source/port_issue_stage.rst | 36 +++--- docs/04_cv32a65x_design/source/port_ras.rst | 2 +- docs/scripts/table_port_builder.py | 8 +- 19 files changed, 196 insertions(+), 168 deletions(-) diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 551b8a296f..d0dcc25be0 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -33,7 +33,7 @@ module commit_stage // TO_BE_COMPLETED - CSR_REGFILE input logic single_step_i, // The instruction we want to commit - ISSUE_STAGE - input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // Acknowledge that we are indeed committing - ISSUE_STAGE output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o, // Register file write address - ID_STAGE @@ -55,7 +55,7 @@ module commit_stage // Data to read from CSR - CSR_REGFILE input riscv::xlen_t csr_rdata_i, // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE - input exception_t csr_exception_i, + input exception_t csr_exception_i, // Write the fflags CSR - CSR_REGFILE output logic csr_write_fflags_o, // Commit the pending store - EX_STAGE diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 5b0bfe0575..8ddf8fd478 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -21,121 +21,121 @@ module csr_regfile parameter int unsigned MHPMCounterNum = 6 ) ( // Subsystem Clock - SUBSYSTEM - input logic clk_i, + input logic clk_i, // Asynchronous reset active low - SUBSYSTEM - input logic rst_ni, + input logic rst_ni, // Timer threw a interrupt - SUBSYSTEM - input logic time_irq_i, + input logic time_irq_i, // send a flush request out when a CSR with a side effect changes - CONTROLLER - output logic flush_o, + output logic flush_o, // halt requested - CONTROLLER - output logic halt_csr_o, + output logic halt_csr_o, // Instruction to be committed - ID_STAGE - input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE - input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM - input logic[riscv::VLEN-1:0] boot_addr_i, + input logic [ riscv::VLEN-1:0] boot_addr_i, // Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM - input logic[riscv::XLEN-1:0] hart_id_i, + input logic [ riscv::XLEN-1:0] hart_id_i, // we are taking an exception // We've got an exception from the commit stage, take it - COMMIT_STAGE - input exception_t ex_i, + input exception_t ex_i, // Operation to perform on the CSR file - COMMIT_STAGE - input fu_op csr_op_i, + input fu_op csr_op_i, // Address of the register to read/write - EX_STAGE - input logic [11:0] csr_addr_i, + input logic [ 11:0] csr_addr_i, // Write data in - COMMIT_STAGE - input logic [riscv::XLEN-1:0] csr_wdata_i, + input logic [ riscv::XLEN-1:0] csr_wdata_i, // Read data out - COMMIT_STAGE - output logic [riscv::XLEN-1:0] csr_rdata_o, + output logic [ riscv::XLEN-1:0] csr_rdata_o, // Mark the FP sate as dirty - COMMIT_STAGE - input logic dirty_fp_state_i, + input logic dirty_fp_state_i, // Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE - input logic csr_write_fflags_i, + input logic csr_write_fflags_i, // Mark the V state as dirty - ACC_DISPATCHER - input logic dirty_v_state_i, + input logic dirty_v_state_i, // PC of instruction accessing the CSR - COMMIT_STAGE - input logic [riscv::VLEN-1:0] pc_i, + input logic [ riscv::VLEN-1:0] pc_i, // attempts to access a CSR without appropriate privilege - COMMIT_STAGE - output exception_t csr_exception_o, + output exception_t csr_exception_o, // Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly - FRONTEND - output logic [riscv::VLEN-1:0] epc_o, + output logic [ riscv::VLEN-1:0] epc_o, // Return from exception, set the PC of epc_o - FRONTEND - output logic eret_o, + output logic eret_o, // Output base of exception vector, correct CSR is output (mtvec, stvec) - FRONTEND - output logic [riscv::VLEN-1:0] trap_vector_base_o, + output logic [ riscv::VLEN-1:0] trap_vector_base_o, // Current privilege level the CPU is in - EX_STAGE - output riscv::priv_lvl_t priv_lvl_o, + output riscv::priv_lvl_t priv_lvl_o, // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER - input logic [4:0] acc_fflags_ex_i, + input logic [ 4:0] acc_fflags_ex_i, // An FP exception from the accelerator occurred - ACC_DISPATCHER - input logic acc_fflags_ex_valid_i, + input logic acc_fflags_ex_valid_i, // Floating point extension status - ID_STAGE - output riscv::xs_t fs_o, + output riscv::xs_t fs_o, // Floating-Point Accured Exceptions - COMMIT_STAGE - output logic [4:0] fflags_o, + output logic [ 4:0] fflags_o, // Floating-Point Dynamic Rounding Mode - EX_STAGE - output logic [2:0] frm_o, + output logic [ 2:0] frm_o, // Floating-Point Precision Control - EX_STAGE - output logic [6:0] fprec_o, + output logic [ 6:0] fprec_o, // Vector extension status - ID_STAGE - output riscv::xs_t vs_o, + output riscv::xs_t vs_o, // interrupt management to id stage - ID_STAGE - output irq_ctrl_t irq_ctrl_o, + output irq_ctrl_t irq_ctrl_o, // enable VA translation - EX_STAGE - output logic en_translation_o, + output logic en_translation_o, // enable VA translation for load and stores - EX_STAGE - output logic en_ld_st_translation_o, + output logic en_ld_st_translation_o, // Privilege level at which load and stores should happen - EX_STAGE - output riscv::priv_lvl_t ld_st_priv_lvl_o, + output riscv::priv_lvl_t ld_st_priv_lvl_o, // TO_BE_COMPLETED - EX_STAGE - output logic sum_o, + output logic sum_o, // TO_BE_COMPLETED - EX_STAGE - output logic mxr_o, + output logic mxr_o, // TO_BE_COMPLETED - EX_STAGE - output logic [riscv::PPNW-1:0] satp_ppn_o, + output logic [ riscv::PPNW-1:0] satp_ppn_o, // TO_BE_COMPLETED - EX_STAGE - output logic [AsidWidth-1:0] asid_o, + output logic [ AsidWidth-1:0] asid_o, // external interrupt in - SUBSYSTEM - input logic [1:0] irq_i, + input logic [ 1:0] irq_i, // inter processor interrupt -> connected to machine mode sw - SUBSYSTEM - input logic ipi_i, + input logic ipi_i, // debug request in - ID_STAGE - input logic debug_req_i, + input logic debug_req_i, // TO_BE_COMPLETED - FRONTEND - output logic set_debug_pc_o, + output logic set_debug_pc_o, // trap virtual memory - ID_STAGE - output logic tvm_o, + output logic tvm_o, // timeout wait - ID_STAGE - output logic tw_o, + output logic tw_o, // trap sret - ID_STAGE - output logic tsr_o, + output logic tsr_o, // we are in debug mode -> that will change some decoding - EX_STAGE - output logic debug_mode_o, + output logic debug_mode_o, // we are in single-step mode - COMMIT_STAGE - output logic single_step_o, + output logic single_step_o, // L1 ICache Enable - CACHE - output logic icache_en_o, + output logic icache_en_o, // L1 DCache Enable - CACHE - output logic dcache_en_o, + output logic dcache_en_o, // Accelerator memory consistent mode - ACC_DISPATCHER - output logic acc_cons_en_o, + output logic acc_cons_en_o, // Performance Counter // read/write address to performance counter module - PERF_COUNTERS - output logic [11:0] perf_addr_o, + output logic [ 11:0] perf_addr_o, // write data to performance counter module - PERF_COUNTERS - output logic [riscv::XLEN-1:0] perf_data_o, + output logic [ riscv::XLEN-1:0] perf_data_o, // read data from performance counter module - PERF_COUNTERS - input logic [riscv::XLEN-1:0] perf_data_i, + input logic [ riscv::XLEN-1:0] perf_data_i, // TO_BE_COMPLETED - PERF_COUNTERS - output logic perf_we_o, + output logic perf_we_o, // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER - output riscv::pmpcfg_t [15:0] pmpcfg_o, + output riscv::pmpcfg_t [ 15:0] pmpcfg_o, // PMP addresses - ACC_DISPATCHER - output logic [15:0][riscv::PLEN-3:0] pmpaddr_o, + output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o, // TO_BE_COMPLETED - PERF_COUNTERS - output logic [31:0] mcountinhibit_o + output logic [ 31:0] mcountinhibit_o ); // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 993d8f6267..2ce58a43db 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -159,7 +159,7 @@ module ex_stage // TO_BE_COMPLETED - CSR_REGFILE input logic [ASID_WIDTH-1:0] asid_i, // icache translation response - CACHE - input icache_arsp_t icache_areq_i, + input icache_arsp_t icache_areq_i, // icache translation request - CACHE output icache_areq_t icache_areq_o, // TO_BE_COMPLETED - CACHE diff --git a/core/include/cv32a65x_config_pkg.sv b/core/include/cv32a65x_config_pkg.sv index 06cd5a1f93..4fe74bfd03 100644 --- a/core/include/cv32a65x_config_pkg.sv +++ b/core/include/cv32a65x_config_pkg.sv @@ -92,7 +92,6 @@ package cva6_config_pkg; XFVec: bit'(CVA6ConfigFVecEn), CvxifEn: bit'(CVA6ConfigCvxifEn), ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn), - // Extended RVF: bit'(0), RVD: bit'(0), FpPresent: bit'(0), @@ -119,15 +118,12 @@ package cva6_config_pkg; PMPAddrRstVal: {16{64'h0}}, PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, - // idempotent region NrNonIdempotentRules: unsigned'(2), NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), NonIdempotentLength: 1024'({64'b0, 64'b0}), NrExecuteRegionRules: unsigned'(3), - // DRAM, Boot ROM, Debug Module ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}), ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}), - // cached region NrCachedRegionRules: unsigned'(1), CachedRegionAddrBase: 1024'({64'h8000_0000}), CachedRegionLength: 1024'({64'h40000000}), diff --git a/core/issue_stage.sv b/core/issue_stage.sv index 5a1b0dc097..b8dc224e1b 100644 --- a/core/issue_stage.sv +++ b/core/issue_stage.sv @@ -108,7 +108,7 @@ module issue_stage // TO_BE_COMPLETED - EX_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i, // TO_BE_COMPLETED - COMMIT_STAGE - output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] COMMIT_STAGE, + output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o, // TO_BE_COMPLETED - COMMIT_STAGE input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Issue stall - PERF_COUNTERS diff --git a/docs/04_cv32a65x_design/source/port_bht.rst b/docs/04_cv32a65x_design/source/port_bht.rst index 052cfeb833..66f695d0bc 100644 --- a/docs/04_cv32a65x_design/source/port_bht.rst +++ b/docs/04_cv32a65x_design/source/port_bht.rst @@ -45,7 +45,7 @@ * - ``vpc_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Virtual PC * - ``bht_update_i`` @@ -57,5 +57,5 @@ * - ``bht_prediction_o`` - out - FRONTEND - - ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0] - Prediction from bht diff --git a/docs/04_cv32a65x_design/source/port_btb.rst b/docs/04_cv32a65x_design/source/port_btb.rst index 7647655912..cfb7362c2f 100644 --- a/docs/04_cv32a65x_design/source/port_btb.rst +++ b/docs/04_cv32a65x_design/source/port_btb.rst @@ -45,7 +45,7 @@ * - ``vpc_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Virtual PC * - ``btb_update_i`` @@ -57,5 +57,5 @@ * - ``btb_prediction_o`` - out - FRONTEND - - ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0] - BTB Prediction diff --git a/docs/04_cv32a65x_design/source/port_commit_stage.rst b/docs/04_cv32a65x_design/source/port_commit_stage.rst index 7669471dc0..c32c404637 100644 --- a/docs/04_cv32a65x_design/source/port_commit_stage.rst +++ b/docs/04_cv32a65x_design/source/port_commit_stage.rst @@ -60,34 +60,40 @@ - logic - TO_BE_COMPLETED + * - ``commit_instr_i`` + - in + - ISSUE_STAGE + - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0] + - The instruction we want to commit + * - ``commit_ack_o`` - out - ISSUE_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - Acknowledge that we are indeed committing * - ``waddr_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][4:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][4:0] - Register file write address * - ``wdata_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] - Register file write data * - ``we_gpr_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - Register file write enable * - ``we_fpr_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - Floating point register enable * - ``amo_resp_i`` @@ -99,7 +105,7 @@ * - ``pc_o`` - out - FRONTEND_CSR - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``csr_op_o`` @@ -123,7 +129,7 @@ * - ``csr_exception_i`` - in - CSR_REGFILE - - exception_t + - exception_t - Exception or interrupt occurred in CSR stage (the same as commit) * - ``csr_write_fflags_o`` @@ -147,7 +153,7 @@ * - ``commit_tran_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - Transaction id of first commit port * - ``amo_valid_commit_o`` diff --git a/docs/04_cv32a65x_design/source/port_csr_regfile.rst b/docs/04_cv32a65x_design/source/port_csr_regfile.rst index ff5c46c6b7..69a54429af 100644 --- a/docs/04_cv32a65x_design/source/port_csr_regfile.rst +++ b/docs/04_cv32a65x_design/source/port_csr_regfile.rst @@ -48,16 +48,28 @@ - logic - halt requested + * - ``commit_instr_i`` + - in + - ID_STAGE + - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0] + - Instruction to be committed + + * - ``commit_ack_i`` + - in + - COMMIT_STAGE + - logic[CVA6Cfg.NrCommitPorts-1:0] + - Commit acknowledged a instruction -> increase instret CSR + * - ``boot_addr_i`` - in - SUBSYSTEM - - logic[riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Address from which to start booting, mtvec is set to the same address * - ``hart_id_i`` - in - SUBSYSTEM - - logic[riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Hart id in a multicore environment (reflected in a CSR) * - ``ex_i`` @@ -75,19 +87,19 @@ * - ``csr_addr_i`` - in - EX_STAGE - - logic [11:0] + - logic[11:0] - Address of the register to read/write * - ``csr_wdata_i`` - in - COMMIT_STAGE - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Write data in * - ``csr_rdata_o`` - out - COMMIT_STAGE - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Read data out * - ``dirty_fp_state_i`` @@ -99,7 +111,7 @@ * - ``csr_write_fflags_i`` - in - COMMIT_STAGE - - logic + - logic - Write fflags register e.g.: we are retiring a floating point instruction * - ``dirty_v_state_i`` @@ -111,7 +123,7 @@ * - ``pc_i`` - in - COMMIT_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - PC of instruction accessing the CSR * - ``csr_exception_o`` @@ -123,7 +135,7 @@ * - ``epc_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly * - ``eret_o`` @@ -135,7 +147,7 @@ * - ``trap_vector_base_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Output base of exception vector, correct CSR is output (mtvec, stvec) * - ``priv_lvl_o`` @@ -144,6 +156,12 @@ - riscv::priv_lvl_t - Current privilege level the CPU is in + * - ``acc_fflags_ex_i`` + - in + - ACC_DISPATCHER + - logic[4:0] + - Imprecise FP exception from the accelerator (fcsr.fflags format) + * - ``acc_fflags_ex_valid_i`` - in - ACC_DISPATCHER @@ -159,19 +177,19 @@ * - ``fflags_o`` - out - COMMIT_STAGE - - logic [4:0] + - logic[4:0] - Floating-Point Accured Exceptions * - ``frm_o`` - out - EX_STAGE - - logic [2:0] + - logic[2:0] - Floating-Point Dynamic Rounding Mode * - ``fprec_o`` - out - EX_STAGE - - logic [6:0] + - logic[6:0] - Floating-Point Precision Control * - ``vs_o`` @@ -198,6 +216,12 @@ - logic - enable VA translation for load and stores + * - ``ld_st_priv_lvl_o`` + - out + - EX_STAGE + - riscv::priv_lvl_t + - Privilege level at which load and stores should happen + * - ``sum_o`` - out - EX_STAGE @@ -213,19 +237,19 @@ * - ``satp_ppn_o`` - out - EX_STAGE - - logic [riscv::PPNW-1:0] + - logic[riscv::PPNW-1:0] - TO_BE_COMPLETED * - ``asid_o`` - out - EX_STAGE - - logic [AsidWidth-1:0] + - logic[AsidWidth-1:0] - TO_BE_COMPLETED * - ``irq_i`` - in - SUBSYSTEM - - logic [1:0] + - logic[1:0] - external interrupt in * - ``ipi_i`` @@ -297,19 +321,19 @@ * - ``perf_addr_o`` - out - PERF_COUNTERS - - logic [11:0] + - logic[11:0] - read/write address to performance counter module * - ``perf_data_o`` - out - PERF_COUNTERS - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - write data to performance counter module * - ``perf_data_i`` - in - PERF_COUNTERS - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - read data from performance counter module * - ``perf_we_o`` @@ -321,17 +345,17 @@ * - ``pmpcfg_o`` - out - ACC_DISPATCHER - - riscv::pmpcfg_t [15:0] + - riscv::pmpcfg_t[15:0] - PMP configuration containing pmpcfg for max 16 PMPs * - ``pmpaddr_o`` - out - ACC_DISPATCHER - - logic [15:0][riscv::PLEN-3:0] + - logic[15:0][riscv::PLEN-3:0] - PMP addresses * - ``mcountinhibit_o`` - out - PERF_COUNTERS - - logic [31:0] + - logic[31:0] - TO_BE_COMPLETED diff --git a/docs/04_cv32a65x_design/source/port_cva6.rst b/docs/04_cv32a65x_design/source/port_cva6.rst index bf1249f2d1..2afd967873 100644 --- a/docs/04_cv32a65x_design/source/port_cva6.rst +++ b/docs/04_cv32a65x_design/source/port_cva6.rst @@ -33,19 +33,19 @@ * - ``boot_addr_i`` - in - SUBSYSTEM - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Reset boot address * - ``hart_id_i`` - in - SUBSYSTEM - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Hard ID reflected as CSR * - ``irq_i`` - in - SUBSYSTEM - - logic [1:0] + - logic[1:0] - Level sensitive (async) interrupts * - ``ipi_i`` diff --git a/docs/04_cv32a65x_design/source/port_ex_stage.rst b/docs/04_cv32a65x_design/source/port_ex_stage.rst index 6a2a1ca084..355aa20108 100644 --- a/docs/04_cv32a65x_design/source/port_ex_stage.rst +++ b/docs/04_cv32a65x_design/source/port_ex_stage.rst @@ -45,13 +45,13 @@ * - ``rs1_forwarding_i`` - in - ID_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``rs2_forwarding_i`` - in - ID_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``fu_data_i`` @@ -63,7 +63,7 @@ * - ``pc_i`` - in - ID_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - PC of the current instruction * - ``is_compressed_instr_i`` @@ -81,7 +81,7 @@ * - ``flu_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - ID of the scoreboard entry at which a=to write back * - ``flu_exception_o`` @@ -141,7 +141,7 @@ * - ``csr_addr_o`` - out - CSR_REGISTERS - - logic [11:0] + - logic[11:0] - TO_BE_COMPLETED * - ``csr_commit_i`` @@ -183,7 +183,7 @@ * - ``load_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``load_exception_o`` @@ -207,7 +207,7 @@ * - ``store_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``store_exception_o`` @@ -231,7 +231,7 @@ * - ``commit_tran_id_i`` - in - COMMIT_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``stall_st_pending_i`` @@ -267,31 +267,31 @@ * - ``fpu_fmt_i`` - in - ID_STAGE - - logic [1:0] + - logic[1:0] - report FP format * - ``fpu_rm_i`` - in - ID_STAGE - - logic [2:0] + - logic[2:0] - FP rm * - ``fpu_frm_i`` - in - ID_STAGE - - logic [2:0] + - logic[2:0] - FP frm * - ``fpu_prec_i`` - in - CSR_REGFILE - - logic [6:0] + - logic[6:0] - FP precision control * - ``fpu_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``fpu_result_o`` @@ -327,13 +327,13 @@ * - ``x_off_instr_i`` - in - ID_STAGE - - logic [31:0] + - logic[31:0] - TO_BE_COMPLETED * - ``x_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``x_exception_o`` @@ -423,19 +423,19 @@ * - ``satp_ppn_i`` - in - CSR_REGFILE - - logic [riscv::PPNW-1:0] + - logic[riscv::PPNW-1:0] - TO_BE_COMPLETED * - ``asid_i`` - in - CSR_REGFILE - - logic [ASID_WIDTH-1:0] + - logic[ASID_WIDTH-1:0] - TO_BE_COMPLETED * - ``icache_areq_i`` - in - CACHE - - icache_arsp_t + - icache_arsp_t - icache translation response * - ``icache_areq_o`` @@ -447,13 +447,13 @@ * - ``dcache_req_ports_i`` - in - CACHE - - dcache_req_o_t [2:0] + - dcache_req_o_t[2:0] - TO_BE_COMPLETED * - ``dcache_req_ports_o`` - out - CACHE - - dcache_req_i_t [2:0] + - dcache_req_i_t[2:0] - TO_BE_COMPLETED * - ``dcache_wbuffer_empty_i`` @@ -495,13 +495,13 @@ * - ``pmpcfg_i`` - in - CSR_REGFILE - - riscv::pmpcfg_t [15:0] + - riscv::pmpcfg_t[15:0] - Report the PMP configuration * - ``pmpaddr_i`` - in - CSR_REGFILE - - logic [15:0][riscv::PLEN-3:0] + - logic[15:0][riscv::PLEN-3:0] - Report the PMP addresses * - ``rvfi_lsu_ctrl_o`` diff --git a/docs/04_cv32a65x_design/source/port_frontend.rst b/docs/04_cv32a65x_design/source/port_frontend.rst index 9306ba75fe..1d8b6b31a3 100644 --- a/docs/04_cv32a65x_design/source/port_frontend.rst +++ b/docs/04_cv32a65x_design/source/port_frontend.rst @@ -57,7 +57,7 @@ * - ``boot_addr_i`` - in - SUBSYSTEM - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when reset * - ``resolved_branch_i`` @@ -75,13 +75,13 @@ * - ``pc_commit_i`` - in - COMMIT - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when flushing pipeline * - ``epc_i`` - in - CSR - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when returning from exception * - ``eret_i`` @@ -93,7 +93,7 @@ * - ``trap_vector_base_i`` - in - CSR - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Next PC when jumping into exception * - ``ex_valid_i`` diff --git a/docs/04_cv32a65x_design/source/port_id_stage.rst b/docs/04_cv32a65x_design/source/port_id_stage.rst index 4961073a27..dccc51ed53 100644 --- a/docs/04_cv32a65x_design/source/port_id_stage.rst +++ b/docs/04_cv32a65x_design/source/port_id_stage.rst @@ -69,7 +69,7 @@ * - ``orig_instr_o`` - out - ISSUE - - logic [31:0] + - logic[31:0] - instruction value * - ``issue_entry_valid_o`` @@ -111,7 +111,7 @@ * - ``frm_i`` - in - CSR - - logic [2:0] + - logic[2:0] - Report floating point dynamic rounding mode * - ``vs_i`` @@ -123,7 +123,7 @@ * - ``irq_i`` - in - SUBSYSTEM - - logic [1:0] + - logic[1:0] - Level sensitive (async) interrupts * - ``irq_ctrl_i`` diff --git a/docs/04_cv32a65x_design/source/port_instr_queue.rst b/docs/04_cv32a65x_design/source/port_instr_queue.rst index 9daf85819b..04c5d2818d 100644 --- a/docs/04_cv32a65x_design/source/port_instr_queue.rst +++ b/docs/04_cv32a65x_design/source/port_instr_queue.rst @@ -39,19 +39,19 @@ * - ``instr_i`` - in - instr_realign - - logic [ariane_pkg::INSTR_PER_FETCH-1:0][31:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0][31:0] - Instruction * - ``addr_i`` - in - instr_realign - - logic [ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] - Instruction address * - ``valid_i`` - in - instr_realign - - logic [ariane_pkg::INSTR_PER_FETCH-1:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0] - Instruction is valid * - ``ready_o`` @@ -63,7 +63,7 @@ * - ``consumed_o`` - out - FRONTEND - - logic [ariane_pkg::INSTR_PER_FETCH-1:0] + - logic[ariane_pkg::INSTR_PER_FETCH-1:0] - Indicates instructions consummed, or popped by ID_STAGE * - ``exception_i`` @@ -75,19 +75,19 @@ * - ``exception_addr_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Exception address * - ``predict_address_i`` - in - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Branch predict * - ``cf_type_i`` - in - FRONTEND - - ariane_pkg::cf_t [ariane_pkg::INSTR_PER_FETCH-1:0] + - ariane_pkg::cf_t[ariane_pkg::INSTR_PER_FETCH-1:0] - Instruction predict address * - ``replay_o`` @@ -99,7 +99,7 @@ * - ``replay_addr_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Address at which to replay the fetch * - ``fetch_entry_o`` diff --git a/docs/04_cv32a65x_design/source/port_instr_realign.rst b/docs/04_cv32a65x_design/source/port_instr_realign.rst index dc1b2c5a40..30f87a5d0b 100644 --- a/docs/04_cv32a65x_design/source/port_instr_realign.rst +++ b/docs/04_cv32a65x_design/source/port_instr_realign.rst @@ -51,29 +51,29 @@ * - ``address_i`` - in - CACHE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - 32-bit block address * - ``data_i`` - in - CACHE - - logic [FETCH_WIDTH-1:0] + - logic[FETCH_WIDTH-1:0] - 32-bit block * - ``valid_o`` - out - FRONTEND - - logic [INSTR_PER_FETCH-1:0] + - logic[INSTR_PER_FETCH-1:0] - instruction is valid * - ``addr_o`` - out - FRONTEND - - logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] + - logic[INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] - Instruction address * - ``instr_o`` - out - none - - logic [INSTR_PER_FETCH-1:0][31:0] + - logic[INSTR_PER_FETCH-1:0][31:0] - none diff --git a/docs/04_cv32a65x_design/source/port_instr_scan.rst b/docs/04_cv32a65x_design/source/port_instr_scan.rst index 1fad65915a..4a88596fb1 100644 --- a/docs/04_cv32a65x_design/source/port_instr_scan.rst +++ b/docs/04_cv32a65x_design/source/port_instr_scan.rst @@ -21,7 +21,7 @@ * - ``instr_i`` - in - instr_realign - - logic [31:0] + - logic[31:0] - Instruction to be predecoded * - ``rvi_return_o`` @@ -57,7 +57,7 @@ * - ``rvi_imm_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Instruction immediat * - ``rvc_branch_o`` @@ -99,5 +99,5 @@ * - ``rvc_imm_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Instruction compressed immediat diff --git a/docs/04_cv32a65x_design/source/port_issue_stage.rst b/docs/04_cv32a65x_design/source/port_issue_stage.rst index ef76c1493d..8326d90c4b 100644 --- a/docs/04_cv32a65x_design/source/port_issue_stage.rst +++ b/docs/04_cv32a65x_design/source/port_issue_stage.rst @@ -63,7 +63,7 @@ * - ``orig_instr_i`` - in - ID_STAGE - - logic [31:0] + - logic[31:0] - instruction value * - ``decoded_instr_valid_i`` @@ -105,7 +105,7 @@ * - ``pc_o`` - out - EX_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``is_compressed_instr_o`` @@ -177,13 +177,13 @@ * - ``fpu_fmt_o`` - out - EX_STAGE - - logic [1:0] + - logic[1:0] - Report FP fmt field * - ``fpu_rm_o`` - out - EX_STAGE - - logic [2:0] + - logic[2:0] - report FP rm field * - ``csr_valid_o`` @@ -207,7 +207,7 @@ * - ``x_off_instr_o`` - out - EX_STAGE - - logic [31:0] + - logic[31:0] - TO_BE_COMPLETED * - ``issue_instr_o`` @@ -225,7 +225,7 @@ * - ``trans_id_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``resolved_branch_i`` @@ -237,19 +237,19 @@ * - ``wbdata_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] - TO_BE_COMPLETED * - ``ex_ex_i`` - in - EX_STAGE - - exception_t [CVA6Cfg.NrWbPorts-1:0] + - exception_t[CVA6Cfg.NrWbPorts-1:0] - exception from execute stage or CVXIF offloaded instruction * - ``wt_valid_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrWbPorts-1:0] + - logic[CVA6Cfg.NrWbPorts-1:0] - TO_BE_COMPLETED * - ``x_we_i`` @@ -261,37 +261,37 @@ * - ``waddr_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][4:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][4:0] - TO_BE_COMPLETED * - ``wdata_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] - TO_BE_COMPLETED * - ``we_gpr_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED * - ``we_fpr_i`` - in - EX_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED - * - ``COMMIT_STAGE`` + * - ``commit_instr_o`` - out - COMMIT_STAGE - - scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] + - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED * - ``commit_ack_i`` - in - COMMIT_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - TO_BE_COMPLETED * - ``stall_issue_o`` @@ -303,11 +303,11 @@ * - ``rvfi_issue_pointer_o`` - out - SUBSYSTEM - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - Information dedicated to RVFI * - ``rvfi_commit_pointer_o`` - out - SUBSYSTEM - - logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] - Information dedicated to RVFI diff --git a/docs/04_cv32a65x_design/source/port_ras.rst b/docs/04_cv32a65x_design/source/port_ras.rst index f8a83cbbae..f6d2372f23 100644 --- a/docs/04_cv32a65x_design/source/port_ras.rst +++ b/docs/04_cv32a65x_design/source/port_ras.rst @@ -51,7 +51,7 @@ * - ``data_i`` - in - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Data to be pushed * - ``data_o`` diff --git a/docs/scripts/table_port_builder.py b/docs/scripts/table_port_builder.py index 29946243b3..abca98aa05 100755 --- a/docs/scripts/table_port_builder.py +++ b/docs/scripts/table_port_builder.py @@ -56,16 +56,18 @@ def __init__( description = "none" connection = "none" for line in fin: - e = re.match(r"^ +(?:(in|out))put ([\S]*(?: [\S]*|)) ([\S]*)\n", line) + e = re.match(r"^ +(?:(in|out))put +([\S]*(?: +.* *|)) ([\S]*)\n", line) d = re.match(r"^ +\/\/ (.*) - ([\S]*)\n", line) if d: description = d.group(1) connection = d.group(2) if e: name = e.group(3) - name = name.split(",") + name = name.replace(",", "") + data_type = e.group(2) + data_type = data_type.replace(" ", "") ports.append( - PortIO(name[0], e.group(1), e.group(2), description, connection) + PortIO(name, e.group(1), data_type, description, connection) ) description = "none" connection = "none"