diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 551b8a296f4..d0dcc25be0f 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -33,7 +33,7 @@ module commit_stage // TO_BE_COMPLETED - CSR_REGFILE input logic single_step_i, // The instruction we want to commit - ISSUE_STAGE - input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // Acknowledge that we are indeed committing - ISSUE_STAGE output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o, // Register file write address - ID_STAGE @@ -55,7 +55,7 @@ module commit_stage // Data to read from CSR - CSR_REGFILE input riscv::xlen_t csr_rdata_i, // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE - input exception_t csr_exception_i, + input exception_t csr_exception_i, // Write the fflags CSR - CSR_REGFILE output logic csr_write_fflags_o, // Commit the pending store - EX_STAGE diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 5b0bfe05754..8ddf8fd478c 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -21,121 +21,121 @@ module csr_regfile parameter int unsigned MHPMCounterNum = 6 ) ( // Subsystem Clock - SUBSYSTEM - input logic clk_i, + input logic clk_i, // Asynchronous reset active low - SUBSYSTEM - input logic rst_ni, + input logic rst_ni, // Timer threw a interrupt - SUBSYSTEM - input logic time_irq_i, + input logic time_irq_i, // send a flush request out when a CSR with a side effect changes - CONTROLLER - output logic flush_o, + output logic flush_o, // halt requested - CONTROLLER - output logic halt_csr_o, + output logic halt_csr_o, // Instruction to be committed - ID_STAGE - input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE - input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM - input logic[riscv::VLEN-1:0] boot_addr_i, + input logic [ riscv::VLEN-1:0] boot_addr_i, // Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM - input logic[riscv::XLEN-1:0] hart_id_i, + input logic [ riscv::XLEN-1:0] hart_id_i, // we are taking an exception // We've got an exception from the commit stage, take it - COMMIT_STAGE - input exception_t ex_i, + input exception_t ex_i, // Operation to perform on the CSR file - COMMIT_STAGE - input fu_op csr_op_i, + input fu_op csr_op_i, // Address of the register to read/write - EX_STAGE - input logic [11:0] csr_addr_i, + input logic [ 11:0] csr_addr_i, // Write data in - COMMIT_STAGE - input logic [riscv::XLEN-1:0] csr_wdata_i, + input logic [ riscv::XLEN-1:0] csr_wdata_i, // Read data out - COMMIT_STAGE - output logic [riscv::XLEN-1:0] csr_rdata_o, + output logic [ riscv::XLEN-1:0] csr_rdata_o, // Mark the FP sate as dirty - COMMIT_STAGE - input logic dirty_fp_state_i, + input logic dirty_fp_state_i, // Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE - input logic csr_write_fflags_i, + input logic csr_write_fflags_i, // Mark the V state as dirty - ACC_DISPATCHER - input logic dirty_v_state_i, + input logic dirty_v_state_i, // PC of instruction accessing the CSR - COMMIT_STAGE - input logic [riscv::VLEN-1:0] pc_i, + input logic [ riscv::VLEN-1:0] pc_i, // attempts to access a CSR without appropriate privilege - COMMIT_STAGE - output exception_t csr_exception_o, + output exception_t csr_exception_o, // Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly - FRONTEND - output logic [riscv::VLEN-1:0] epc_o, + output logic [ riscv::VLEN-1:0] epc_o, // Return from exception, set the PC of epc_o - FRONTEND - output logic eret_o, + output logic eret_o, // Output base of exception vector, correct CSR is output (mtvec, stvec) - FRONTEND - output logic [riscv::VLEN-1:0] trap_vector_base_o, + output logic [ riscv::VLEN-1:0] trap_vector_base_o, // Current privilege level the CPU is in - EX_STAGE - output riscv::priv_lvl_t priv_lvl_o, + output riscv::priv_lvl_t priv_lvl_o, // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER - input logic [4:0] acc_fflags_ex_i, + input logic [ 4:0] acc_fflags_ex_i, // An FP exception from the accelerator occurred - ACC_DISPATCHER - input logic acc_fflags_ex_valid_i, + input logic acc_fflags_ex_valid_i, // Floating point extension status - ID_STAGE - output riscv::xs_t fs_o, + output riscv::xs_t fs_o, // Floating-Point Accured Exceptions - COMMIT_STAGE - output logic [4:0] fflags_o, + output logic [ 4:0] fflags_o, // Floating-Point Dynamic Rounding Mode - EX_STAGE - output logic [2:0] frm_o, + output logic [ 2:0] frm_o, // Floating-Point Precision Control - EX_STAGE - output logic [6:0] fprec_o, + output logic [ 6:0] fprec_o, // Vector extension status - ID_STAGE - output riscv::xs_t vs_o, + output riscv::xs_t vs_o, // interrupt management to id stage - ID_STAGE - output irq_ctrl_t irq_ctrl_o, + output irq_ctrl_t irq_ctrl_o, // enable VA translation - EX_STAGE - output logic en_translation_o, + output logic en_translation_o, // enable VA translation for load and stores - EX_STAGE - output logic en_ld_st_translation_o, + output logic en_ld_st_translation_o, // Privilege level at which load and stores should happen - EX_STAGE - output riscv::priv_lvl_t ld_st_priv_lvl_o, + output riscv::priv_lvl_t ld_st_priv_lvl_o, // TO_BE_COMPLETED - EX_STAGE - output logic sum_o, + output logic sum_o, // TO_BE_COMPLETED - EX_STAGE - output logic mxr_o, + output logic mxr_o, // TO_BE_COMPLETED - EX_STAGE - output logic [riscv::PPNW-1:0] satp_ppn_o, + output logic [ riscv::PPNW-1:0] satp_ppn_o, // TO_BE_COMPLETED - EX_STAGE - output logic [AsidWidth-1:0] asid_o, + output logic [ AsidWidth-1:0] asid_o, // external interrupt in - SUBSYSTEM - input logic [1:0] irq_i, + input logic [ 1:0] irq_i, // inter processor interrupt -> connected to machine mode sw - SUBSYSTEM - input logic ipi_i, + input logic ipi_i, // debug request in - ID_STAGE - input logic debug_req_i, + input logic debug_req_i, // TO_BE_COMPLETED - FRONTEND - output logic set_debug_pc_o, + output logic set_debug_pc_o, // trap virtual memory - ID_STAGE - output logic tvm_o, + output logic tvm_o, // timeout wait - ID_STAGE - output logic tw_o, + output logic tw_o, // trap sret - ID_STAGE - output logic tsr_o, + output logic tsr_o, // we are in debug mode -> that will change some decoding - EX_STAGE - output logic debug_mode_o, + output logic debug_mode_o, // we are in single-step mode - COMMIT_STAGE - output logic single_step_o, + output logic single_step_o, // L1 ICache Enable - CACHE - output logic icache_en_o, + output logic icache_en_o, // L1 DCache Enable - CACHE - output logic dcache_en_o, + output logic dcache_en_o, // Accelerator memory consistent mode - ACC_DISPATCHER - output logic acc_cons_en_o, + output logic acc_cons_en_o, // Performance Counter // read/write address to performance counter module - PERF_COUNTERS - output logic [11:0] perf_addr_o, + output logic [ 11:0] perf_addr_o, // write data to performance counter module - PERF_COUNTERS - output logic [riscv::XLEN-1:0] perf_data_o, + output logic [ riscv::XLEN-1:0] perf_data_o, // read data from performance counter module - PERF_COUNTERS - input logic [riscv::XLEN-1:0] perf_data_i, + input logic [ riscv::XLEN-1:0] perf_data_i, // TO_BE_COMPLETED - PERF_COUNTERS - output logic perf_we_o, + output logic perf_we_o, // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER - output riscv::pmpcfg_t [15:0] pmpcfg_o, + output riscv::pmpcfg_t [ 15:0] pmpcfg_o, // PMP addresses - ACC_DISPATCHER - output logic [15:0][riscv::PLEN-3:0] pmpaddr_o, + output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o, // TO_BE_COMPLETED - PERF_COUNTERS - output logic [31:0] mcountinhibit_o + output logic [ 31:0] mcountinhibit_o ); // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; diff --git a/core/ex_stage.sv b/core/ex_stage.sv index 993d8f6267a..2ce58a43dbc 100644 --- a/core/ex_stage.sv +++ b/core/ex_stage.sv @@ -159,7 +159,7 @@ module ex_stage // TO_BE_COMPLETED - CSR_REGFILE input logic [ASID_WIDTH-1:0] asid_i, // icache translation response - CACHE - input icache_arsp_t icache_areq_i, + input icache_arsp_t icache_areq_i, // icache translation request - CACHE output icache_areq_t icache_areq_o, // TO_BE_COMPLETED - CACHE diff --git a/docs/04_cv32a65x_design/source/port_commit_stage.rst b/docs/04_cv32a65x_design/source/port_commit_stage.rst index 7669471dc0c..c32c404637d 100644 --- a/docs/04_cv32a65x_design/source/port_commit_stage.rst +++ b/docs/04_cv32a65x_design/source/port_commit_stage.rst @@ -60,34 +60,40 @@ - logic - TO_BE_COMPLETED + * - ``commit_instr_i`` + - in + - ISSUE_STAGE + - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0] + - The instruction we want to commit + * - ``commit_ack_o`` - out - ISSUE_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - Acknowledge that we are indeed committing * - ``waddr_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][4:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][4:0] - Register file write address * - ``wdata_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] - Register file write data * - ``we_gpr_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - Register file write enable * - ``we_fpr_o`` - out - ID_STAGE - - logic [CVA6Cfg.NrCommitPorts-1:0] + - logic[CVA6Cfg.NrCommitPorts-1:0] - Floating point register enable * - ``amo_resp_i`` @@ -99,7 +105,7 @@ * - ``pc_o`` - out - FRONTEND_CSR - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``csr_op_o`` @@ -123,7 +129,7 @@ * - ``csr_exception_i`` - in - CSR_REGFILE - - exception_t + - exception_t - Exception or interrupt occurred in CSR stage (the same as commit) * - ``csr_write_fflags_o`` @@ -147,7 +153,7 @@ * - ``commit_tran_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - Transaction id of first commit port * - ``amo_valid_commit_o`` diff --git a/docs/04_cv32a65x_design/source/port_csr_regfile.rst b/docs/04_cv32a65x_design/source/port_csr_regfile.rst index ff5c46c6b76..69a54429aff 100644 --- a/docs/04_cv32a65x_design/source/port_csr_regfile.rst +++ b/docs/04_cv32a65x_design/source/port_csr_regfile.rst @@ -48,16 +48,28 @@ - logic - halt requested + * - ``commit_instr_i`` + - in + - ID_STAGE + - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0] + - Instruction to be committed + + * - ``commit_ack_i`` + - in + - COMMIT_STAGE + - logic[CVA6Cfg.NrCommitPorts-1:0] + - Commit acknowledged a instruction -> increase instret CSR + * - ``boot_addr_i`` - in - SUBSYSTEM - - logic[riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Address from which to start booting, mtvec is set to the same address * - ``hart_id_i`` - in - SUBSYSTEM - - logic[riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Hart id in a multicore environment (reflected in a CSR) * - ``ex_i`` @@ -75,19 +87,19 @@ * - ``csr_addr_i`` - in - EX_STAGE - - logic [11:0] + - logic[11:0] - Address of the register to read/write * - ``csr_wdata_i`` - in - COMMIT_STAGE - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Write data in * - ``csr_rdata_o`` - out - COMMIT_STAGE - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - Read data out * - ``dirty_fp_state_i`` @@ -99,7 +111,7 @@ * - ``csr_write_fflags_i`` - in - COMMIT_STAGE - - logic + - logic - Write fflags register e.g.: we are retiring a floating point instruction * - ``dirty_v_state_i`` @@ -111,7 +123,7 @@ * - ``pc_i`` - in - COMMIT_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - PC of instruction accessing the CSR * - ``csr_exception_o`` @@ -123,7 +135,7 @@ * - ``epc_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly * - ``eret_o`` @@ -135,7 +147,7 @@ * - ``trap_vector_base_o`` - out - FRONTEND - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - Output base of exception vector, correct CSR is output (mtvec, stvec) * - ``priv_lvl_o`` @@ -144,6 +156,12 @@ - riscv::priv_lvl_t - Current privilege level the CPU is in + * - ``acc_fflags_ex_i`` + - in + - ACC_DISPATCHER + - logic[4:0] + - Imprecise FP exception from the accelerator (fcsr.fflags format) + * - ``acc_fflags_ex_valid_i`` - in - ACC_DISPATCHER @@ -159,19 +177,19 @@ * - ``fflags_o`` - out - COMMIT_STAGE - - logic [4:0] + - logic[4:0] - Floating-Point Accured Exceptions * - ``frm_o`` - out - EX_STAGE - - logic [2:0] + - logic[2:0] - Floating-Point Dynamic Rounding Mode * - ``fprec_o`` - out - EX_STAGE - - logic [6:0] + - logic[6:0] - Floating-Point Precision Control * - ``vs_o`` @@ -198,6 +216,12 @@ - logic - enable VA translation for load and stores + * - ``ld_st_priv_lvl_o`` + - out + - EX_STAGE + - riscv::priv_lvl_t + - Privilege level at which load and stores should happen + * - ``sum_o`` - out - EX_STAGE @@ -213,19 +237,19 @@ * - ``satp_ppn_o`` - out - EX_STAGE - - logic [riscv::PPNW-1:0] + - logic[riscv::PPNW-1:0] - TO_BE_COMPLETED * - ``asid_o`` - out - EX_STAGE - - logic [AsidWidth-1:0] + - logic[AsidWidth-1:0] - TO_BE_COMPLETED * - ``irq_i`` - in - SUBSYSTEM - - logic [1:0] + - logic[1:0] - external interrupt in * - ``ipi_i`` @@ -297,19 +321,19 @@ * - ``perf_addr_o`` - out - PERF_COUNTERS - - logic [11:0] + - logic[11:0] - read/write address to performance counter module * - ``perf_data_o`` - out - PERF_COUNTERS - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - write data to performance counter module * - ``perf_data_i`` - in - PERF_COUNTERS - - logic [riscv::XLEN-1:0] + - logic[riscv::XLEN-1:0] - read data from performance counter module * - ``perf_we_o`` @@ -321,17 +345,17 @@ * - ``pmpcfg_o`` - out - ACC_DISPATCHER - - riscv::pmpcfg_t [15:0] + - riscv::pmpcfg_t[15:0] - PMP configuration containing pmpcfg for max 16 PMPs * - ``pmpaddr_o`` - out - ACC_DISPATCHER - - logic [15:0][riscv::PLEN-3:0] + - logic[15:0][riscv::PLEN-3:0] - PMP addresses * - ``mcountinhibit_o`` - out - PERF_COUNTERS - - logic [31:0] + - logic[31:0] - TO_BE_COMPLETED diff --git a/docs/04_cv32a65x_design/source/port_ex_stage.rst b/docs/04_cv32a65x_design/source/port_ex_stage.rst index 6a2a1ca0841..355aa201083 100644 --- a/docs/04_cv32a65x_design/source/port_ex_stage.rst +++ b/docs/04_cv32a65x_design/source/port_ex_stage.rst @@ -45,13 +45,13 @@ * - ``rs1_forwarding_i`` - in - ID_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``rs2_forwarding_i`` - in - ID_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - TO_BE_COMPLETED * - ``fu_data_i`` @@ -63,7 +63,7 @@ * - ``pc_i`` - in - ID_STAGE - - logic [riscv::VLEN-1:0] + - logic[riscv::VLEN-1:0] - PC of the current instruction * - ``is_compressed_instr_i`` @@ -81,7 +81,7 @@ * - ``flu_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - ID of the scoreboard entry at which a=to write back * - ``flu_exception_o`` @@ -141,7 +141,7 @@ * - ``csr_addr_o`` - out - CSR_REGISTERS - - logic [11:0] + - logic[11:0] - TO_BE_COMPLETED * - ``csr_commit_i`` @@ -183,7 +183,7 @@ * - ``load_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``load_exception_o`` @@ -207,7 +207,7 @@ * - ``store_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``store_exception_o`` @@ -231,7 +231,7 @@ * - ``commit_tran_id_i`` - in - COMMIT_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``stall_st_pending_i`` @@ -267,31 +267,31 @@ * - ``fpu_fmt_i`` - in - ID_STAGE - - logic [1:0] + - logic[1:0] - report FP format * - ``fpu_rm_i`` - in - ID_STAGE - - logic [2:0] + - logic[2:0] - FP rm * - ``fpu_frm_i`` - in - ID_STAGE - - logic [2:0] + - logic[2:0] - FP frm * - ``fpu_prec_i`` - in - CSR_REGFILE - - logic [6:0] + - logic[6:0] - FP precision control * - ``fpu_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``fpu_result_o`` @@ -327,13 +327,13 @@ * - ``x_off_instr_i`` - in - ID_STAGE - - logic [31:0] + - logic[31:0] - TO_BE_COMPLETED * - ``x_trans_id_o`` - out - ID_STAGE - - logic [TRANS_ID_BITS-1:0] + - logic[TRANS_ID_BITS-1:0] - TO_BE_COMPLETED * - ``x_exception_o`` @@ -423,19 +423,19 @@ * - ``satp_ppn_i`` - in - CSR_REGFILE - - logic [riscv::PPNW-1:0] + - logic[riscv::PPNW-1:0] - TO_BE_COMPLETED * - ``asid_i`` - in - CSR_REGFILE - - logic [ASID_WIDTH-1:0] + - logic[ASID_WIDTH-1:0] - TO_BE_COMPLETED * - ``icache_areq_i`` - in - CACHE - - icache_arsp_t + - icache_arsp_t - icache translation response * - ``icache_areq_o`` @@ -447,13 +447,13 @@ * - ``dcache_req_ports_i`` - in - CACHE - - dcache_req_o_t [2:0] + - dcache_req_o_t[2:0] - TO_BE_COMPLETED * - ``dcache_req_ports_o`` - out - CACHE - - dcache_req_i_t [2:0] + - dcache_req_i_t[2:0] - TO_BE_COMPLETED * - ``dcache_wbuffer_empty_i`` @@ -495,13 +495,13 @@ * - ``pmpcfg_i`` - in - CSR_REGFILE - - riscv::pmpcfg_t [15:0] + - riscv::pmpcfg_t[15:0] - Report the PMP configuration * - ``pmpaddr_i`` - in - CSR_REGFILE - - logic [15:0][riscv::PLEN-3:0] + - logic[15:0][riscv::PLEN-3:0] - Report the PMP addresses * - ``rvfi_lsu_ctrl_o`` diff --git a/verif/core-v-verif b/verif/core-v-verif index aa5fe849395..79d03a517f8 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit aa5fe849395171901b3ac0ae04c1c41a9f286490 +Subproject commit 79d03a517f8f09e3ca7c24332aec91bb78b47932