diff --git a/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv b/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv index 985e2bdfce..8a665b928b 100644 --- a/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv +++ b/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv @@ -30,7 +30,14 @@ privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; riscv_instr_name_t unsupported_instr[]; // ISA supported by the processor -riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32B, RV32X}; +riscv_instr_group_t supported_isa[$] = {RV32I, + RV32M, + RV32C, + RV32ZBA, + RV32ZBB, + RV32ZBC, + RV32ZBS, + RV32X}; // Interrupt mode support mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED}; diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index 27d7168c17..a955464f0c 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -97,15 +97,15 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; ext_v_supported == 0; ext_f_supported == 0; ext_d_supported == 0; - ext_zba_supported == 0; - ext_zbb_supported == 0; - ext_zbc_supported == 0; + ext_zba_supported == 1; + ext_zbb_supported == 1; + ext_zbc_supported == 1; ext_zbe_supported == 0; ext_zbf_supported == 0; ext_zbm_supported == 0; ext_zbp_supported == 0; ext_zbr_supported == 0; - ext_zbs_supported == 0; + ext_zbs_supported == 1; ext_zbt_supported == 0; ext_zifencei_supported == 1; ext_zicsr_supported == 1; diff --git a/verif/regress/dv-generated-tests.sh b/verif/regress/dv-generated-tests.sh index 4798c0dde5..eb87c29838 100644 --- a/verif/regress/dv-generated-tests.sh +++ b/verif/regress/dv-generated-tests.sh @@ -111,7 +111,7 @@ printf "+======================================================================= j=0 while [[ $j -lt ${#TEST_NAME[@]} ]];do cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ - python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 + python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 n=0 echo "Generate the test: ${TEST_NAME[j]}" #this while loop detects the failed tests from the log file and remove them diff --git a/verif/regress/dv-generated-xif-tests.sh b/verif/regress/dv-generated-xif-tests.sh index d43df11caa..867acce674 100644 --- a/verif/regress/dv-generated-xif-tests.sh +++ b/verif/regress/dv-generated-xif-tests.sh @@ -74,7 +74,7 @@ printf "+======================================================================= j=0 while [[ $j -lt ${#TEST_NAME[@]} ]];do cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ - python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 + python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 n=0 echo "Generate the test: ${TEST_NAME[j]}" #this while loop detects the failed tests from the log file and remove them diff --git a/verif/regress/smoke-gen_tests.sh b/verif/regress/smoke-gen_tests.sh index 666b13c568..c94fea3f2e 100644 --- a/verif/regress/smoke-gen_tests.sh +++ b/verif/regress/smoke-gen_tests.sh @@ -27,9 +27,9 @@ fi cd verif/sim/ cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ -python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 -python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 -python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 +python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_arithmetic_basic_test_comp --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 +python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 +python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=$DV_SIMULATORS $DV_OPTS -i 1 --iss_timeout 300 make clean_all cd - diff --git a/verif/sim/cva6_base_testlist.yaml b/verif/sim/cva6_base_testlist.yaml index 0de29f54fd..4fa161282e 100644 --- a/verif/sim/cva6_base_testlist.yaml +++ b/verif/sim/cva6_base_testlist.yaml @@ -39,7 +39,10 @@ +directed_instr_1=riscv_load_store_hazard_instr_stream,10 +directed_instr_2=riscv_multi_page_load_store_instr_stream,10 +directed_instr_3=riscv_mem_region_stress_test,10 - +disable_compressed_instr=0 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -56,6 +59,10 @@ +directed_instr_2=riscv_multi_page_load_store_instr_stream,10 +directed_instr_3=riscv_mem_region_stress_test,10 +hint_instr_ratio=500 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -70,6 +77,10 @@ +directed_instr_1=riscv_jal_instr,20 +illegal_instr_ratio=100 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -82,6 +93,10 @@ +num_of_sub_program=0 +directed_instr_1=riscv_jal_instr,70 +hint_instr_ratio=500 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -94,6 +109,10 @@ +num_of_sub_program=0 +directed_instr_0=riscv_jal_instr,70 +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -108,7 +127,10 @@ +no_branch_jump=0 +directed_instr_0=riscv_load_store_rand_instr_stream,70 +directed_instr_1=riscv_load_store_hazard_instr_stream,50 - +disable_compressed_instr=0 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -124,6 +146,10 @@ +directed_instr_0=riscv_load_store_rand_instr_stream,20 +directed_instr_1=riscv_load_store_hazard_instr_stream,50 +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -140,7 +166,10 @@ +no_branch_jump=1 +boot_mode=m +no_csr_instr=1 - +disable_compressed_instr=0 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -159,6 +188,10 @@ +enable_x_extension=1 +disable_compressed_instr=1 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -176,6 +209,10 @@ +enable_x_extension=1 +illegal_instr_ratio=100 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -192,6 +229,10 @@ +directed_instr_1=riscv_load_store_hazard_instr_stream,50 +tvec_alignment=8 +enable_x_extension=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -205,6 +246,10 @@ +directed_instr_1=riscv_jal_instr,70 +enable_x_extension=1 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -222,6 +267,10 @@ +boot_mode=m +no_csr_instr=1 +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -238,6 +287,10 @@ +no_branch_jump=1 +boot_mode=m +no_csr_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -254,6 +307,10 @@ +no_branch_jump=0 +boot_mode=m +no_csr_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -269,6 +326,10 @@ +no_branch_jump=1 +boot_mode=m +no_csr_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -285,6 +346,10 @@ +no_csr_instr=1 +illegal_instr_ratio=100 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -303,7 +368,10 @@ +directed_instr_1=riscv_load_store_hazard_instr_stream,20 +enable_unaligned_load_store=1 +tvec_alignment=8 - +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -322,6 +390,10 @@ +enable_access_invalid_csr_level=1 +disable_compressed_instr=1 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -338,6 +410,10 @@ +boot_mode=m +enable_dummy_csr_write=1 +no_csr_instr=0 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -357,6 +433,10 @@ +randomize_csr=1 +enable_acess_invalid_csr_level=1 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -376,6 +456,10 @@ +enable_illegal_csr_instruction=1 +hint_instr_ratio=150 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -396,6 +480,10 @@ +illegal_instr_ratio=100 +hint_instr_ratio=100 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -412,6 +500,10 @@ +no_branch_jump=1 +boot_mode=m +no_csr_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -430,6 +522,10 @@ +no_dret=0 +no_fence=0 +tvec_alignment=8 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -447,6 +543,10 @@ +no_csr_instr=1 +enable_same_reg=1 +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_hazard_test_c rtl_test: core_base_test @@ -464,6 +564,10 @@ +no_csr_instr=1 +enable_rdrs1_hazard=1 +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_hazard_test_c rtl_test: core_base_test @@ -481,6 +585,10 @@ +no_csr_instr=1 +enable_rdrs2_hazard=1 +disable_compressed_instr=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 iterations: 2 gen_test: cva6_instr_hazard_test_c rtl_test: core_base_test