From 78111aa5eb67aa0283f64b949ea2fedeaa86bc94 Mon Sep 17 00:00:00 2001 From: Michael Platzer Date: Wed, 17 Jan 2024 17:41:38 +0100 Subject: [PATCH] config_pkg/csr_regfile: Add PMP entry rst vals & RO option (#1769) This commit adds three new fields to the `cva6_cfg_t` configuration struct, which allows to specify reset values for the PMP configuration and address CSRs as well as optionally making individual PMP entries read-only. The purpose is to allow hard-wiring of certain regions' privileges, which is explicitly allowed by the RISC-V Privileged Architecture specification Machine-Level ISA, v1.12 (see Sect. 3.7). --- core/csr_regfile.sv | 19 +++++++++++++++---- core/cva6.sv | 3 +++ core/include/config_pkg.sv | 4 ++++ core/include/cv32a60x_config_pkg.sv | 3 +++ core/include/cv32a6_embedded_config_pkg.sv | 3 +++ .../cv32a6_ima_sv32_fpga_config_pkg.sv | 3 +++ core/include/cv32a6_imac_sv0_config_pkg.sv | 3 +++ core/include/cv32a6_imac_sv32_config_pkg.sv | 3 +++ core/include/cv32a6_imafc_sv32_config_pkg.sv | 3 +++ .../cv64a6_imadfcv_sv39_polara_config_pkg.sv | 3 +++ core/include/cv64a6_imafdc_sv39_config_pkg.sv | 3 +++ .../cv64a6_imafdc_sv39_hpdcache_config_pkg.sv | 3 +++ ...cv64a6_imafdc_sv39_openpiton_config_pkg.sv | 3 +++ .../cv64a6_imafdc_sv39_wb_config_pkg.sv | 3 +++ .../include/cv64a6_imafdcv_sv39_config_pkg.sv | 3 +++ corev_apu/fpga/src/ariane_xilinx.sv | 3 +++ 16 files changed, 61 insertions(+), 4 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 27e2252f9e..88c16444a4 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1554,8 +1554,15 @@ module csr_regfile // wait for interrupt wfi_q <= 1'b0; // pmp - pmpcfg_q <= '0; - pmpaddr_q <= '0; + for (int i = 0; i < 16; i++) begin + if (i < CVA6Cfg.NrPMPEntries) begin + pmpcfg_q[i] <= riscv::pmpcfg_t'(CVA6Cfg.PMPCfgRstVal[i]); + pmpaddr_q[i] <= CVA6Cfg.PMPAddrRstVal[i][riscv::PLEN-3:0]; + end else begin + pmpcfg_q[i] <= '0; + pmpaddr_q[i] <= '0; + end + end end else begin priv_lvl_q <= priv_lvl_d; // floating-point registers @@ -1607,12 +1614,16 @@ module csr_regfile for (int i = 0; i < 16; i++) begin if (i < CVA6Cfg.NrPMPEntries) begin // We only support >=8-byte granularity, NA4 is disabled - if(pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin + if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin pmpcfg_q[i] <= pmpcfg_d[i]; end else begin pmpcfg_q[i] <= pmpcfg_q[i]; end - pmpaddr_q[i] <= pmpaddr_d[i]; + if (!CVA6Cfg.PMPEntryReadOnly[i]) begin + pmpaddr_q[i] <= pmpaddr_d[i]; + end else begin + pmpaddr_q[i] <= pmpaddr_q[i]; + end end else begin pmpcfg_q[i] <= '0; pmpaddr_q[i] <= '0; diff --git a/core/cva6.sv b/core/cva6.sv index 777ea3865f..47ca5d6284 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -206,6 +206,9 @@ module cva6 CVA6Cfg.BHTEntries, CVA6Cfg.DmBaseAddress, CVA6Cfg.NrPMPEntries, + CVA6Cfg.PMPCfgRstVal, + CVA6Cfg.PMPAddrRstVal, + CVA6Cfg.PMPEntryReadOnly, CVA6Cfg.NOCType, CVA6Cfg.NrNonIdempotentRules, CVA6Cfg.NonIdempotentAddrBase, diff --git a/core/include/config_pkg.sv b/core/include/config_pkg.sv index 853bc290b6..90d6bfe159 100644 --- a/core/include/config_pkg.sv +++ b/core/include/config_pkg.sv @@ -89,6 +89,10 @@ package config_pkg; logic [63:0] DmBaseAddress; /// Number of PMP entries. int unsigned NrPMPEntries; + /// Physical Memory Protection (PMP) CSR reset values and read-only bits + logic [15:0][63:0] PMPCfgRstVal; + logic [15:0][63:0] PMPAddrRstVal; + bit [15:0] PMPEntryReadOnly; /// Set to the bus type in use. noc_type_e NOCType; /// Physical Memory Attributes (PMAs) diff --git a/core/include/cv32a60x_config_pkg.sv b/core/include/cv32a60x_config_pkg.sv index 7f00a04260..318caf2ba1 100644 --- a/core/include/cv32a60x_config_pkg.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_embedded_config_pkg.sv b/core/include/cv32a6_embedded_config_pkg.sv index f8129a317b..0181345a1e 100644 --- a/core/include/cv32a6_embedded_config_pkg.sv +++ b/core/include/cv32a6_embedded_config_pkg.sv @@ -115,6 +115,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv index b89243cd73..46b88ac4aa 100644 --- a/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv +++ b/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_imac_sv0_config_pkg.sv b/core/include/cv32a6_imac_sv0_config_pkg.sv index 11be0b699e..933e94be1a 100644 --- a/core/include/cv32a6_imac_sv0_config_pkg.sv +++ b/core/include/cv32a6_imac_sv0_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_imac_sv32_config_pkg.sv b/core/include/cv32a6_imac_sv32_config_pkg.sv index ac0365474c..a9737428f7 100644 --- a/core/include/cv32a6_imac_sv32_config_pkg.sv +++ b/core/include/cv32a6_imac_sv32_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv32a6_imafc_sv32_config_pkg.sv b/core/include/cv32a6_imafc_sv32_config_pkg.sv index a74a8c1cdc..ab4ee2c287 100644 --- a/core/include/cv32a6_imafc_sv32_config_pkg.sv +++ b/core/include/cv32a6_imafc_sv32_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv index f77599a1e4..5b1ca3647a 100644 --- a/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv +++ b/core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv @@ -115,6 +115,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_config_pkg.sv index 4f109453cb..ec4db64f57 100644 --- a/core/include/cv64a6_imafdc_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv index b6573865f6..7436decb25 100644 --- a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv @@ -123,6 +123,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv index b7809464bb..add8f15849 100644 --- a/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_L15_BIG_ENDIAN, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv index 3de8082671..f3ba6c40a4 100644 --- a/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv +++ b/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv @@ -116,6 +116,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv index 5adfaa7d3c..ff82a05cb5 100644 --- a/core/include/cv64a6_imafdcv_sv39_config_pkg.sv +++ b/core/include/cv64a6_imafdcv_sv39_config_pkg.sv @@ -115,6 +115,9 @@ package cva6_config_pkg; BHTEntries: unsigned'(CVA6ConfigBHTEntries), DmBaseAddress: 64'h0, NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index c676aff655..fcda4b5f48 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -197,6 +197,9 @@ localparam config_pkg::cva6_cfg_t CVA6Cfg = '{ ExceptionAddress: dm::ExceptionAddress, DmBaseAddress: ariane_soc::DebugBase, NrPMPEntries: unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {16{64'h0}}, + PMPAddrRstVal: {16{64'h0}}, + PMPEntryReadOnly: 16'd0, NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, // idempotent region NrNonIdempotentRules: unsigned'(1),