From 7808dbdab77f4496a968cc8ebb40938168c6a17c Mon Sep 17 00:00:00 2001
From: jquevremont <jerome.quevremont@thalesgroup.com>
Date: Sat, 27 Jan 2024 19:36:11 +0100
Subject: [PATCH] Improved index, replaced failing CV32A60AX CSR details with
 placeholder

Signed-off-by: jquevremont <jerome.quevremont@thalesgroup.com>
---
 docs/01_cva6_user/CSR_CV32A60AX.rst | 26 +++++++++++++++++-
 docs/01_cva6_user/index.rst         | 42 +++++++++++++++--------------
 2 files changed, 47 insertions(+), 21 deletions(-)

diff --git a/docs/01_cva6_user/CSR_CV32A60AX.rst b/docs/01_cva6_user/CSR_CV32A60AX.rst
index 1001e92157..259ade0ffd 100644
--- a/docs/01_cva6_user/CSR_CV32A60AX.rst
+++ b/docs/01_cva6_user/CSR_CV32A60AX.rst
@@ -1 +1,25 @@
-.. include:: ../csr-from-ip-xact/cv32a60ax/csr.rst
\ No newline at end of file
+..
+   Copyright (c) 2023 OpenHW Group
+   Copyright (c) 2023 Thales DIS design services SAS
+
+   SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+.. Level 1
+   =======
+
+   Level 2
+   -------
+
+   Level 3
+   ~~~~~~~
+
+   Level 4
+   ^^^^^^^
+
+.. _CSR_CV32A60AX:
+
+
+CV32A60AX Control Status Registers
+==================================
+
+*This chapter is not yet available.*
diff --git a/docs/01_cva6_user/index.rst b/docs/01_cva6_user/index.rst
index 6d21158197..255fa8544b 100644
--- a/docs/01_cva6_user/index.rst
+++ b/docs/01_cva6_user/index.rst
@@ -18,7 +18,6 @@
 
 CVA6 User Manual
 ================
-Editor: **Jerome Quevremont**
 
 .. toctree::
    :maxdepth: 2
@@ -33,27 +32,30 @@ Editor: **Jerome Quevremont**
    Traps_Interrupts_Exceptions
    Compiler_Command_Lines
    RISCV_Instructions
-   RISCV_Instructions_RV32I
-   RISCV_Instructions_RV32M
-   RISCV_Instructions_RV32A
-   RISCV_Instructions_RV32C
-   RISCV_Instructions_RVZba
-   RISCV_Instructions_RVZbb
-   RISCV_Instructions_RVZbc
-   RISCV_Instructions_RVZbs
-   RISCV_Instructions_RV32ZCb
-   RISCV_Instructions_RVZicsr
-   RISCV_Instructions_RVZifencei
-   RISCV_Instructions_RVZicond
-   CSR_CV32A60X_list
-   CSR_CV32A60X
-   CSR_CV32A60AX
-   CV64A6_Control_Status_Registers
+   RV32I <RISCV_Instructions_RV32I>
+   RV32M <RISCV_Instructions_RV32M>
+   RV32A <RISCV_Instructions_RV32A>
+   RV32C <RISCV_Instructions_RV32C>
+   RV32Zcb <RISCV_Instructions_RV32ZCb>
+   RVZba <RISCV_Instructions_RVZba>
+   RVZbb <RISCV_Instructions_RVZbb>
+   RVZbc <RISCV_Instructions_RVZbc>
+   RVZbs <RISCV_Instructions_RVZbs>
+   RVZicsr <RISCV_Instructions_RVZicsr>
+   RVZifencei <RISCV_Instructions_RVZifencei>
+   RVZicond <RISCV_Instructions_RVZicond>
+   CV32A60X CSR List <CSR_CV32A60X_list>
+   CV32A60X CSR Details <CSR_CV32A60X>
+   CV32A60AX CSR List <CSR_CV32A60AX_list>
+   CV32A60AX CSR Details <CSR_CV32A60AX>
+   CV64A6 CSR <CV64A6_Control_Status_Registers>
    CSR_Cache_Control
-   CSR_Performance_Counters
+   CSR Performance Counters <CSR_Performance_Counters>
    Parameters_Configuration
    Interfaces
+   AXI Bus Interface <AXI_Interface>
+   CV-X-IF Interface <CVX_Interface_Coprocessor>
    Core_Integration
-   CVX_Interface_Coprocessor
-   AXI_Interface
+
+