From 741e82133d8e7e646869f78bf11969629cb474a3 Mon Sep 17 00:00:00 2001 From: Nils Wistoff Date: Sun, 6 Feb 2022 11:17:21 +0100 Subject: [PATCH] ariane_testharness/ariane_xilinx: Fix AXI ID width (#813) - Fix the AXI ID width for the CLINT (previously `4`, now `5`) - Parametrise the CLINT's AXI types - Deprecate `axi_[master|slave]_connect` and move to AXI assign macros, as they allow arbitrary AXI types Signed-off-by: Nils Wistoff --- Bender.yml | 4 -- CHANGELOG.md | 12 ++-- Flist.ariane | 4 -- Makefile | 4 -- common/local/util/axi_master_connect.sv | 68 -------------------- common/local/util/axi_master_connect_rev.sv | 68 -------------------- common/local/util/axi_slave_connect.sv | 70 --------------------- common/local/util/axi_slave_connect_rev.sv | 67 -------------------- corev_apu/clint/axi_lite_interface.sv | 8 ++- corev_apu/clint/clint.sv | 12 ++-- corev_apu/fpga/src/ariane_xilinx.sv | 28 ++++++--- corev_apu/tb/ariane_testharness.sv | 45 ++++++------- 12 files changed, 58 insertions(+), 332 deletions(-) delete mode 100644 common/local/util/axi_master_connect.sv delete mode 100644 common/local/util/axi_master_connect_rev.sv delete mode 100644 common/local/util/axi_slave_connect.sv delete mode 100644 common/local/util/axi_slave_connect_rev.sv diff --git a/Bender.yml b/Bender.yml index 461b141943..b1cc22fa09 100644 --- a/Bender.yml +++ b/Bender.yml @@ -153,10 +153,6 @@ sources: - common/submodules/common_cells/src/stream_demux.sv - common/submodules/common_cells/src/stream_arbiter.sv - common/submodules/common_cells/src/stream_arbiter_flushable.sv - - common/local/util/axi_master_connect.sv - - common/local/util/axi_slave_connect.sv - - common/local/util/axi_master_connect_rev.sv - - common/local/util/axi_slave_connect_rev.sv - corev_apu/axi/src/axi_cut.sv - corev_apu/axi/src/axi_join.sv - corev_apu/axi/src/axi_delayer.sv diff --git a/CHANGELOG.md b/CHANGELOG.md index 41711b5c54..3046b001e7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -70,10 +70,6 @@ src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_s src/common_cells/src/stream_mux.sv ==> common/submodules/common_cells/src/stream_mux.sv src/common_cells/src/stream_demux.sv ==> common/submodules/common_cells/src/stream_demux.sv src/common_cells/src/exp_backoff.sv ==> common/submodules/common_cells/src/exp_backoff.sv - src/util/axi_master_connect.sv ==> common/local/util/axi_master_connect.sv - src/util/axi_slave_connect.sv ==> common/local/util/axi_slave_connect.sv - src/util/axi_master_connect_rev.sv ==> common/local/util/axi_master_connect_rev.sv - src/util/axi_slave_connect_rev.sv ==> common/local/util/axi_slave_connect_rev.sv src/axi/src/axi_cut.sv ==> corev_apu/axi/src/axi_cut.sv src/axi/src/axi_join.sv ==> corev_apu/axi/src/axi_join.sv src/axi/src/axi_delayer.sv ==> corev_apu/axi/src/axi_delayer.sv @@ -107,6 +103,14 @@ src/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv ==> core/fpu/src/fpu_div_s tb/common/SimJTAG.sv ==> corev_apu/tb/common/SimJTAG.sv ``` +#### Removed standalone components +``` +src/util/axi_master_connect.sv +src/util/axi_slave_connect.sv +src/util/axi_master_connect_rev.sv +src/util/axi_slave_connect_rev.sv +``` + ### 4.2.0 - 2019-06-04 ### Added diff --git a/Flist.ariane b/Flist.ariane index e1249fc865..7ca8b5de72 100644 --- a/Flist.ariane +++ b/Flist.ariane @@ -67,10 +67,6 @@ include/instr_tracer_pkg.sv src/util/instr_tracer_if.sv src/util/instr_tracer.sv src/util/sram.sv -src/util/axi_master_connect.sv -src/util/axi_master_connect_rev.sv -src/util/axi_slave_connect.sv -src/util/axi_slave_connect_rev.sv src/fpga-support/rtl/SyncSpRamBeNx64.sv src/dromajo_ram.sv src/axi_mem_if/src/axi2mem.sv diff --git a/Makefile b/Makefile index 8c3eaa12a3..172af0d203 100644 --- a/Makefile +++ b/Makefile @@ -196,10 +196,6 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv)) common/submodules/common_cells/src/exp_backoff.sv \ common/submodules/common_cells/src/addr_decode.sv \ common/submodules/common_cells/src/stream_register.sv \ - common/local/util/axi_master_connect.sv \ - common/local/util/axi_slave_connect.sv \ - common/local/util/axi_master_connect_rev.sv \ - common/local/util/axi_slave_connect_rev.sv \ corev_apu/axi/src/axi_cut.sv \ corev_apu/axi/src/axi_join.sv \ corev_apu/axi/src/axi_delayer.sv \ diff --git a/common/local/util/axi_master_connect.sv b/common/local/util/axi_master_connect.sv deleted file mode 100644 index 9448f2f35e..0000000000 --- a/common/local/util/axi_master_connect.sv +++ /dev/null @@ -1,68 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Description: Connects SV AXI interface to structs used by Ariane -// Author: Florian Zaruba - -module axi_master_connect ( - input ariane_axi::req_t axi_req_i, - output ariane_axi::resp_t axi_resp_o, - AXI_BUS.Master master -); - - assign master.aw_id = axi_req_i.aw.id; - assign master.aw_addr = axi_req_i.aw.addr; - assign master.aw_len = axi_req_i.aw.len; - assign master.aw_size = axi_req_i.aw.size; - assign master.aw_burst = axi_req_i.aw.burst; - assign master.aw_lock = axi_req_i.aw.lock; - assign master.aw_cache = axi_req_i.aw.cache; - assign master.aw_prot = axi_req_i.aw.prot; - assign master.aw_qos = axi_req_i.aw.qos; - assign master.aw_atop = axi_req_i.aw.atop; - assign master.aw_region = axi_req_i.aw.region; - assign master.aw_user = '0; - assign master.aw_valid = axi_req_i.aw_valid; - assign axi_resp_o.aw_ready = master.aw_ready; - - assign master.w_data = axi_req_i.w.data; - assign master.w_strb = axi_req_i.w.strb; - assign master.w_last = axi_req_i.w.last; - assign master.w_user = '0; - assign master.w_valid = axi_req_i.w_valid; - assign axi_resp_o.w_ready = master.w_ready; - - assign axi_resp_o.b.id = master.b_id; - assign axi_resp_o.b.resp = master.b_resp; - assign axi_resp_o.b_valid = master.b_valid; - assign master.b_ready = axi_req_i.b_ready; - - assign master.ar_id = axi_req_i.ar.id; - assign master.ar_addr = axi_req_i.ar.addr; - assign master.ar_len = axi_req_i.ar.len; - assign master.ar_size = axi_req_i.ar.size; - assign master.ar_burst = axi_req_i.ar.burst; - assign master.ar_lock = axi_req_i.ar.lock; - assign master.ar_cache = axi_req_i.ar.cache; - assign master.ar_prot = axi_req_i.ar.prot; - assign master.ar_qos = axi_req_i.ar.qos; - assign master.ar_region = axi_req_i.ar.region; - assign master.ar_user = '0; - assign master.ar_valid = axi_req_i.ar_valid; - assign axi_resp_o.ar_ready = master.ar_ready; - - assign axi_resp_o.r.id = master.r_id; - assign axi_resp_o.r.data = master.r_data; - assign axi_resp_o.r.resp = master.r_resp; - assign axi_resp_o.r.last = master.r_last; - assign axi_resp_o.r_valid = master.r_valid; - assign master.r_ready = axi_req_i.r_ready; - -endmodule diff --git a/common/local/util/axi_master_connect_rev.sv b/common/local/util/axi_master_connect_rev.sv deleted file mode 100644 index 620b303b54..0000000000 --- a/common/local/util/axi_master_connect_rev.sv +++ /dev/null @@ -1,68 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Description: Connects SV AXI interface to structs used by Ariane -// Author: Florian Zaruba - -module axi_master_connect_rev ( - output ariane_axi::req_t axi_req_o, - input ariane_axi::resp_t axi_resp_i, - AXI_BUS.Slave master -); - - assign axi_req_o.aw.atop = '0; // not supported at the moment - assign axi_req_o.aw.id = master.aw_id; - assign axi_req_o.aw.addr = master.aw_addr; - assign axi_req_o.aw.len = master.aw_len; - assign axi_req_o.aw.size = master.aw_size; - assign axi_req_o.aw.burst = master.aw_burst; - assign axi_req_o.aw.lock = master.aw_lock; - assign axi_req_o.aw.cache = master.aw_cache; - assign axi_req_o.aw.prot = master.aw_prot; - assign axi_req_o.aw.qos = master.aw_qos; - assign axi_req_o.aw.region = master.aw_region; - // assign = master.aw_user; - assign axi_req_o.aw_valid = master.aw_valid; - assign master.aw_ready = axi_resp_i.aw_ready; - - assign axi_req_o.w.data = master.w_data; - assign axi_req_o.w.strb = master.w_strb; - assign axi_req_o.w.last = master.w_last; - // assign = master.w_user; - assign axi_req_o.w_valid = master.w_valid; - assign master.w_ready = axi_resp_i.w_ready; - - assign master.b_id = axi_resp_i.b.id; - assign master.b_resp = axi_resp_i.b.resp; - assign master.b_valid = axi_resp_i.b_valid; - assign axi_req_o.b_ready = master.b_ready; - - assign axi_req_o.ar.id = master.ar_id; - assign axi_req_o.ar.addr = master.ar_addr; - assign axi_req_o.ar.len = master.ar_len; - assign axi_req_o.ar.size = master.ar_size; - assign axi_req_o.ar.burst = master.ar_burst; - assign axi_req_o.ar.lock = master.ar_lock; - assign axi_req_o.ar.cache = master.ar_cache; - assign axi_req_o.ar.prot = master.ar_prot; - assign axi_req_o.ar.qos = master.ar_qos; - assign axi_req_o.ar.region = master.ar_region; - // assign = master.ar_user; - assign axi_req_o.ar_valid = master.ar_valid; - assign master.ar_ready = axi_resp_i.ar_ready; - - assign master.r_id = axi_resp_i.r.id; - assign master.r_data = axi_resp_i.r.data; - assign master.r_resp = axi_resp_i.r.resp; - assign master.r_last = axi_resp_i.r.last; - assign master.r_valid = axi_resp_i.r_valid; - assign axi_req_o.r_ready = master.r_ready; - -endmodule diff --git a/common/local/util/axi_slave_connect.sv b/common/local/util/axi_slave_connect.sv deleted file mode 100644 index ce5dedea5c..0000000000 --- a/common/local/util/axi_slave_connect.sv +++ /dev/null @@ -1,70 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Description: Connects SV AXI interface to structs used by Ariane -// Author: Florian Zaruba - -module axi_slave_connect ( - output ariane_axi::req_t axi_req_o, - input ariane_axi::resp_t axi_resp_i, - AXI_BUS.Slave slave -); - - assign axi_req_o.aw.id = slave.aw_id; - assign axi_req_o.aw.addr = slave.aw_addr; - assign axi_req_o.aw.len = slave.aw_len; - assign axi_req_o.aw.size = slave.aw_size; - assign axi_req_o.aw.burst = slave.aw_burst; - assign axi_req_o.aw.lock = slave.aw_lock; - assign axi_req_o.aw.cache = slave.aw_cache; - assign axi_req_o.aw.prot = slave.aw_prot; - assign axi_req_o.aw.qos = slave.aw_qos; - assign axi_req_o.aw.atop = slave.aw_atop; - assign axi_req_o.aw.region = slave.aw_region; - // assign = slave.aw_user; - assign axi_req_o.aw_valid = slave.aw_valid; - assign slave.aw_ready = axi_resp_i.aw_ready; - - assign axi_req_o.w.data = slave.w_data; - assign axi_req_o.w.strb = slave.w_strb; - assign axi_req_o.w.last = slave.w_last; - // assign = slave.w_user; - assign axi_req_o.w_valid = slave.w_valid; - assign slave.w_ready = axi_resp_i.w_ready; - - assign slave.b_id = axi_resp_i.b.id; - assign slave.b_resp = axi_resp_i.b.resp; - assign slave.b_valid = axi_resp_i.b_valid; - assign slave.b_user = 1'b0; - assign axi_req_o.b_ready = slave.b_ready; - - assign axi_req_o.ar.id = slave.ar_id; - assign axi_req_o.ar.addr = slave.ar_addr; - assign axi_req_o.ar.len = slave.ar_len; - assign axi_req_o.ar.size = slave.ar_size; - assign axi_req_o.ar.burst = slave.ar_burst; - assign axi_req_o.ar.lock = slave.ar_lock; - assign axi_req_o.ar.cache = slave.ar_cache; - assign axi_req_o.ar.prot = slave.ar_prot; - assign axi_req_o.ar.qos = slave.ar_qos; - assign axi_req_o.ar.region = slave.ar_region; - // assign = slave.ar_user; - assign axi_req_o.ar_valid = slave.ar_valid; - assign slave.ar_ready = axi_resp_i.ar_ready; - - assign slave.r_id = axi_resp_i.r.id; - assign slave.r_data = axi_resp_i.r.data; - assign slave.r_resp = axi_resp_i.r.resp; - assign slave.r_last = axi_resp_i.r.last; - assign slave.r_valid = axi_resp_i.r_valid; - assign slave.r_user = 1'b0; - assign axi_req_o.r_ready = slave.r_ready; - -endmodule diff --git a/common/local/util/axi_slave_connect_rev.sv b/common/local/util/axi_slave_connect_rev.sv deleted file mode 100644 index 5dbaaabf34..0000000000 --- a/common/local/util/axi_slave_connect_rev.sv +++ /dev/null @@ -1,67 +0,0 @@ -// Copyright 2018 ETH Zurich and University of Bologna. -// Copyright and related rights are licensed under the Solderpad Hardware -// License, Version 0.51 (the "License"); you may not use this file except in -// compliance with the License. You may obtain a copy of the License at -// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law -// or agreed to in writing, software, hardware and materials distributed under -// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR -// CONDITIONS OF ANY KIND, either express or implied. See the License for the -// specific language governing permissions and limitations under the License. -// -// Description: Connects SV AXI interface to structs used by Ariane -// Author: Florian Zaruba - -module axi_slave_connect_rev ( - input ariane_axi::req_t axi_req_i, - output ariane_axi::resp_t axi_resp_o, - AXI_BUS.Master slave -); - - assign slave.aw_id = axi_req_i.aw.id; - assign slave.aw_addr = axi_req_i.aw.addr; - assign slave.aw_len = axi_req_i.aw.len; - assign slave.aw_size = axi_req_i.aw.size; - assign slave.aw_burst = axi_req_i.aw.burst; - assign slave.aw_lock = axi_req_i.aw.lock; - assign slave.aw_cache = axi_req_i.aw.cache; - assign slave.aw_prot = axi_req_i.aw.prot; - assign slave.aw_qos = axi_req_i.aw.qos; - assign slave.aw_region = axi_req_i.aw.region; - assign slave.aw_user = '0; - assign slave.aw_valid = axi_req_i.aw_valid; - assign axi_resp_o.aw_ready = slave.aw_ready; - - assign slave.w_data = axi_req_i.w.data; - assign slave.w_strb = axi_req_i.w.strb; - assign slave.w_last = axi_req_i.w.last; - assign slave.w_user = '0; - assign slave.w_valid = axi_req_i.w_valid; - assign axi_resp_o.w_ready = slave.w_ready; - - assign axi_resp_o.b.id = slave.b_id; - assign axi_resp_o.b.resp = slave.b_resp; - assign axi_resp_o.b_valid = slave.b_valid; - assign slave.b_ready = axi_req_i.b_ready; - - assign slave.ar_id = axi_req_i.ar.id; - assign slave.ar_addr = axi_req_i.ar.addr; - assign slave.ar_len = axi_req_i.ar.len; - assign slave.ar_size = axi_req_i.ar.size; - assign slave.ar_burst = axi_req_i.ar.burst; - assign slave.ar_lock = axi_req_i.ar.lock; - assign slave.ar_cache = axi_req_i.ar.cache; - assign slave.ar_prot = axi_req_i.ar.prot; - assign slave.ar_qos = axi_req_i.ar.qos; - assign slave.ar_region = axi_req_i.ar.region; - assign slave.ar_user = '0; - assign slave.ar_valid = axi_req_i.ar_valid; - assign axi_resp_o.ar_ready = slave.ar_ready; - - assign axi_resp_o.r.id = slave.r_id; - assign axi_resp_o.r.data = slave.r_data; - assign axi_resp_o.r.resp = slave.r_resp; - assign axi_resp_o.r.last = slave.r_last; - assign axi_resp_o.r_valid = slave.r_valid; - assign slave.r_ready = axi_req_i.r_ready; - -endmodule diff --git a/corev_apu/clint/axi_lite_interface.sv b/corev_apu/clint/axi_lite_interface.sv index cdbcd53a68..c431dc02a0 100644 --- a/corev_apu/clint/axi_lite_interface.sv +++ b/corev_apu/clint/axi_lite_interface.sv @@ -16,13 +16,15 @@ module axi_lite_interface #( parameter int unsigned AXI_ADDR_WIDTH = 64, parameter int unsigned AXI_DATA_WIDTH = 64, - parameter int unsigned AXI_ID_WIDTH = 10 + parameter int unsigned AXI_ID_WIDTH = 10, + parameter type axi_req_t = ariane_axi::req_t, + parameter type axi_resp_t = ariane_axi::resp_t ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low - input ariane_axi::req_t axi_req_i, - output ariane_axi::resp_t axi_resp_o, + input axi_req_t axi_req_i, + output axi_resp_t axi_resp_o, output logic [AXI_ADDR_WIDTH-1:0] address_o, output logic en_o, // transaction is valid diff --git a/corev_apu/clint/clint.sv b/corev_apu/clint/clint.sv index d1b8112e5d..e76f96d8f9 100644 --- a/corev_apu/clint/clint.sv +++ b/corev_apu/clint/clint.sv @@ -20,13 +20,15 @@ module clint #( parameter int unsigned AXI_ADDR_WIDTH = 64, parameter int unsigned AXI_DATA_WIDTH = 64, parameter int unsigned AXI_ID_WIDTH = 10, - parameter int unsigned NR_CORES = 1 // Number of cores therefore also the number of timecmp registers and timer interrupts + parameter int unsigned NR_CORES = 1, // Number of cores therefore also the number of timecmp registers and timer interrupts + parameter type axi_req_t = ariane_axi::req_t, + parameter type axi_resp_t = ariane_axi::resp_t ) ( input logic clk_i, // Clock input logic rst_ni, // Asynchronous reset active low input logic testmode_i, - input ariane_axi::req_t axi_req_i, - output ariane_axi::resp_t axi_resp_o, + input axi_req_t axi_req_i, + output axi_resp_t axi_resp_o, input logic rtc_i, // Real-time clock in (usually 32.768 kHz) output logic [NR_CORES-1:0] timer_irq_o, // Timer interrupts output logic [NR_CORES-1:0] ipi_o // software interrupt (a.k.a inter-process-interrupt) @@ -63,7 +65,9 @@ module clint #( axi_lite_interface #( .AXI_ADDR_WIDTH ( AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( AXI_ID_WIDTH ) + .AXI_ID_WIDTH ( AXI_ID_WIDTH ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ) ) axi_lite_interface_i ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/corev_apu/fpga/src/ariane_xilinx.sv b/corev_apu/fpga/src/ariane_xilinx.sv index a8a43150c0..fef509ab2a 100644 --- a/corev_apu/fpga/src/ariane_xilinx.sv +++ b/corev_apu/fpga/src/ariane_xilinx.sv @@ -161,6 +161,13 @@ localparam AxiIdWidthMaster = 4; localparam AxiIdWidthSlaves = AxiIdWidthMaster + $clog2(NBSlave); // 5 localparam AxiUserWidth = 1; +`AXI_TYPEDEF_ALL(axi_slave, + logic [ AxiAddrWidth-1:0], + logic [AxiIdWidthSlaves-1:0], + logic [ AxiDataWidth-1:0], + logic [(AxiDataWidth/8)-1:0], + logic [ AxiUserWidth-1:0]) + AXI_BUS #( .AXI_ADDR_WIDTH ( AxiAddrWidth ), .AXI_DATA_WIDTH ( AxiDataWidth ), @@ -673,11 +680,8 @@ if (riscv::XLEN==32 ) begin .m_axi_rready(slave[1].r_ready) ); end else begin - axi_master_connect i_dm_axi_master_connect ( - .axi_req_i(dm_axi_m_req), - .axi_resp_o(dm_axi_m_resp), - .master(slave[1]) - ); + `AXI_ASSIGN_FROM_REQ(slave[1], dm_axi_m_req) + `AXI_ASSIGN_TO_RESP(dm_axi_m_resp, slave[1]) end @@ -702,7 +706,8 @@ ariane #( .axi_resp_i ( axi_ariane_resp ) ); -axi_master_connect i_axi_master_connect_ariane (.axi_req_i(axi_ariane_req), .axi_resp_o(axi_ariane_resp), .master(slave[0])); +`AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req) +`AXI_ASSIGN_TO_RESP(axi_ariane_resp, slave[0]) // --------------- // CLINT @@ -716,14 +721,16 @@ always_ff @(posedge clk or negedge ndmreset_n) begin end end -ariane_axi::req_t axi_clint_req; -ariane_axi::resp_t axi_clint_resp; +axi_slave_req_t axi_clint_req; +axi_slave_resp_t axi_clint_resp; clint #( .AXI_ADDR_WIDTH ( AxiAddrWidth ), .AXI_DATA_WIDTH ( AxiDataWidth ), .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .NR_CORES ( 1 ) + .NR_CORES ( 1 ), + .axi_req_t ( axi_slave_req_t ), + .axi_resp_t ( axi_slave_resp_t ) ) i_clint ( .clk_i ( clk ), .rst_ni ( ndmreset_n ), @@ -735,7 +742,8 @@ clint #( .ipi_o ( ipi ) ); -axi_slave_connect i_axi_slave_connect_clint (.axi_req_o(axi_clint_req), .axi_resp_i(axi_clint_resp), .slave(master[ariane_soc::CLINT])); +`AXI_ASSIGN_TO_REQ(axi_clint_req, master[ariane_soc::CLINT]) +`AXI_ASSIGN_FROM_RESP(master[ariane_soc::CLINT], axi_clint_resp) // --------------- // ROM diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index 7ea64508e8..69704789e0 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -276,11 +276,8 @@ module ariane_testharness #( .data_i ( dm_slave_rdata ) ); - axi_master_connect i_dm_axi_master_connect ( - .axi_req_i(dm_axi_m_req), - .axi_resp_o(dm_axi_m_resp), - .master(slave[1]) - ); + `AXI_ASSIGN_FROM_REQ(slave[1], dm_axi_m_req) + `AXI_ASSIGN_TO_RESP(dm_axi_m_resp, slave[1]) axi_adapter #( .DATA_WIDTH ( AXI_DATA_WIDTH ), @@ -354,14 +351,14 @@ module ariane_testharness #( // GPIO not implemented, adding an error slave here - ariane_axi_soc::req_t gpio_req; - ariane_axi_soc::resp_t gpio_resp; + ariane_axi_soc::req_slv_t gpio_req; + ariane_axi_soc::resp_slv_t gpio_resp; `AXI_ASSIGN_TO_REQ(gpio_req, master[ariane_soc::GPIO]) `AXI_ASSIGN_FROM_RESP(master[ariane_soc::GPIO], gpio_resp) axi_err_slv #( - .AxiIdWidth ( ariane_soc::IdWidthSlave ), - .req_t ( ariane_axi_soc::req_t ), - .resp_t ( ariane_axi_soc::resp_t ) + .AxiIdWidth ( ariane_soc::IdWidthSlave ), + .req_t ( ariane_axi_soc::req_slv_t ), + .resp_t ( ariane_axi_soc::resp_slv_t ) ) i_gpio_err_slv ( .clk_i ( clk_i ), .rst_ni ( ndmreset_n ), @@ -514,14 +511,16 @@ module ariane_testharness #( logic ipi; logic timer_irq; - ariane_axi_soc::req_t axi_clint_req; - ariane_axi_soc::resp_t axi_clint_resp; + ariane_axi_soc::req_slv_t axi_clint_req; + ariane_axi_soc::resp_slv_t axi_clint_resp; clint #( - .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), - .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), - .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), - .NR_CORES ( 1 ) + .AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ), + .AXI_DATA_WIDTH ( AXI_DATA_WIDTH ), + .AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ), + .NR_CORES ( 1 ), + .axi_req_t ( ariane_axi_soc::req_slv_t ), + .axi_resp_t ( ariane_axi_soc::resp_slv_t ) ) i_clint ( .clk_i ( clk_i ), .rst_ni ( ndmreset_n ), @@ -533,11 +532,8 @@ module ariane_testharness #( .ipi_o ( ipi ) ); - axi_slave_connect i_axi_slave_connect_clint ( - .axi_req_o(axi_clint_req), - .axi_resp_i(axi_clint_resp), - .slave(master[ariane_soc::CLINT]) - ); + `AXI_ASSIGN_TO_REQ(axi_clint_req, master[ariane_soc::CLINT]) + `AXI_ASSIGN_FROM_RESP(master[ariane_soc::CLINT], axi_clint_resp) // --------------- // Peripherals @@ -621,11 +617,8 @@ module ariane_testharness #( .axi_resp_i ( axi_ariane_resp ) ); - axi_master_connect i_axi_master_connect_ariane ( - .axi_req_i(axi_ariane_req), - .axi_resp_o(axi_ariane_resp), - .master(slave[0]) - ); + `AXI_ASSIGN_FROM_REQ(slave[0], axi_ariane_req) + `AXI_ASSIGN_TO_RESP(axi_ariane_resp, slave[0]) // ------------- // Simulation Helper Functions