From 71f57a38c24b06ddb8278197abc731977c5c8b0c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andr=C3=A9=20Sintzoff?=
 <61976467+ASintzoff@users.noreply.github.com>
Date: Wed, 21 Feb 2024 18:16:35 +0100
Subject: [PATCH] csr_regfile.sv: no MENVCFG[H], MCOUNTEREN when no User mode
 (fix #1843) (#1861)

---
 .gitlab-ci/expected_synth.yml |  5 ++---
 core/csr_regfile.sv           | 16 +++++++++++-----
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml
index 21cf15d725..59cfbcb8b9 100644
--- a/.gitlab-ci/expected_synth.yml
+++ b/.gitlab-ci/expected_synth.yml
@@ -1,5 +1,4 @@
 cv32a6_embedded:
-  gates: 110519
+  gates: 110087
 cv32a65x:
-  gates: 110519
-
+  gates: 109501
diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv
index dee9faf94f..416b28c4f6 100644
--- a/core/csr_regfile.sv
+++ b/core/csr_regfile.sv
@@ -345,9 +345,12 @@ module csr_regfile
         riscv::CSR_MCAUSE: csr_rdata = mcause_q;
         riscv::CSR_MTVAL: csr_rdata = mtval_q;
         riscv::CSR_MIP: csr_rdata = mip_q;
-        riscv::CSR_MENVCFG: csr_rdata = '0 | fiom_q;
+        riscv::CSR_MENVCFG: begin
+          if (CVA6Cfg.RVU) csr_rdata = '0 | fiom_q;
+          else read_access_exception = 1'b1;
+        end
         riscv::CSR_MENVCFGH: begin
-          if (riscv::XLEN == 32) csr_rdata = '0;
+          if (CVA6Cfg.RVU && riscv::XLEN == 32) csr_rdata = '0;
           else read_access_exception = 1'b1;
         end
         riscv::CSR_MVENDORID: csr_rdata = OPENHWGROUP_MVENDORID;
@@ -884,7 +887,10 @@ module csr_regfile
           // alignment constraint of 64 * 4 bytes
           if (csr_wdata[0]) mtvec_d = {csr_wdata[riscv::XLEN-1:8], 7'b0, csr_wdata[0]};
         end
-        riscv::CSR_MCOUNTEREN: mcounteren_d = {{riscv::XLEN - 32{1'b0}}, csr_wdata[31:0]};
+        riscv::CSR_MCOUNTEREN: begin
+          if (CVA6Cfg.RVU) mcounteren_d = {{riscv::XLEN - 32{1'b0}}, csr_wdata[31:0]};
+          else update_access_exception = 1'b1;
+        end
 
         riscv::CSR_MSCRATCH: mscratch_d = csr_wdata;
         riscv::CSR_MEPC: mepc_d = {csr_wdata[riscv::XLEN-1:1], 1'b0};
@@ -897,9 +903,9 @@ module csr_regfile
           mask  = riscv::MIP_SSIP | riscv::MIP_STIP | riscv::MIP_SEIP;
           mip_d = (mip_q & ~mask) | (csr_wdata & mask);
         end
-        riscv::CSR_MENVCFG: if (CVA6Cfg.RVS) fiom_d = csr_wdata[0];
+        riscv::CSR_MENVCFG: if (CVA6Cfg.RVU) fiom_d = csr_wdata[0];
         riscv::CSR_MENVCFGH: begin
-          if (riscv::XLEN != 32) update_access_exception = 1'b1;
+          if (!CVA6Cfg.RVU || riscv::XLEN != 32) update_access_exception = 1'b1;
         end
         riscv::CSR_MCOUNTINHIBIT:
         if (PERF_COUNTER_EN) mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]};