From 6e79e20cc64451c5414a742aa6d697ddcb465b56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Qu=C3=A9vremont?= Date: Thu, 21 Dec 2023 17:23:14 +0100 Subject: [PATCH] UM: Part number + reshuffled Zb* RV32/RV64 instructions (#1733) --- docs/01_cva6_user/AXI_Interface.rst | 2 +- .../01_cva6_user/CSR_Performance_Counters.rst | 4 +- .../CVX_Interface_Coprocessor.rst | 2 +- docs/01_cva6_user/Interfaces.rst | 8 +- docs/01_cva6_user/Introduction.rst | 8 +- docs/01_cva6_user/Programmer_View.rst | 98 +++++++-------- docs/01_cva6_user/RISCV_Instructions.rst | 4 + .../01_cva6_user/RISCV_Instructions_RV32A.rst | 4 +- .../01_cva6_user/RISCV_Instructions_RV32C.rst | 2 +- .../01_cva6_user/RISCV_Instructions_RV32I.rst | 2 +- .../01_cva6_user/RISCV_Instructions_RV32M.rst | 2 +- .../RISCV_Instructions_RV32ZCb.rst | 2 +- .../01_cva6_user/RISCV_Instructions_RVZba.rst | 95 ++++++++++----- .../01_cva6_user/RISCV_Instructions_RVZbb.rst | 114 ++++++++++++++---- .../01_cva6_user/RISCV_Instructions_RVZbc.rst | 36 +++++- .../01_cva6_user/RISCV_Instructions_RVZbs.rst | 36 +++++- .../RISCV_Instructions_RVZicond.rst | 4 +- .../cva6_requirements_specification.rst | 42 +++---- 18 files changed, 320 insertions(+), 145 deletions(-) diff --git a/docs/01_cva6_user/AXI_Interface.rst b/docs/01_cva6_user/AXI_Interface.rst index 9c9fb00eea..90fde70a43 100644 --- a/docs/01_cva6_user/AXI_Interface.rst +++ b/docs/01_cva6_user/AXI_Interface.rst @@ -24,8 +24,8 @@ In order to understand how the AXI memory interface behaves in CVA6, it is neces :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "AXI included" "CV32A60X", "AXI included" - "CV32A60MX", "AXI included" About the AXI4 protocol ~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/01_cva6_user/CSR_Performance_Counters.rst b/docs/01_cva6_user/CSR_Performance_Counters.rst index 59d570005e..e3032700c2 100644 --- a/docs/01_cva6_user/CSR_Performance_Counters.rst +++ b/docs/01_cva6_user/CSR_Performance_Counters.rst @@ -25,8 +25,8 @@ :align: left :header: "Configuration", "Implementation" - "CV32A60X", "Performance counters included" - "CV32A60MX", "No performance counters" + "CV32A60AX", "Performance counters included" + "CV32A60X", "No performance counters" CSR performance counters control ================================ diff --git a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst index a0f9d1148e..bd529a2098 100644 --- a/docs/01_cva6_user/CVX_Interface_Coprocessor.rst +++ b/docs/01_cva6_user/CVX_Interface_Coprocessor.rst @@ -31,8 +31,8 @@ with external coprocessors. :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "CV-X-IF included" "CV32A60X", "CV-X-IF included" - "CV32A60MX", "CV-X-IF included" CV-X-IF interface specification diff --git a/docs/01_cva6_user/Interfaces.rst b/docs/01_cva6_user/Interfaces.rst index f17b5fdd75..08698dcd8c 100644 --- a/docs/01_cva6_user/Interfaces.rst +++ b/docs/01_cva6_user/Interfaces.rst @@ -32,8 +32,8 @@ The AXI interface is described in a separate chapter. :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "AXI implemented" "CV32A60X", "AXI implemented" - "CV32A60MX", "AXI implemented" Debug Interface --------------- @@ -50,8 +50,8 @@ Debug Interface :align: left :header: "Configuration", "Implementation" - "CV32A60X", "Debug interface implemented" - "CV32A60MX", "No debug interface" + "CV32A60AX", "Debug interface implemented" + "CV32A60X", "No debug interface" Interrupt Interface ------------------- @@ -75,5 +75,5 @@ For more information, refer to OpenPiton documents. :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "No TRI interface" "CV32A60X", "No TRI interface" - "CV32A60MX", "No TRI interface" diff --git a/docs/01_cva6_user/Introduction.rst b/docs/01_cva6_user/Introduction.rst index 9e4bae1168..16844787cf 100644 --- a/docs/01_cva6_user/Introduction.rst +++ b/docs/01_cva6_user/Introduction.rst @@ -100,11 +100,11 @@ As of today, two configurations are being verified and addressed in this documen :align: left :header: "Configuration", "Short description", "Target", "Privilege levels", "Supported RISC-V ISA", "CV-X-IF" - "**CV32A60X**", "32-bit **application** core", "ASIC", "Machine, Supervisor, User", "RV32IMACZicsr_Zifencei_Zicount_Zba_Zbb_Zbc_Zbs_Zcb_Zicond", "Included" - "**CV32A60MX**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included" + "**CV32A60AX**", "32-bit **application** core", "ASIC", "Machine, Supervisor, User", "RV32IMACZicsr_Zifencei_Zicount_Zba_Zbb_Zbc_Zbs_Zcb_Zicond", "Included" + "**CV32A60X**", "32-bit **embedded** core", "ASIC", "Machine only", "RV32IMCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs_Zcb", "Included" -CV32A60MX is an interim part number until the team can decide if this configuration is single- or dual-issue. -If the dual-issue architecture is selected, the part number will become CV32A65MX to denote the extra performance. +CV32A60X is an interim part number until the team can decide if this configuration is single- or dual-issue. +If the dual-issue architecture is selected, the part number will become CV32A65X to denote the extra performance. In the future, dedicated user manuals for each configuration could be generated. The team is looking for a contributor to implement this through *templating*. diff --git a/docs/01_cva6_user/Programmer_View.rst b/docs/01_cva6_user/Programmer_View.rst index 03473d06d7..b601ade72b 100644 --- a/docs/01_cva6_user/Programmer_View.rst +++ b/docs/01_cva6_user/Programmer_View.rst @@ -32,23 +32,25 @@ CVA6 family The following extensions are available for the CVA6 family. Some of them are optional and are enabled through parameters in the SystemVerilog design. +**RV32** denotes RISC-V 32-bit extensions. **RV64** denotes RISC-V 64-bit extensions. + .. csv-table:: :widths: auto :align: left :header: "Extension", "Optional", "RV32 (in CV32A6)", "RV64 (in CV64A6)", "Note" - "I- Base Integer Instruction Set", "No", "✓", "✓", "Note 1" - "A - Atomic Instructions", "Yes", "✓", "✓", "Note 1" - "Zb* - Bit-Manipulation", "Yes", "✓", "✓", "Note 1" - "C - Compressed Instructions ", "Yes", "✓", "✓", "Note 1" - "Zcb - Code Size Reduction", "Yes", "✓", "✓", "Note 1" - "D - Double precision floating-point", "Yes", "", "✓", "Note 1" - "F - Single precision floating-point", "Yes", "✓", "✓", "Note 1" - "M - Integer Multiply/Divide", "No", "✓", "✓", "Note 1" - "Zicount - Performance Counters", "Yes", "✓", "✓", "Note 2" - "Zicsr - Control and Status Register Instructions", "No", "✓", "✓", "Note 2" - "Zifencei - Instruction-Fetch Fence", "No", "✓", "✓", "Note 2" - "Zicond - Integer Conditional Operations(Ratification pending)", "Yes", "✓", "✓", "Note 2" + "I- Base Integer Instruction Set", "No", "✔", "✔", "Note 1" + "A - Atomic Instructions", "Yes", "✔", "✔", "Note 1" + "Zb* - Bit-Manipulation", "Yes", "✔", "✔", "Note 1" + "C - Compressed Instructions ", "Yes", "✔", "✔", "Note 1" + "Zcb - Code Size Reduction", "Yes", "✔", "✔", "Note 1" + "D - Double precision floating-point", "Yes", "", "✔", "Note 1" + "F - Single precision floating-point", "Yes", "✔", "✔", "Note 1" + "M - Integer Multiply/Divide", "No", "✔", "✔", "Note 1" + "Zicount - Performance Counters", "Yes", "✔", "✔", "Note 2" + "Zicsr - Control and Status Register Instructions", "No", "✔", "✔", "Note 2" + "Zifencei - Instruction-Fetch Fence", "No", "✔", "✔", "Note 2" + "Zicond - Integer Conditional Operations(Ratification pending)", "Yes", "✔", "✔", "Note 2" Notes: @@ -57,50 +59,50 @@ Notes: *The following tables detail the availability of extensions for the various CVA6 configurations:* -CV32A60X extensions +CV32A60AX extensions ~~~~~~~~~~~~~~~~~~~ -These extensions are available in CV32A60X: +These extensions are available in CV32A60AX: .. csv-table:: :widths: auto :align: left - :header: "Extension", "Available in CV32A60X" + :header: "Extension", "Available in CV32A60AX" - "RV32I - Base Integer Instruction Set", "✓" - "RV32A - Atomic Instructions", "✓" - "RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✓" - "RV32C - Compressed Instructions ", "✓" - "RV32Zcb - Code Size Reduction", "✓" + "RV32I - Base Integer Instruction Set", "✔" + "RV32A - Atomic Instructions", "✔" + "RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔" + "RV32C - Compressed Instructions ", "✔" + "RV32Zcb - Code Size Reduction", "✔" "RV32D - Double precision floating-point", "" "RV32F - Single precision floating-point", "" - "RV32M - Integer Multiply/Divide", "✓" - "RVZicount - Performance Counters", "✓" - "RVZicsr - Control and Status Register Instructions", "✓" - "RVZifencei - Instruction-Fetch Fence", "✓" - "RVZicond - Integer Conditional Operations(Ratification pending)", "✓" + "RV32M - Integer Multiply/Divide", "✔" + "RVZicount - Performance Counters", "✔" + "RVZicsr - Control and Status Register Instructions", "✔" + "RVZifencei - Instruction-Fetch Fence", "✔" + "RVZicond - Integer Conditional Operations(Ratification pending)", "✔" -CV32A60MX extensions +CV32A60X extensions ~~~~~~~~~~~~~~~~~~~ -These extensions are available in CV32A60MX: +These extensions are available in CV32A60X: .. csv-table:: :widths: auto :align: left - :header: "Extension", "Available in CV32A60X" + :header: "Extension", "Available in CV32A60AX" - "RV32I - Base Integer Instruction Set", "✓" + "RV32I - Base Integer Instruction Set", "✔" "RV32A - Atomic Instructions", "" - "RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✓" - "RV32C - Compressed Instructions ", "✓" - "RV32Zcb - Code Size Reduction", "✓" + "RV32Zb* - Bit-Manipulation (Zba, Zbb, Zbc, Zbs)", "✔" + "RV32C - Compressed Instructions ", "✔" + "RV32Zcb - Code Size Reduction", "✔" "RV32D - Double precision floating-point", "" "RV32F - Single precision floating-point", "" - "RV32M - Integer Multiply/Divide", "✓" + "RV32M - Integer Multiply/Divide", "✔" "RVZicount - Performance Counters", "" - "RVZicsr - Control and Status Register Instructions", "✓" - "RVZifencei - Instruction-Fetch Fence", "✓" + "RVZicsr - Control and Status Register Instructions", "✔" + "RVZifencei - Instruction-Fetch Fence", "✔" "RVZicond - Integer Conditional Operations(Ratification pending)", "" @@ -125,31 +127,31 @@ Note: The addition of the H Extension is in the process. After that, HS, VS, and *The following tables detail the availability of privileges modes for the various CVA6 configurations:* -CV32A60X privilege modes +CV32A60AX privilege modes ~~~~~~~~~~~~~~~~~~~~~~~~ -These privilege modes are available in CV32A60X: +These privilege modes are available in CV32A60AX: .. csv-table:: :widths: auto :align: left - :header: "Privileges", "Available in CV32A60X" + :header: "Privileges", "Available in CV32A60AX" - "M - Machine", "✓" - "S - Supervior", "✓" - "U - User", "✓" + "M - Machine", "✔" + "S - Supervior", "✔" + "U - User", "✔" -CV32A60MX privilege modes +CV32A60X privilege modes ~~~~~~~~~~~~~~~~~~~~~~~~ -These privilege modes are available in CV32A60MX: +These privilege modes are available in CV32A60X: .. csv-table:: :widths: auto :align: left - :header: "Privileges", "Available in CV32A60MX" + :header: "Privileges", "Available in CV32A60X" - "M - Machine", "✓" + "M - Machine", "✔" "S - Supervior", "" "U - User", "" @@ -178,13 +180,13 @@ Notes for the integrator: *These are the addressing modes supported by the various CVA6 configurations:* -CV32A60X virtual memory +CV32A60AX virtual memory ~~~~~~~~~~~~~~~~~~~~~~~ -CV32A60X integrates an MMU and supports both the **Bare** and **Sv32** addressing modes. +CV32A60AX integrates an MMU and supports both the **Bare** and **Sv32** addressing modes. -CV32A60MX virtual memory +CV32A60X virtual memory ~~~~~~~~~~~~~~~~~~~~~~~~ CV32A60X integrates no MMU and only supports the **Bare** addressing mode. diff --git a/docs/01_cva6_user/RISCV_Instructions.rst b/docs/01_cva6_user/RISCV_Instructions.rst index aa26c8c95e..0398c0ae1e 100644 --- a/docs/01_cva6_user/RISCV_Instructions.rst +++ b/docs/01_cva6_user/RISCV_Instructions.rst @@ -31,6 +31,10 @@ In the next pages, the ISA (Instruction Set Architecture) for various CVA6 confi * RV32M – Standard Extension for Integer Multiplication and Division Instructions * RV32A – Standard Extension for Atomic Instructions * RV32C – Standard Extension for Compressed Instructions +* RVZba - Standard Extension for Bit Manipulation: Address generation instructions (RV32 and RV64) +* RVZbb - Standard Extension for Bit Manipulation: Basic bit manipulation (RV32 and RV64) +* RVZbc - Standard Extension for Bit Manipulation: Carry-less multiplication (RV32 and RV64) +* RVZbs - Standard Extension for Bit Manipulation: Single-bit instructions (RV32 and RV64) * RV32Zcb – Standard Extension for Code Size Reduction * RVZicsr – Standard Extension for CSR Instructions * RVZifencei – Standard Extension for Instruction-Fetch Fence diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32A.rst b/docs/01_cva6_user/RISCV_Instructions_RV32A.rst index a2c404088c..799e762322 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32A.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32A.rst @@ -25,8 +25,8 @@ :align: left :header: "Configuration", "Implementation" - "CV32A60X", "Implemented extension" - "CV32A60MX", "Not implemented extension" + "CV32A60AX", "Implemented extension" + "CV32A60X", "Not implemented extension" **Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64A, that includes additional instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32C.rst b/docs/01_cva6_user/RISCV_Instructions_RV32C.rst index 8b9bf0beab..3428994566 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32C.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32C.rst @@ -25,8 +25,8 @@ :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "Implemented extension" "CV32A60X", "Implemented extension" - "CV32A60MX", "Implemented extension" **Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64C, that includes a different list of instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32I.rst b/docs/01_cva6_user/RISCV_Instructions_RV32I.rst index 62df7d0167..fde58f5bb9 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32I.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32I.rst @@ -27,8 +27,8 @@ This chapter is applicable to all CV32A6 configurations. :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "Implemented extension" "CV32A60X", "Implemented extension" - "CV32A60MX", "Implemented extension" **Note**: CV64A6 implements RV64I that includes additional instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32M.rst b/docs/01_cva6_user/RISCV_Instructions_RV32M.rst index 771934de93..31c715d993 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32M.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32M.rst @@ -27,8 +27,8 @@ This chapter is applicable to all CV32A6 configurations. :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "Implemented extension" "CV32A60X", "Implemented extension" - "CV32A60MX", "Implemented extension" **Note**: CV64A6 implements RV64M that includes additional instructions. diff --git a/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst b/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst index 4b9789adbc..f8086a5401 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst @@ -25,8 +25,8 @@ :align: left :header: "Configuration", "Implementation" + "CV32A60AX", "Implemented extension" "CV32A60X", "Implemented extension" - "CV32A60MX", "Implemented extension" **Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64Zcb, that includes one additional instruction. diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZba.rst b/docs/01_cva6_user/RISCV_Instructions_RVZba.rst index 062821469a..fa2ee0fd7b 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZba.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZba.rst @@ -1,5 +1,36 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zba: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV32A60X", "Implemented extension" + + ====================================== -Zba: Address generation instructions +RVZba: Address generation instructions ====================================== The Zba instructions can be used to accelerate the generation of addresses that index into arrays of basic types (halfword, word, doubleword) using both unsigned word-sized and XLEN-sized indices: a shifted index is added to a base address. @@ -29,77 +60,85 @@ The following instructions (and pseudoinstructions) comprise the Zba extension: | | ✔ | slli.uw rd, rs1, imm | +-----------+-----------+-----------------------+ -- **ADD.UW**: Add unsigned word +RV32 and RV64 Instructions +-------------------------- - **Format**: add.uw rd, rs1, rs2 - **Description**: This instruction performs an XLEN-wide addition between rs2 and the zero-extended least-significant word of rs1. +- **SH1ADD**: Shift left by 1 and add - **Pseudocode**: X(rd) = rs2 + EXTZ(X(rs1)[31..0]) + **Format**: sh1add rd, rs1, rs2 + + **Description**: This instruction shifts rs1 to the left by 1 bit and adds it to rs2. + + **Pseudocode**: X(rd) = X(rs2) + (X(rs1) << 1) **Invalid values**: NONE **Exception raised**: NONE -- **SH1ADD**: Shift left by 1 and add +- **SH2ADD**: Shift left by 2 and add - **Format**: sh1add rd, rs1, rs2 + **Format**: sh2add rd, rs1, rs2 - **Description**: This instruction shifts rs1 to the left by 1 bit and adds it to rs2. + **Description**: This instruction shifts rs1 to the left by 2 bit and adds it to rs2. - **Pseudocode**: X(rd) = X(rs2) + (X(rs1) << 1) + **Pseudocode**: X(rd) = X(rs2) + (X(rs1) << 2) **Invalid values**: NONE **Exception raised**: NONE -- **SH1ADD.UW**: Shift unsigned word left by 1 and add +- **SH3ADD**: Shift left by 3 and add - **Format**: sh1add.uw rd, rs1, rs2 + **Format**: sh3add rd, rs1, rs2 - **Description**: This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 1 place. + **Description**: This instruction shifts rs1 to the left by 3 bit and adds it to rs2. - **Pseudocode**: X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 1) + **Pseudocode**: X(rd) = X(rs2) + (X(rs1) << 3) **Invalid values**: NONE - **Exception raised**: NONE + **Exception raised**: NONE -- **SH2ADD**: Shift left by 2 and add - **Format**: sh2add rd, rs1, rs2 +RV64 specific instructions +-------------------------- - **Description**: This instruction shifts rs1 to the left by 2 bit and adds it to rs2. +- **ADD.UW**: Add unsigned word - **Pseudocode**: X(rd) = X(rs2) + (X(rs1) << 2) + **Format**: add.uw rd, rs1, rs2 + + **Description**: This instruction performs an XLEN-wide addition between rs2 and the zero-extended least-significant word of rs1. + + **Pseudocode**: X(rd) = rs2 + EXTZ(X(rs1)[31..0]) **Invalid values**: NONE **Exception raised**: NONE -- **SH2ADD.UW**: Shift unsigned word left by 2 and add +- **SH1ADD.UW**: Shift unsigned word left by 1 and add - **Format**: sh2add.uw rd, rs1, rs2 + **Format**: sh1add.uw rd, rs1, rs2 - **Description**: This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 2 places. + **Description**: This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 1 place. - **Pseudocode**: X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 2) + **Pseudocode**: X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 1) **Invalid values**: NONE **Exception raised**: NONE -- **SH3ADD**: Shift left by 3 and add +- **SH2ADD.UW**: Shift unsigned word left by 2 and add - **Format**: sh3add rd, rs1, rs2 + **Format**: sh2add.uw rd, rs1, rs2 - **Description**: This instruction shifts rs1 to the left by 3 bit and adds it to rs2. + **Description**: This instruction performs an XLEN-wide addition of two addends. The first addend is rs2. The second addend is the unsigned value formed by extracting the least-significant word of rs1 and shifting it left by 2 places. - **Pseudocode**: X(rd) = X(rs2) + (X(rs1) << 3) + **Pseudocode**: X(rd) = rs2 + (EXTZ(X(rs1)[31..0]) << 2) **Invalid values**: NONE - **Exception raised**: NONE + **Exception raised**: NONE - **SH3ADD.UW**: Shift unsigned word left by 3 and add @@ -124,5 +163,3 @@ The following instructions (and pseudoinstructions) comprise the Zba extension: **Invalid values**: NONE **Exception raised**: NONE - - diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst index 635161056c..3ea37fda11 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst @@ -1,6 +1,36 @@ -============================ -Zbb: Basic bit-manipulation -============================ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zbb: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV32A60X", "Implemented extension" + +============================= +RVZbb: Basic bit-manipulation +============================= The following instructions comprise the Zbb extension: @@ -18,6 +48,10 @@ The Logical with Negate instructions can be implemented by inverting the rs2 inp | ✔ | ✔ | xnor rd, rs1, rs2 | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + - **ANDN**: AND with inverted operand **Format**: andn rd, rs1, rs2 @@ -71,6 +105,9 @@ These instructions are used to count the leading/trailing zero bits. | | ✔ | ctzw rd, rs | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **CLZ**: Count leading zero bits **Format**: clz rd, rs @@ -83,25 +120,28 @@ These instructions are used to count the leading/trailing zero bits. **Exception raised**: NONE -- **CLZW**: Count leading zero bits in word +- **CTZ**: Count trailing zeros - **Format**: clzw rd, rs + **Format**: ctz rd, rs - **Description**: This instruction counts the number of 0’s before the first 1 starting at bit 31 and progressing to bit 0. Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant bit of the word (i.e., bit 31) is a 1, the output is 0. + **Description**: This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1). Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0. - **Pseudocode**: if [x[i]] == 1 then return(i) else return -1 + **Pseudocode**: if [x[i]] == 1 then return(i) else return xlen; **Invalid values**: NONE **Exception raised**: NONE -- **CTZ**: Count trailing zeros +RV64 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ - **Format**: ctz rd, rs +- **CLZW**: Count leading zero bits in word - **Description**: This instruction counts the number of 0’s before the first 1, starting at the least-significant bit (i.e., 0) and progressing to the most-significant bit (i.e., XLEN-1). Accordingly, if the input is 0, the output is XLEN, and if the least-significant bit of the input is a 1, the output is 0. + **Format**: clzw rd, rs - **Pseudocode**: if [x[i]] == 1 then return(i) else return xlen; + **Description**: This instruction counts the number of 0’s before the first 1 starting at bit 31 and progressing to bit 0. Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant bit of the word (i.e., bit 31) is a 1, the output is 0. + + **Pseudocode**: if [x[i]] == 1 then return(i) else return -1 **Invalid values**: NONE @@ -119,7 +159,7 @@ These instructions are used to count the leading/trailing zero bits. **Exception raised**: NONE - + Count population ------------------- These instructions count the number of set bits (1-bits). This is also commonly referred to as population count. @@ -132,6 +172,9 @@ These instructions count the number of set bits (1-bits). This is also commonly | | ✔ | cpopw rd, rs | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **CPOP**: Count set bits **Format**: cpop rd, rs @@ -144,6 +187,9 @@ These instructions count the number of set bits (1-bits). This is also commonly **Exception raised**: NONE +RV64 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **CPOPW**: Count set bits in word **Format**: cpopw rd, rs @@ -174,6 +220,9 @@ The integer minimum/maximum instructions are arithmetic R-type instructions that | ✔ | ✔ | minu rd, rs1, rs2 | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **MAX**: Maximum **Format**: max rd, rs1, rs2 @@ -239,6 +288,9 @@ These instructions replace the generalized idioms slli rD,rS,(XLEN-) + srl | ✔ | ✔ | zext.h rd, rs | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **SEXT.B**: Sign-extend byte **Format**: sext.b rd, rs @@ -295,6 +347,9 @@ Bitwise rotation instructions are similar to the shift-logical operations from t | | ✔ | rorw rd, rs1, rs2 | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **ROL**: Rotate Left (Register) **Format**: rol rd, rs1, rs2 @@ -307,18 +362,6 @@ Bitwise rotation instructions are similar to the shift-logical operations from t **Exception raised**: NONE -- **ROLW**: Rotate Left Word (Register) - - **Format**: rolw rd, rs1, rs2 - - **Description**: This instruction performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits. - - **Pseudocode**: EXTS((rs1 << X(rs2)[4..0];) | (rs1 >> (32 - X(rs2)[4..0];))) - - **Invalid values**: NONE - - **Exception raised**: NONE - - **ROR**: Rotate Right **Format**: ror rd, rs1, rs2 @@ -343,6 +386,21 @@ Bitwise rotation instructions are similar to the shift-logical operations from t **Exception raised**: NONE +RV64 specific instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **ROLW**: Rotate Left Word (Register) + + **Format**: rolw rd, rs1, rs2 + + **Description**: This instruction performs a rotate left on the least-significant word of rs1 by the amount in least-significant 5 bits of rs2. The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits. + + **Pseudocode**: EXTS((rs1 << X(rs2)[4..0];) | (rs1 >> (32 - X(rs2)[4..0];))) + + **Invalid values**: NONE + + **Exception raised**: NONE + - **RORIW**: Rotate Right Word by Immediate **Format**: roriw rd, rs1, shamt @@ -366,7 +424,7 @@ Bitwise rotation instructions are similar to the shift-logical operations from t **Invalid values**: NONE **Exception raised**: NONE - + OR Combine ------------ orc.b sets the bits of each byte in the result rd to all zeros if no bit within the respective byte of rs is set, or to all ones if any bit within the respective byte of rs is set. @@ -379,6 +437,9 @@ One use-case is string-processing functions, such as strlen and strcpy, which ca | ✔ | ✔ | orc.b rd, rs | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **ORC.B**: Bitwise OR-Combine, byte granule **Format**: orc.b rd, rs @@ -401,6 +462,9 @@ rev8 reverses the byte-ordering of rs. | ✔ | ✔ | rev8 rd, rs | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +~~~~~~~~~~~~~~~~~~~~~~~~~~ + - **REV8**: Byte-reverse register **Format**: rev8 rd, rs diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst index dd0d7126a7..27257affda 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst @@ -1,5 +1,36 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zbc: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV32A60X", "Implemented extension" + + ================================= -Zbc: Carry-less multiplication +RVZbc: Carry-less multiplication ================================= Carry-less multiplication is the multiplication in the polynomial ring over GF(2). @@ -19,6 +50,9 @@ The following instructions (and pseudoinstructions) comprise the Zbc extension: | ✔ | ✔ | clmulr rd, rs1, rs2 | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +-------------------------- + - **CLMUL**: Carry-less multiply (low-part) **Format**: clmul rd, rs1, rs2 diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst index c4926dc08a..06cf980356 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst @@ -1,5 +1,36 @@ +.. + Copyright (c) 2023 OpenHW Group + Copyright (c) 2023 10xEngineers + + SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +.. Level 1 + ======= + + Level 2 + ------- + + Level 3 + ~~~~~~~ + + Level 4 + ^^^^^^^ + +.. _cva6_riscv_instructions_RV32Zbs: + +*Applicability of this chapter to configurations:* + +.. csv-table:: + :widths: auto + :align: left + :header: "Configuration", "Implementation" + + "CV32A60AX", "Implemented extension" + "CV32A60X", "Implemented extension" + + ============================ -Zbs: Single-bit instructions +RVZbs: Single-bit instructions ============================ The single-bit instructions provide a mechanism to set, clear, invert, or extract a single bit in a register. The bit is specified by its index. @@ -25,6 +56,9 @@ The following instructions (and pseudoinstructions) comprise the Zbs extension: | ✔ | ✔ | bseti rd, rs1, imm | +-----------+-----------+-----------------------+ +RV32 and RV64 Instructions +-------------------------- + - **BCLR**: Single-Bit Clear (Register) **Format**: bclr rd, rs1, rs2 diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst b/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst index d4f6ec39ad..e2b5d1c3f1 100644 --- a/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst +++ b/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst @@ -25,8 +25,8 @@ :align: left :header: "Configuration", "Implementation" - "CV32A60X", "Implemented extension" - "CV32A60MX", "Not implemented extension" + "CV32A60AX", "Implemented extension" + "CV32A60X", "Not implemented extension" **Note**: RV32Zicond and RV64Zicond are identical. diff --git a/docs/02_cva6_requirements/cva6_requirements_specification.rst b/docs/02_cva6_requirements/cva6_requirements_specification.rst index 4f6d46c4a8..3265d3aa57 100644 --- a/docs/02_cva6_requirements/cva6_requirements_specification.rst +++ b/docs/02_cva6_requirements/cva6_requirements_specification.rst @@ -143,30 +143,30 @@ Below are the configuration of the first releases of the CVA6. +--------------------+---------+---------+------+-------+---------+---------+---------+---------+ | Release ID | Target | ISA | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | +====================+=========+=========+======+=======+=========+=========+=========+=========+ -| CV32E6?X | ASIC | IMC | 32 | No | Yes | None | 2 kB | 2 kB | +| ``CV32A60X`` | ASIC | IMC | 32 | No | Yes | None | 2 kB | 2 kB | +--------------------+---------+---------+------+-------+---------+---------+---------+---------+ -| CV32A60X | ASIC | IMC | 32 | No | Yes | Sv32 | 16kB | 16 kB | +| ``CV32A60AX`` | ASIC | IMC | 32 | No | Yes | Sv32 | 16kB | 16 kB | +--------------------+---------+---------+------+-------+---------+---------+---------+---------+ -The value of the "?" digit above is yet to be defined when all details of this configuration are known. - -Possible Future Releases ------------------------- - -Below is a proposed list of configurations that could undergo verification and their main parameters. -The full list of parameters for these configurations will be detailed in the users’ guide if and when these configurations are fully verified. - -+--------------------+---------+--------+------+-------+---------+---------+---------+---------+ -| Configuation ID | Target | ISA | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | -+====================+=========+========+======+=======+=========+=========+=========+=========+ -| cv32a6_imacf_sv32 | FPGA | IMACF | 32 | Yes | TBD | Sv32 | 32 kB | 16 kB | -+--------------------+---------+--------+------+-------+---------+---------+---------+---------+ -| cv32a6_imac_sv32 | FPGA | IMAC | 32 | No | TBD | Sv32 | 32 kB | 16 kB | -+--------------------+---------+--------+------+-------+---------+---------+---------+---------+ -| cv64a6_imacfd_sv39 | ASIC | IMACFD | 64 | Yes | Yes | Sv39 | 16 kB | 16 kB | -+--------------------+---------+--------+------+-------+---------+---------+---------+---------+ -| cv32a6_imac_sv0 | ASIC | IMAC | 32 | No | Yes | None | None | 4 kB | -+--------------------+---------+--------+------+-------+---------+---------+---------+---------+ +CV32A60X could evolve to CV32A65X if the team decides to integrate the dual-issue optional architectural feature. + +.. Possible Future Releases +.. ------------------------ +.. +.. Below is a proposed list of configurations that could undergo verification and their main parameters. +.. The full list of parameters for these configurations will be detailed in the users’ guide if and when these configurations are fully verified. +.. +.. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ +.. | Configuation ID | Target | ISA | XLEN | FPU | CV-X-IF | MMU | L1 D$ | L1 I$ | +.. +====================+=========+========+======+=======+=========+=========+=========+=========+ +.. | cv32a6_imacf_sv32 | FPGA | IMACF | 32 | Yes | TBD | Sv32 | 32 kB | 16 kB | +.. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ +.. | cv32a6_imac_sv32 | FPGA | IMAC | 32 | No | TBD | Sv32 | 32 kB | 16 kB | +.. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ +.. | cv64a6_imacfd_sv39 | ASIC | IMACFD | 64 | Yes | Yes | Sv39 | 16 kB | 16 kB | +.. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ +.. | cv32a6_imac_sv0 | ASIC | IMAC | 32 | No | Yes | None | None | 4 kB | +.. +--------------------+---------+--------+------+-------+---------+---------+---------+---------+ .. _references: