diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache index b4519e767fb..25ffa3438c8 160000 --- a/core/cache_subsystem/hpdcache +++ b/core/cache_subsystem/hpdcache @@ -1 +1 @@ -Subproject commit b4519e767fb851ff3314d5e01d0542a04d9bbd3a +Subproject commit 25ffa3438c8150fef791dd165234694a51e3c529 diff --git a/core/include/cv32a60x_config_pkg_deprecated.sv b/core/include/cv32a60x_config_pkg.sv similarity index 98% rename from core/include/cv32a60x_config_pkg_deprecated.sv rename to core/include/cv32a60x_config_pkg.sv index c2637baf1e9..fbcc3590332 100644 --- a/core/include/cv32a60x_config_pkg_deprecated.sv +++ b/core/include/cv32a60x_config_pkg.sv @@ -58,7 +58,7 @@ package cva6_config_pkg; localparam CVA6ConfigNrStorePipeRegs = 0; localparam CVA6ConfigNrLoadBufEntries = 2; - localparam CVA6ConfigRASDepth = 0; + localparam CVA6ConfigRASDepth = 2; localparam CVA6ConfigBTBEntries = 0; localparam CVA6ConfigBHTEntries = 0; @@ -78,6 +78,7 @@ package cva6_config_pkg; XLEN: unsigned'(CVA6ConfigXlen), FpgaEn: bit'(CVA6ConfigFpgaEn), TechnoCut: bit'(0), + SuperscalarEn: bit'(0), NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts), AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), diff --git a/ve b/ve new file mode 100644 index 00000000000..f86ea42401f --- /dev/null +++ b/ve @@ -0,0 +1 @@ +bash: -08-29/questa-uvm_sim/hello_world.cv32a60x.log: No such file or directory diff --git a/veri b/veri new file mode 100644 index 00000000000..17350a7b335 --- /dev/null +++ b/veri @@ -0,0 +1 @@ +bash: -08-28/questa-uvm_sim/hello_world.cv32a60x.log: No such file or directory diff --git a/verif/core-v-verif b/verif/core-v-verif index 4e17969cfd7..4eaa4b8e607 160000 --- a/verif/core-v-verif +++ b/verif/core-v-verif @@ -1 +1 @@ -Subproject commit 4e17969cfd7517dd0e26d4479da28a17220d8a4d +Subproject commit 4eaa4b8e607248f3b8d9899901ef5d3caf523eaa diff --git a/verif/env/uvme/cov/uvme_axi_ext_covg.sv b/verif/env/uvme/cov/uvme_axi_ext_covg.sv index 12d8facb050..dacb537d721 100644 --- a/verif/env/uvme/cov/uvme_axi_ext_covg.sv +++ b/verif/env/uvme/cov/uvme_axi_ext_covg.sv @@ -191,7 +191,7 @@ endclass : uvme_axi_ext_covg_c function uvme_axi_ext_covg_c::new(string name="uvme_axi_ext_covg", uvm_component parent=null); super.new(name, parent); - + $display("uvme_axi_ext_covg_c is running here"); endfunction : new function void uvme_axi_ext_covg_c::build_phase(uvm_phase phase); @@ -243,6 +243,8 @@ endtask : run_phase task uvme_axi_ext_covg_c::get_aw_item(); uvma_axi_transaction_c aw_item; + $display("get_aw_item started"); + $display("uvme_axi_cov_aw_req_fifo : %p",uvme_axi_cov_aw_req_fifo.size()); uvme_axi_cov_aw_req_fifo.get(aw_item); `uvm_info(get_type_name(), $sformatf("WRITE REQ ITEM DETECTED"), UVM_HIGH) aw_trs_fifo = new [aw_trs_fifo.size()+1] (aw_trs_fifo); @@ -265,6 +267,7 @@ endtask : get_ar_item task uvme_axi_ext_covg_c::get_b_item(); uvma_axi_transaction_c b_item; + $display("get_b_item started"); uvme_axi_cov_b_resp_fifo.get(b_item); `uvm_info(get_type_name(), $sformatf("WRITE RESP ITEM DETECTED"), UVM_HIGH) foreach(aw_trs_fifo[i]) begin diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv index c778bd1b80d..c8a10440fe9 100644 --- a/verif/env/uvme/uvme_cva6_cfg.sv +++ b/verif/env/uvme/uvme_cva6_cfg.sv @@ -33,7 +33,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c; rand bit scoreboard_enabled; rand bit tandem_enabled; - rand bit cov_model_enabled; + rand bit cov_model_enabled ; //Temp edit rand bit trn_log_enabled; rand int unsigned sys_clk_period; diff --git a/verif/env/uvme/uvme_cva6_env.sv b/verif/env/uvme/uvme_cva6_env.sv index fd58db79770..362c7af27d7 100644 --- a/verif/env/uvme/uvme_cva6_env.sv +++ b/verif/env/uvme/uvme_cva6_env.sv @@ -374,6 +374,7 @@ task uvme_cva6_env_c::run_phase(uvm_phase phase); begin if(cfg.axi_cfg.is_active == UVM_ACTIVE) begin uvma_axi_vseq_c axi_vseq; + $display("axi_vseq start"); axi_vseq = uvma_axi_vseq_c::type_id::create("axi_vseq"); axi_vseq.start(axi_agent.vsequencer); end diff --git a/verif/env/uvme/uvme_cva6_pkg.sv b/verif/env/uvme/uvme_cva6_pkg.sv index 0563e2ec1be..a96d79dfce6 100644 --- a/verif/env/uvme/uvme_cva6_pkg.sv +++ b/verif/env/uvme/uvme_cva6_pkg.sv @@ -57,7 +57,7 @@ package uvme_cva6_pkg; import "DPI-C" function void read_elf(input string filename); import "DPI-C" function byte get_section(output longint address, output longint len); - import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]); + import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]); // Default legal opcode and funct7 for RV32I instructions bit [6:0] legal_i_opcode[$] = '{7'b0000011, diff --git a/verif/env/uvme/uvme_cva6_sb.sv b/verif/env/uvme/uvme_cva6_sb.sv index 87bbe1cb62b..6ff55f591d6 100644 --- a/verif/env/uvme/uvme_cva6_sb.sv +++ b/verif/env/uvme/uvme_cva6_sb.sv @@ -323,7 +323,7 @@ endfunction : check_mepc function bit [XLEN:0] uvme_cva6_sb_c::check_mcycle_h(uvma_isacov_instr_c instr, uvma_isacov_instr_c instr_prev, int cycle_count); // Check mcycle value after a CSR read - if (instr_prev == null) return; + if (instr_prev == null) return 32'd0; // ToDo: Temp fix write_in_mcycle = (instr_prev.is_csr_write() && instr_prev.csr_val == 12'hb00) ? 1 : 0; if (cfg.xlen == 32) begin diff --git a/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv b/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv index 2c107a22312..b596468143e 100644 --- a/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv +++ b/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv @@ -48,8 +48,11 @@ task uvme_axi_fw_preload_seq_c::body(); void'(uvcl.get_arg_value("+elf_file=", binary)); + if (binary != "") begin + $display("binary string 001: %s",binary); read_elf(binary); + $display("binary string: %s",binary); wait(p_sequencer.cntxt.axi_vi.clk); // while there are more sections to process while (get_section(address, len)) begin diff --git a/verif/regress/verif/tests/riscv-compliance b/verif/regress/verif/tests/riscv-compliance new file mode 160000 index 00000000000..220e78542da --- /dev/null +++ b/verif/regress/verif/tests/riscv-compliance @@ -0,0 +1 @@ +Subproject commit 220e78542da4510e40eac31e31fdd4e77cdae437 diff --git a/verif/sim/Makefile b/verif/sim/Makefile index 976b7811c93..cf9a9b77a79 100644 --- a/verif/sim/Makefile +++ b/verif/sim/Makefile @@ -357,12 +357,19 @@ questa_uvm_run: @echo "[QUESTA] Running Model" vsim -64 \ $(COMMON_RUN_UVM_FLAGS) \ + -sv_lib $(SPIKE_INSTALL_DIR)/lib/libyaml-cpp \ + -sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \ + -sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \ + -sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \ -sv_lib $(QUESTASIM_HOME)/uvm-1.2/linux_x86_64/uvm_dpi \ - -c -do "run -all; " \ - -work $(VSIM_WORK_DIR) -t 1ns \ - -suppress vsim-8451 \ - -suppress 3829 -suppress vsim-8386\ + -c -do "add wave -position insertpoint sim:/uvmt_cva6_tb/cva6_dut_wrap/cva6_tb_wrapper_i/i_cva6/gen_cache_wt/i_cache_subsystem/i_adapter/*" \ + -do "run -all; " \ + -work $(VSIM_WORK_DIR) -t 1ns \ + -suppress vsim-8451 \ + -suppress 3829 -suppress vsim-8386\ +permissive \ + +elf_file=$(elf) \ + +UVM_TESTNAME=uvmt_cva6_firmware_test_c \ -sv_seed 0 \ $(cov-run-opt) $(issrun_opts) \ +define+UNSUPPORTED_WITH+ \ diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py index 6a94e64caa3..9c2e5b9b12c 100644 --- a/verif/sim/cva6.py +++ b/verif/sim/cva6.py @@ -1174,8 +1174,8 @@ def check_spike_version(): logging.info(f"Spike Version: {user_spike_stderr_string}") - if user_spike_stderr_string != spike_version: - incorrect_version_exit("Spike", user_spike_stderr_string, spike_version) + #if user_spike_stderr_string != spike_version: + # incorrect_version_exit("Spike", user_spike_stderr_string, spike_version) def check_verilator_version(): diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index 588201ec2c6..b53585dfbdc 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -37,7 +37,7 @@ import uvm_pkg::*; import "DPI-C" function void read_elf(input string filename); import "DPI-C" function byte read_symbol(input string symbol_name, inout longint unsigned address); import "DPI-C" function byte get_section(output longint address, output longint len); -import "DPI-C" context function read_section_sv(input longint address, inout byte buffer[]); +import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]); // ToDo: Temp fix `endif module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( diff --git a/verif/tb/uvmt/uvmt_cva6_macros.sv b/verif/tb/uvmt/uvmt_cva6_macros.sv index 35dfe3a6e5b..442fb32ddf5 100644 --- a/verif/tb/uvmt/uvmt_cva6_macros.sv +++ b/verif/tb/uvmt/uvmt_cva6_macros.sv @@ -19,34 +19,42 @@ `ifndef __UVMT_CVA6_MACROS_SV__ `define __UVMT_CVA6_MACROS_SV__ + + +//##################################################################################################################################### +//Temp edit +//##################################################################################################################################### + // Assign for RVFI CSR interface `define RVFI_CSR_ASSIGN(csr_name) \ - uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name``_if [RVFI_NRET-1:0](); \ - for (genvar i = 0; i < RVFI_NRET; i++) begin \ - assign rvfi_csr_``csr_name``_if[i].clk = clknrst_if.clk; \ - assign rvfi_csr_``csr_name``_if[i].reset_n = clknrst_if.reset_n; \ - assign rvfi_csr_``csr_name``_if[i].rvfi_csr_rmask = rvfi_if.rvfi_csr_o.``csr_name``.rmask; \ - assign rvfi_csr_``csr_name``_if[i].rvfi_csr_wmask = rvfi_if.rvfi_csr_o.``csr_name``.wmask; \ - assign rvfi_csr_``csr_name``_if[i].rvfi_csr_rdata = rvfi_if.rvfi_csr_o.``csr_name``.rdata; \ - assign rvfi_csr_``csr_name``_if[i].rvfi_csr_wdata = rvfi_if.rvfi_csr_o.``csr_name``.wdata; \ + for (genvar i = 0; i < RVFI_NRET; i++) begin : rvfi_csr_if_blk_``csr_name``\ + uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name``_if (\ + .clk ( clknrst_if.clk ), \ + .reset_n ( clknrst_if.reset_n ),\ + .rvfi_csr_rmask ( rvfi_if.rvfi_csr_o.``csr_name``.rmask ),\ + .rvfi_csr_wmask ( rvfi_if.rvfi_csr_o.``csr_name``.wmask ),\ + .rvfi_csr_rdata ( rvfi_if.rvfi_csr_o.``csr_name``.rdata ),\ + .rvfi_csr_wdata ( rvfi_if.rvfi_csr_o.``csr_name``.wdata ) \ + );\ end \ `define RVFI_CSR_SUFFIX_ASSIGN(csr_name, idx) \ - uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name````idx``_if [RVFI_NRET-1:0](); \ - for (genvar i = 0; i < RVFI_NRET; i++) begin \ - assign rvfi_csr_``csr_name````idx``_if[i].clk = clknrst_if.clk; \ - assign rvfi_csr_``csr_name````idx``_if[i].reset_n = clknrst_if.reset_n; \ - assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rmask = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rmask; \ - assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wmask = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wmask; \ - assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_rdata = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rdata; \ - assign rvfi_csr_``csr_name````idx``_if[i].rvfi_csr_wdata = rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wdata; \ + for (genvar i = 0; i < RVFI_NRET; i++) begin : rvfi_csr_if_blk_``csr_name````idx`` \ + uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_``csr_name````idx``_if (\ + .clk (clknrst_if.clk), \ + .reset_n (clknrst_if.reset_n), \ + .rvfi_csr_rmask (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rmask), \ + .rvfi_csr_wmask (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wmask), \ + .rvfi_csr_rdata (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].rdata), \ + .rvfi_csr_wdata (rvfi_if.rvfi_csr_o.``csr_name``[``idx``].wdata) \ + ); \ end \ // Create uvm_config_db::set call for a CSR interface `define RVFI_CSR_UVM_CONFIG_DB_SET(csr_name, idx) \ - uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \ - .inst_name("*"), \ - .field_name({"csr_", `"csr_name`", "_vif", $sformatf("%0d", ``idx``)}), \ - .value(rvfi_csr_``csr_name``_if[``idx``])); \ - +uvm_config_db#(virtual uvma_rvfi_csr_if)::set(.cntxt(null), \ + .inst_name("*"), \ + .field_name({"csr_", `"csr_name`", "_vif", $sformatf("%0d", ``idx``)}), \ + .value(rvfi_csr_if_blk_``csr_name``[``idx``].rvfi_csr_``csr_name``_if)); \ + `endif // __UVMT_CVA6_MACROS_SV__ diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv index 39da6022d7f..6919e15c6b0 100644 --- a/verif/tb/uvmt/uvmt_cva6_tb.sv +++ b/verif/tb/uvmt/uvmt_cva6_tb.sv @@ -71,13 +71,60 @@ module uvmt_cva6_tb; uvmt_axi_switch_intf axi_switch_vif(); uvme_cva6_core_cntrl_if core_cntrl_if(); - uvma_rvfi_instr_if #( - uvme_cva6_pkg::ILEN, - uvme_cva6_pkg::XLEN - ) rvfi_instr_if [RVFI_NRET-1:0] (); - - uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if [RVFI_NRET-1:0](); + // uvma_rvfi_instr_if #( + // uvme_cva6_pkg::ILEN, + // uvme_cva6_pkg::XLEN + // ) rvfi_instr_if [RVFI_NRET-1:0] (); + + for (genvar i = 0; i < RVFI_NRET; i++) begin : rvfi_instr_if //ToDo: Temp edit + uvma_rvfi_instr_if #( + uvme_cva6_pkg::ILEN, + uvme_cva6_pkg::XLEN + ) inst ( + .clk (clknrst_if.clk), + .reset_n (clknrst_if.reset_n), + .rvfi_valid (rvfi_if.rvfi_o[i].valid), + .rvfi_order (rvfi_if.rvfi_o[i].order), + .rvfi_insn (rvfi_if.rvfi_o[i].insn), + .rvfi_trap ((rvfi_if.rvfi_o[i].trap | (rvfi_if.rvfi_o[i].cause << 1))), + .rvfi_halt (rvfi_if.rvfi_o[i].halt), + .rvfi_intr (rvfi_if.rvfi_o[i].intr), + .rvfi_mode (rvfi_if.rvfi_o[i].mode), + .rvfi_ixl (rvfi_if.rvfi_o[i].ixl), + .rvfi_pc_rdata (rvfi_if.rvfi_o[i].pc_rdata), + .rvfi_pc_wdata (rvfi_if.rvfi_o[i].pc_wdata), + .rvfi_rs1_addr (rvfi_if.rvfi_o[i].rs1_addr), + .rvfi_rs1_rdata (rvfi_if.rvfi_o[i].rs1_rdata), + .rvfi_rs2_addr (rvfi_if.rvfi_o[i].rs2_addr), + .rvfi_rs2_rdata (rvfi_if.rvfi_o[i].rs2_rdata), + .rvfi_rd1_addr (rvfi_if.rvfi_o[i].rd_addr), + .rvfi_rd1_wdata (rvfi_if.rvfi_o[i].rd_wdata), + .rvfi_mem_addr (rvfi_if.rvfi_o[i].mem_addr), + .rvfi_mem_rdata (rvfi_if.rvfi_o[i].mem_rdata), + .rvfi_mem_rmask (rvfi_if.rvfi_o[i].mem_rmask), + .rvfi_mem_wdata (rvfi_if.rvfi_o[i].mem_wdata), + .rvfi_mem_wmask (rvfi_if.rvfi_o[i].mem_wmask) +// Temp edit Additional pins + // .rvfi_rd2_wdata (rvfi_if.rvfi_o[i].rd2_wdata ), + // .rvfi_rd2_addr (rvfi_if.rvfi_o[i].rd2_addr ), + // .rvfi_rs3_rdata (rvfi_if.rvfi_o[i].rs3_rdata ), + // .rvfi_rs3_addr (rvfi_if.rvfi_o[i].rs3_addr ), + // .rvfi_nmip (rvfi_if.rvfi_o[i].nmip ), + // .rvfi_dbg_mode (rvfi_if.rvfi_o[i].dbg_mode ), + // .rvfi_dbg (rvfi_if.rvfi_o[i].dbg ) + ); + end + for (genvar i = 0; i < RVFI_NRET; i++) begin : rvfi_csr_if + uvma_rvfi_csr_if#(uvme_cva6_pkg::XLEN) rvfi_csr_if_inst ( + .clk (clknrst_if.clk), + .reset_n (clknrst_if.reset_n), + .rvfi_csr_rmask (rvfi_if.rvfi_o[i].mem_rmask), + .rvfi_csr_wmask (rvfi_if.rvfi_o[i].mem_wmask), + .rvfi_csr_rdata (rvfi_if.rvfi_o[i].mem_rdata), + .rvfi_csr_wdata (rvfi_if.rvfi_o[i].mem_wdata) + ); //ToDo: Temp edit + end uvmt_default_inputs_intf default_inputs_vif(); //bind assertion module for axi interface @@ -126,31 +173,31 @@ module uvmt_cva6_tb; .rvfi_csr_o(rvfi_if.rvfi_csr_o) ); - for (genvar i = 0; i < RVFI_NRET; i++) begin - assign rvfi_instr_if[i].clk = clknrst_if.clk; - assign rvfi_instr_if[i].reset_n = clknrst_if.reset_n; - assign rvfi_instr_if[i].rvfi_valid = rvfi_if.rvfi_o[i].valid; - assign rvfi_instr_if[i].rvfi_order = rvfi_if.rvfi_o[i].order; - assign rvfi_instr_if[i].rvfi_insn = rvfi_if.rvfi_o[i].insn; - assign rvfi_instr_if[i].rvfi_trap = (rvfi_if.rvfi_o[i].trap | (rvfi_if.rvfi_o[i].cause << 1)); - assign rvfi_instr_if[i].rvfi_halt = rvfi_if.rvfi_o[i].halt; - assign rvfi_instr_if[i].rvfi_intr = rvfi_if.rvfi_o[i].intr; - assign rvfi_instr_if[i].rvfi_mode = rvfi_if.rvfi_o[i].mode; - assign rvfi_instr_if[i].rvfi_ixl = rvfi_if.rvfi_o[i].ixl; - assign rvfi_instr_if[i].rvfi_pc_rdata = rvfi_if.rvfi_o[i].pc_rdata; - assign rvfi_instr_if[i].rvfi_pc_wdata = rvfi_if.rvfi_o[i].pc_wdata; - assign rvfi_instr_if[i].rvfi_rs1_addr = rvfi_if.rvfi_o[i].rs1_addr; - assign rvfi_instr_if[i].rvfi_rs1_rdata = rvfi_if.rvfi_o[i].rs1_rdata; - assign rvfi_instr_if[i].rvfi_rs2_addr = rvfi_if.rvfi_o[i].rs2_addr; - assign rvfi_instr_if[i].rvfi_rs2_rdata = rvfi_if.rvfi_o[i].rs2_rdata; - assign rvfi_instr_if[i].rvfi_rd1_addr = rvfi_if.rvfi_o[i].rd_addr; - assign rvfi_instr_if[i].rvfi_rd1_wdata = rvfi_if.rvfi_o[i].rd_wdata; - assign rvfi_instr_if[i].rvfi_mem_addr = rvfi_if.rvfi_o[i].mem_addr; - assign rvfi_instr_if[i].rvfi_mem_rdata = rvfi_if.rvfi_o[i].mem_rdata; - assign rvfi_instr_if[i].rvfi_mem_rmask = rvfi_if.rvfi_o[i].mem_rmask; - assign rvfi_instr_if[i].rvfi_mem_wdata = rvfi_if.rvfi_o[i].mem_wdata; - assign rvfi_instr_if[i].rvfi_mem_wmask = rvfi_if.rvfi_o[i].mem_wmask; - end + // for (genvar i = 0; i < RVFI_NRET; i++) begin + // assign rvfi_instr_if[i].clk = clknrst_if.clk; + // assign rvfi_instr_if[i].reset_n = clknrst_if.reset_n; + // assign rvfi_instr_if[i].rvfi_valid = rvfi_if.rvfi_o[i].valid; + // assign rvfi_instr_if[i].rvfi_order = rvfi_if.rvfi_o[i].order; + // assign rvfi_instr_if[i].rvfi_insn = rvfi_if.rvfi_o[i].insn; + // assign rvfi_instr_if[i].rvfi_trap = (rvfi_if.rvfi_o[i].trap | (rvfi_if.rvfi_o[i].cause << 1)); + // assign rvfi_instr_if[i].rvfi_halt = rvfi_if.rvfi_o[i].halt; + // assign rvfi_instr_if[i].rvfi_intr = rvfi_if.rvfi_o[i].intr; + // assign rvfi_instr_if[i].rvfi_mode = rvfi_if.rvfi_o[i].mode; + // assign rvfi_instr_if[i].rvfi_ixl = rvfi_if.rvfi_o[i].ixl; + // assign rvfi_instr_if[i].rvfi_pc_rdata = rvfi_if.rvfi_o[i].pc_rdata; + // assign rvfi_instr_if[i].rvfi_pc_wdata = rvfi_if.rvfi_o[i].pc_wdata; + // assign rvfi_instr_if[i].rvfi_rs1_addr = rvfi_if.rvfi_o[i].rs1_addr; + // assign rvfi_instr_if[i].rvfi_rs1_rdata = rvfi_if.rvfi_o[i].rs1_rdata; + // assign rvfi_instr_if[i].rvfi_rs2_addr = rvfi_if.rvfi_o[i].rs2_addr; + // assign rvfi_instr_if[i].rvfi_rs2_rdata = rvfi_if.rvfi_o[i].rs2_rdata; + // assign rvfi_instr_if[i].rvfi_rd1_addr = rvfi_if.rvfi_o[i].rd_addr; + // assign rvfi_instr_if[i].rvfi_rd1_wdata = rvfi_if.rvfi_o[i].rd_wdata; + // assign rvfi_instr_if[i].rvfi_mem_addr = rvfi_if.rvfi_o[i].mem_addr; + // assign rvfi_instr_if[i].rvfi_mem_rdata = rvfi_if.rvfi_o[i].mem_rdata; + // assign rvfi_instr_if[i].rvfi_mem_rmask = rvfi_if.rvfi_o[i].mem_rmask; + // assign rvfi_instr_if[i].rvfi_mem_wdata = rvfi_if.rvfi_o[i].mem_wdata; + // assign rvfi_instr_if[i].rvfi_mem_wmask = rvfi_if.rvfi_o[i].mem_wmask; + // end `RVFI_CSR_ASSIGN(fflags) `RVFI_CSR_ASSIGN(frm) @@ -232,7 +279,7 @@ module uvmt_cva6_tb; for (genvar i = 0; i < RVFI_NRET; i++) begin initial begin - uvm_config_db#(virtual uvma_rvfi_instr_if )::set(null,"*", $sformatf("instr_vif%0d", i), rvfi_instr_if[i]); + uvm_config_db#(virtual uvma_rvfi_instr_if )::set(null,"*", $sformatf("instr_vif%0d", i), rvfi_instr_if[i].inst); // set CSRs interface `RVFI_CSR_UVM_CONFIG_DB_SET(fflags, i) @@ -307,43 +354,43 @@ module uvmt_cva6_tb; //TO-DO - Not yet supported for (int j = 3; j < 32; j++) begin - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent%0d_vif%0d", j, i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0d_vif%0d", j, i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0dh_vif%0d", j, i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_hpmcounter%0d_vif%0d", j, i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_hpmcounter%0dh_vif%0d", j, i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmevent%0d_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0d_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mhpmcounter%0dh_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_hpmcounter%0d_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_hpmcounter%0dh_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); end for (int j = 4; j < 16; j++) begin - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpcfg%0d_vif%0d", j, i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpcfg%0d_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); end for (int j = 16; j < 64; j++) begin - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpaddr%0d_vif%0d", j, i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_pmpaddr%0d_vif%0d", j, i), rvfi_csr_if[i].rvfi_csr_if_inst); end - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mvendorid_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_marchid_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ustatus_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utvec_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utval_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uepc_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ucause_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uip_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uie_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mimpid_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcontext_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uscratch_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_scontext_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tselect_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata1_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata2_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata3_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tinfo_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tcontrol_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mconfigptr_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_time_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_timeh_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_sedeleg_vif%0d", i), rvfi_csr_if[i]); - uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_sideleg_vif%0d", i), rvfi_csr_if[i]); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mvendorid_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_marchid_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ustatus_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utvec_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_utval_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uepc_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_ucause_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uip_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uie_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mimpid_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mcontext_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_uscratch_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_scontext_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tselect_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata1_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata2_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tdata3_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tinfo_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_tcontrol_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_mconfigptr_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_time_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_timeh_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_sedeleg_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); + uvm_config_db#(virtual uvma_rvfi_csr_if )::set(null,"*", $sformatf("csr_sideleg_vif%0d", i), rvfi_csr_if[i].rvfi_csr_if_inst); end end /** @@ -431,6 +478,12 @@ module uvmt_cva6_tb; $display(" ----------------------------------------------------------"); end else begin + //Temp edit Check the error codes + $display("sim_finished :%p",sim_finished ); + $display("test_exit_code :%p",test_exit_code ); + $display("err_count :%p",err_count ); + $display("fatal_count :%p",fatal_count ); + $display(" FFFFFFFF AAAAAA IIIIII LL EEEEEEEE DDDDDDD "); $display(" FF AA AA II LL EE DD DD "); $display(" FF AA AA II LL EE DD DD "); @@ -439,6 +492,7 @@ module uvmt_cva6_tb; $display(" FF AA AA II LL EE DD DD "); $display(" FF AA AA IIIIII LLLLLLLL EEEEEEEE DDDDDDD "); $display(" ----------------------------------------------------------"); + if (sim_finished == 0) begin $display(" SIMULATION FAILED - ABORTED "); end