From 6c9e271a2e8b33fed663075a289a4583e345670d Mon Sep 17 00:00:00 2001 From: Yannick Casamatta Date: Mon, 12 Feb 2024 09:35:48 +0100 Subject: [PATCH] add csr in rvfi --- core/csr_regfile.sv | 437 +++++++++++++++++++++++----- core/cva6.sv | 91 +++--- core/cva6_rvfi.sv | 189 +++++++++--- core/cva6_rvfi_probes.sv | 81 ++++-- core/include/ariane_pkg.sv | 115 ++++++++ corev_apu/src/ariane.sv | 8 +- corev_apu/tb/ariane_testharness.sv | 40 +-- corev_apu/tb/rvfi_tracer.sv | 2 + pd/synth/cva6_synth.tcl | 3 + verif/tb/uvmt/cva6_tb_wrapper.sv | 45 +-- verif/tb/uvmt/uvmt_cva6_dut_wrap.sv | 10 +- verif/tb/uvmt/uvmt_cva6_tb.sv | 15 +- 12 files changed, 772 insertions(+), 264 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 8ddf8fd478c..276c4547f35 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -21,122 +21,125 @@ module csr_regfile parameter int unsigned MHPMCounterNum = 6 ) ( // Subsystem Clock - SUBSYSTEM - input logic clk_i, + input logic clk_i, // Asynchronous reset active low - SUBSYSTEM - input logic rst_ni, + input logic rst_ni, // Timer threw a interrupt - SUBSYSTEM - input logic time_irq_i, + input logic time_irq_i, // send a flush request out when a CSR with a side effect changes - CONTROLLER - output logic flush_o, + output logic flush_o, // halt requested - CONTROLLER - output logic halt_csr_o, + output logic halt_csr_o, // Instruction to be committed - ID_STAGE - input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, + input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i, // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE - input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM - input logic [ riscv::VLEN-1:0] boot_addr_i, + input logic [riscv::VLEN-1:0] boot_addr_i, // Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM - input logic [ riscv::XLEN-1:0] hart_id_i, + input logic [riscv::XLEN-1:0] hart_id_i, // we are taking an exception // We've got an exception from the commit stage, take it - COMMIT_STAGE - input exception_t ex_i, + input exception_t ex_i, // Operation to perform on the CSR file - COMMIT_STAGE - input fu_op csr_op_i, + input fu_op csr_op_i, // Address of the register to read/write - EX_STAGE - input logic [ 11:0] csr_addr_i, + input logic [11:0] csr_addr_i, // Write data in - COMMIT_STAGE - input logic [ riscv::XLEN-1:0] csr_wdata_i, + input logic [riscv::XLEN-1:0] csr_wdata_i, // Read data out - COMMIT_STAGE - output logic [ riscv::XLEN-1:0] csr_rdata_o, + output logic [riscv::XLEN-1:0] csr_rdata_o, // Mark the FP sate as dirty - COMMIT_STAGE - input logic dirty_fp_state_i, + input logic dirty_fp_state_i, // Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE - input logic csr_write_fflags_i, + input logic csr_write_fflags_i, // Mark the V state as dirty - ACC_DISPATCHER - input logic dirty_v_state_i, + input logic dirty_v_state_i, // PC of instruction accessing the CSR - COMMIT_STAGE - input logic [ riscv::VLEN-1:0] pc_i, + input logic [riscv::VLEN-1:0] pc_i, // attempts to access a CSR without appropriate privilege - COMMIT_STAGE - output exception_t csr_exception_o, + output exception_t csr_exception_o, // Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly - FRONTEND - output logic [ riscv::VLEN-1:0] epc_o, + output logic [riscv::VLEN-1:0] epc_o, // Return from exception, set the PC of epc_o - FRONTEND - output logic eret_o, + output logic eret_o, // Output base of exception vector, correct CSR is output (mtvec, stvec) - FRONTEND - output logic [ riscv::VLEN-1:0] trap_vector_base_o, + output logic [riscv::VLEN-1:0] trap_vector_base_o, // Current privilege level the CPU is in - EX_STAGE - output riscv::priv_lvl_t priv_lvl_o, + output riscv::priv_lvl_t priv_lvl_o, // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER - input logic [ 4:0] acc_fflags_ex_i, + input logic [4:0] acc_fflags_ex_i, // An FP exception from the accelerator occurred - ACC_DISPATCHER - input logic acc_fflags_ex_valid_i, + input logic acc_fflags_ex_valid_i, // Floating point extension status - ID_STAGE - output riscv::xs_t fs_o, + output riscv::xs_t fs_o, // Floating-Point Accured Exceptions - COMMIT_STAGE - output logic [ 4:0] fflags_o, + output logic [4:0] fflags_o, // Floating-Point Dynamic Rounding Mode - EX_STAGE - output logic [ 2:0] frm_o, + output logic [2:0] frm_o, // Floating-Point Precision Control - EX_STAGE - output logic [ 6:0] fprec_o, + output logic [6:0] fprec_o, // Vector extension status - ID_STAGE - output riscv::xs_t vs_o, + output riscv::xs_t vs_o, // interrupt management to id stage - ID_STAGE - output irq_ctrl_t irq_ctrl_o, + output irq_ctrl_t irq_ctrl_o, // enable VA translation - EX_STAGE - output logic en_translation_o, + output logic en_translation_o, // enable VA translation for load and stores - EX_STAGE - output logic en_ld_st_translation_o, + output logic en_ld_st_translation_o, // Privilege level at which load and stores should happen - EX_STAGE - output riscv::priv_lvl_t ld_st_priv_lvl_o, + output riscv::priv_lvl_t ld_st_priv_lvl_o, // TO_BE_COMPLETED - EX_STAGE - output logic sum_o, + output logic sum_o, // TO_BE_COMPLETED - EX_STAGE - output logic mxr_o, + output logic mxr_o, // TO_BE_COMPLETED - EX_STAGE - output logic [ riscv::PPNW-1:0] satp_ppn_o, + output logic [riscv::PPNW-1:0] satp_ppn_o, // TO_BE_COMPLETED - EX_STAGE - output logic [ AsidWidth-1:0] asid_o, + output logic [AsidWidth-1:0] asid_o, // external interrupt in - SUBSYSTEM - input logic [ 1:0] irq_i, + input logic [1:0] irq_i, // inter processor interrupt -> connected to machine mode sw - SUBSYSTEM - input logic ipi_i, + input logic ipi_i, // debug request in - ID_STAGE - input logic debug_req_i, + input logic debug_req_i, // TO_BE_COMPLETED - FRONTEND - output logic set_debug_pc_o, + output logic set_debug_pc_o, // trap virtual memory - ID_STAGE - output logic tvm_o, + output logic tvm_o, // timeout wait - ID_STAGE - output logic tw_o, + output logic tw_o, // trap sret - ID_STAGE - output logic tsr_o, + output logic tsr_o, // we are in debug mode -> that will change some decoding - EX_STAGE - output logic debug_mode_o, + output logic debug_mode_o, // we are in single-step mode - COMMIT_STAGE - output logic single_step_o, + output logic single_step_o, // L1 ICache Enable - CACHE - output logic icache_en_o, + output logic icache_en_o, // L1 DCache Enable - CACHE - output logic dcache_en_o, + output logic dcache_en_o, // Accelerator memory consistent mode - ACC_DISPATCHER - output logic acc_cons_en_o, + output logic acc_cons_en_o, // Performance Counter // read/write address to performance counter module - PERF_COUNTERS - output logic [ 11:0] perf_addr_o, + output logic [11:0] perf_addr_o, // write data to performance counter module - PERF_COUNTERS - output logic [ riscv::XLEN-1:0] perf_data_o, + output logic [riscv::XLEN-1:0] perf_data_o, // read data from performance counter module - PERF_COUNTERS - input logic [ riscv::XLEN-1:0] perf_data_i, + input logic [riscv::XLEN-1:0] perf_data_i, // TO_BE_COMPLETED - PERF_COUNTERS - output logic perf_we_o, + output logic perf_we_o, // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER - output riscv::pmpcfg_t [ 15:0] pmpcfg_o, + output riscv::pmpcfg_t [15:0] pmpcfg_o, // PMP addresses - ACC_DISPATCHER - output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o, + output logic [15:0][riscv::PLEN-3:0] pmpaddr_o, // TO_BE_COMPLETED - PERF_COUNTERS - output logic [ 31:0] mcountinhibit_o + output logic [31:0] mcountinhibit_o, + // RVFI + output rvfi_probes_csr_t rvfi_csr_o ); + // internal signal to keep track of access exceptions logic read_access_exception, update_access_exception, privilege_violation; logic csr_we, csr_read; @@ -191,8 +194,8 @@ module csr_regfile logic [63:0] cycle_q, cycle_d; logic [63:0] instret_q, instret_d; - riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; - logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d; + riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d, pmpcfg_next; + logic [15:0][riscv::PLEN-3:0] pmpaddr_q, pmpaddr_d, pmpaddr_next; logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q; logic [3:0] index; @@ -1663,23 +1666,29 @@ module csr_regfile // wait for interrupt wfi_q <= wfi_d; // pmp - for (int i = 0; i < 16; i++) begin - if (i < CVA6Cfg.NrPMPEntries) begin - // We only support >=8-byte granularity, NA4 is disabled - if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin - pmpcfg_q[i] <= pmpcfg_d[i]; - end else begin - pmpcfg_q[i] <= pmpcfg_q[i]; - end - if (!CVA6Cfg.PMPEntryReadOnly[i]) begin - pmpaddr_q[i] <= pmpaddr_d[i]; - end else begin - pmpaddr_q[i] <= pmpaddr_q[i]; - end + pmpcfg_q <= pmpcfg_next; + pmpaddr_q <= pmpaddr_next; + end + end + + // write logic pmp + always_comb begin : write + for (int i = 0; i < 16; i++) begin + if (i < CVA6Cfg.NrPMPEntries) begin + // We only support >=8-byte granularity, NA4 is disabled + if(!CVA6Cfg.PMPEntryReadOnly[i] && pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin + pmpcfg_next[i] <= pmpcfg_d[i]; end else begin - pmpcfg_q[i] <= '0; - pmpaddr_q[i] <= '0; + pmpcfg_next[i] <= pmpcfg_q[i]; + end + if (!CVA6Cfg.PMPEntryReadOnly[i]) begin + pmpaddr_next[i] <= pmpaddr_d[i]; + end else begin + pmpaddr_next[i] <= pmpaddr_q[i]; end + end else begin + pmpcfg_next[i] <= '0; + pmpaddr_next[i] <= '0; end end end @@ -1695,4 +1704,284 @@ module csr_regfile $stop(); end //pragma translate_on + + + //RVFI CSR + + //------------- + // RVFI + //------------- + assign rvfi_csr_o.fflags = CVA6Cfg.FpPresent ? + '{rdata: {'0, fcsr_q.fflags}, wdata: {'0, fcsr_d.fflags}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.frm = CVA6Cfg.FpPresent ? + '{rdata: {'0, fcsr_q.frm}, wdata: {'0, fcsr_d.frm}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.fcsr = CVA6Cfg.FpPresent ? + '{ + rdata: {'0, fcsr_q.frm, fcsr_q.fflags}, + wdata: {'0, fcsr_d.frm, fcsr_d.fflags}, + rmask: '1, + wmask: '1 + } + : '0; + assign rvfi_csr_o.ftran = CVA6Cfg.FpPresent ? + '{rdata: {'0, fcsr_q.fprec}, wdata: {'0, fcsr_d.fprec}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dcsr = CVA6Cfg.DebugEn ? + '{rdata: {'0, dcsr_q}, wdata: {'0, dcsr_d}, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dpc = CVA6Cfg.DebugEn ? + '{rdata: {dpc_q}, wdata: dpc_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dscratch0 = CVA6Cfg.DebugEn ? + '{rdata: dscratch0_q, wdata: dscratch0_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dscratch1 = CVA6Cfg.DebugEn ? + '{rdata: dscratch1_q, wdata: dscratch1_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sstatus = CVA6Cfg.RVS ? + '{ + rdata: mstatus_extended & ariane_pkg::SMODE_STATUS_READ_MASK[riscv::XLEN-1:0], + wdata: mstatus_extended & ariane_pkg::SMODE_STATUS_READ_MASK[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + } + : '0; + assign rvfi_csr_o.sie = CVA6Cfg.RVS ? + '{rdata: mie_q & mideleg_q, wdata: mie_d & mideleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sip = CVA6Cfg.RVS ? + '{rdata: mip_q & mideleg_q, wdata: mip_d & mideleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.stvec = CVA6Cfg.RVS ? + '{rdata: stvec_q, wdata: stvec_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.scounteren = CVA6Cfg.RVS ? + '{rdata: scounteren_q, wdata: scounteren_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sscratch = CVA6Cfg.RVS ? + '{rdata: sscratch_q, wdata: sscratch_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.sepc = CVA6Cfg.RVS ? + '{rdata: sepc_q, wdata: sepc_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.scause = CVA6Cfg.RVS ? + '{rdata: scause_q, wdata: scause_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.stval = CVA6Cfg.RVS ? + '{rdata: stval_q, wdata: stval_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.satp = CVA6Cfg.RVS ? + '{rdata: satp_q, wdata: satp_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mstatus = '{ + rdata: mstatus_extended, + wdata: mstatus_extended, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mstatush = riscv::XLEN == 32 ? + '{rdata: '0, wdata: '0, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.misa = '{rdata: IsaCode, wdata: IsaCode, rmask: '1, wmask: '1}; + assign rvfi_csr_o.medeleg = CVA6Cfg.RVS ? + '{rdata: medeleg_q, wdata: medeleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mideleg = CVA6Cfg.RVS ? + '{rdata: mideleg_q, wdata: mideleg_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mie = '{rdata: mie_q, wdata: mie_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mtvec = '{rdata: mtvec_q, wdata: mtvec_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mcounteren = '{ + rdata: mcounteren_q, + wdata: mcounteren_d, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mscratch = '{rdata: mscratch_q, wdata: mscratch_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mepc = '{rdata: mepc_q, wdata: mepc_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mcause = '{rdata: mcause_q, wdata: mcause_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mtval = '{rdata: mtval_q, wdata: mtval_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mip = '{rdata: mip_q, wdata: mip_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.menvcfg = '{rdata: {'0, fiom_q}, wdata: {'0, fiom_d}, rmask: '1, wmask: '1}; + assign rvfi_csr_o.menvcfgh = riscv::XLEN == 32 ? + '{rdata: '0, wdata: '0, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.mvendorid = '{ + rdata: OPENHWGROUP_MVENDORID, + wdata: OPENHWGROUP_MVENDORID, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.marchid = '{ + rdata: ARIANE_MARCHID, + wdata: ARIANE_MARCHID, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mhartid = '{rdata: hart_id_i, wdata: hart_id_i, rmask: '1, wmask: '1}; + assign rvfi_csr_o.mcountinhibit = '{ + rdata: {'0, mcountinhibit_q}, + wdata: {'0, mcountinhibit_d}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mcycle = '{ + rdata: cycle_q[riscv::XLEN-1:0], + wdata: cycle_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.mcycleh = riscv::XLEN == 32 ? + '{rdata: cycle_q[63:32], wdata: cycle_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.minstret = '{ + rdata: instret_q[riscv::XLEN-1:0], + wdata: instret_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.minstreth = riscv::XLEN == 32 ? + '{rdata: instret_q[63:32], wdata: instret_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.cycle = '{ + rdata: cycle_q[riscv::XLEN-1:0], + wdata: cycle_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.cycleh = riscv::XLEN == 32 ? + '{rdata: cycle_q[63:32], wdata: cycle_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.instret = '{ + rdata: instret_q[riscv::XLEN-1:0], + wdata: instret_d[riscv::XLEN-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.instreth = riscv::XLEN == 32 ? + '{rdata: instret_q[63:32], wdata: instret_d[63:32], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.dcache = '{rdata: dcache_q, wdata: dcache_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.icache = '{rdata: icache_q, wdata: icache_d, rmask: '1, wmask: '1}; + assign rvfi_csr_o.acc_cons = CVA6Cfg.EnableAccelerator ? + '{rdata: acc_cons_q, wdata: acc_cons_d, rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.pmpcfg0 = '{ + rdata: pmpcfg_q[riscv::XLEN/8-1:0], + wdata: pmpcfg_d[riscv::XLEN/8-1:0], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpcfg1 = riscv::XLEN == 32 ? + '{rdata: pmpcfg_q[7:4], wdata: pmpcfg_d[7:4], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.pmpcfg2 = '{ + rdata: pmpcfg_q[8+:riscv::XLEN/8], + wdata: pmpcfg_d[8+:riscv::XLEN/8], + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpcfg3 = riscv::XLEN == 32 ? + '{rdata: pmpcfg_q[15:12], wdata: pmpcfg_d[15:12], rmask: '1, wmask: '1} + : '0; + assign rvfi_csr_o.pmpaddr0 = '{ + rdata: {'0, pmpaddr_q[0][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[0][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr1 = '{ + rdata: {'0, pmpaddr_q[1][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[1][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr2 = '{ + rdata: {'0, pmpaddr_q[2][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[2][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr3 = '{ + rdata: {'0, pmpaddr_q[3][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[3][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr4 = '{ + rdata: {'0, pmpaddr_q[4][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[4][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr5 = '{ + rdata: {'0, pmpaddr_q[5][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[5][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr6 = '{ + rdata: {'0, pmpaddr_q[6][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[6][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr7 = '{ + rdata: {'0, pmpaddr_q[7][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[7][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr8 = '{ + rdata: {'0, pmpaddr_q[8][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[8][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr9 = '{ + rdata: {'0, pmpaddr_q[9][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[9][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr10 = '{ + rdata: {'0, pmpaddr_q[10][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[10][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr11 = '{ + rdata: {'0, pmpaddr_q[11][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[11][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr12 = '{ + rdata: {'0, pmpaddr_q[12][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[12][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr13 = '{ + rdata: {'0, pmpaddr_q[13][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[13][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr14 = '{ + rdata: {'0, pmpaddr_q[14][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[14][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + assign rvfi_csr_o.pmpaddr15 = '{ + rdata: {'0, pmpaddr_q[15][riscv::PLEN-3:0]}, + wdata: {'0, pmpaddr_d[15][riscv::PLEN-3:0]}, + rmask: '1, + wmask: '1 + }; + + endmodule diff --git a/core/cva6.sv b/core/cva6.sv index 385a487908c..d8ad675d09f 100644 --- a/core/cva6.sv +++ b/core/cva6.sv @@ -18,30 +18,11 @@ module cva6 #( // CVA6 config parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg, - parameter bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace), - // RVFI + parameter type rvfi_probes_t = struct packed { - logic [TRANS_ID_BITS-1:0] issue_pointer; - logic [CVA6Cfg.NrCommitPorts-1:0][TRANS_ID_BITS-1:0] commit_pointer; - logic flush_unissued_instr; - logic decoded_instr_valid; - logic flush; - logic decoded_instr_ack; - logic issue_instr_ack; - logic fetch_entry_valid; - logic [31:0] instruction; - logic is_compressed; - riscv::xlen_t rs1_forwarding; - riscv::xlen_t rs2_forwarding; - scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr; - exception_t ex_commit; - riscv::priv_lvl_t priv_lvl; - lsu_ctrl_t lsu_ctrl; - logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; - logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; - logic [riscv::PLEN-1:0] mem_paddr; - logic debug_mode; - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + logic csr; + logic scoreboard; + logic instr; }, // AXI types @@ -462,8 +443,7 @@ module cva6 lsu_ctrl_t rvfi_lsu_ctrl; logic [riscv::PLEN-1:0] rvfi_mem_paddr; logic rvfi_is_compressed; - rvfi_probes_t rvfi_probes; - + rvfi_csr_t rvfi_csr; // Accelerator port logic [ 63:0] inval_addr; @@ -881,6 +861,8 @@ module cva6 .pmpcfg_o (pmpcfg), .pmpaddr_o (pmpaddr), .mcountinhibit_o (mcountinhibit_csr_perf), + //RVFI + .rvfi_csr_o (rvfi_csr), .debug_req_i, .ipi_i, .irq_i, @@ -1374,44 +1356,45 @@ module cva6 //pragma translate_on - if (IsRVFI) begin + //RVFI INSTR - cva6_rvfi_probes #( - .CVA6Cfg (CVA6ExtendCfg), - .rvfi_probes_t(rvfi_probes_t) - ) i_cva6_rvfi_combi ( + cva6_rvfi_probes #( + .CVA6Cfg (CVA6ExtendCfg), + .rvfi_probes_t(rvfi_probes_t) + ) i_cva6_rvfi_probes ( - .flush_i (flush_ctrl_if), - .issue_instr_ack_i (issue_instr_issue_id), - .fetch_entry_valid_i(fetch_valid_if_id), - .instruction_i (fetch_entry_if_id.instruction), - .is_compressed_i (rvfi_is_compressed), + .flush_i (flush_ctrl_if), + .issue_instr_ack_i (issue_instr_issue_id), + .fetch_entry_valid_i(fetch_valid_if_id), + .instruction_i (fetch_entry_if_id.instruction), + .is_compressed_i (rvfi_is_compressed), - .issue_pointer_i (rvfi_issue_pointer), - .commit_pointer_i(rvfi_commit_pointer), + .issue_pointer_i (rvfi_issue_pointer), + .commit_pointer_i(rvfi_commit_pointer), - .flush_unissued_instr_i(flush_unissued_instr_ctrl_id), - .decoded_instr_valid_i (issue_entry_valid_id_issue), - .decoded_instr_ack_i (issue_instr_issue_id), + .flush_unissued_instr_i(flush_unissued_instr_ctrl_id), + .decoded_instr_valid_i (issue_entry_valid_id_issue), + .decoded_instr_ack_i (issue_instr_issue_id), - .rs1_forwarding_i(rs1_forwarding_id_ex), - .rs2_forwarding_i(rs2_forwarding_id_ex), + .rs1_forwarding_i(rs1_forwarding_id_ex), + .rs2_forwarding_i(rs2_forwarding_id_ex), - .commit_instr_i(commit_instr_id_commit), - .ex_commit_i (ex_commit), - .priv_lvl_i (priv_lvl), + .commit_instr_i(commit_instr_id_commit), + .ex_commit_i (ex_commit), + .priv_lvl_i (priv_lvl), - .lsu_ctrl_i (rvfi_lsu_ctrl), - .wbdata_i (wbdata_ex_id), - .commit_ack_i(commit_ack), - .mem_paddr_i (rvfi_mem_paddr), - .debug_mode_i(debug_mode), - .wdata_i (wdata_commit_id), + .lsu_ctrl_i (rvfi_lsu_ctrl), + .wbdata_i (wbdata_ex_id), + .commit_ack_i(commit_ack), + .mem_paddr_i (rvfi_mem_paddr), + .debug_mode_i(debug_mode), + .wdata_i (wdata_commit_id), - .rvfi_probes_o(rvfi_probes_o) + .csr_i(rvfi_csr), - ); + .rvfi_probes_o(rvfi_probes_o) + + ); - end //IsRVFI endmodule // ariane diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index d4d9f103424..249b34a8bb7 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -14,14 +14,22 @@ module cva6_rvfi #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rvfi_instr_t = logic, - parameter type rvfi_probes_t = logic + parameter type rvfi_csr_t = logic, + parameter type rvfi_probes_t = struct packed { + logic csr; + logic scoreboard; + logic instr; + } + ) ( input logic clk_i, input logic rst_ni, input rvfi_probes_t rvfi_probes_i, - output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr_o, + output rvfi_csr_t rvfi_csr_o + ); @@ -146,32 +154,60 @@ module cva6_rvfi logic [ (riscv::XLEN/8)-1:0] lsu_wmask; logic [ TRANS_ID_BITS-1:0] lsu_addr_trans_id; - assign flush = rvfi_probes_i.flush; - assign issue_instr_ack = rvfi_probes_i.issue_instr_ack; - assign fetch_entry_valid = rvfi_probes_i.fetch_entry_valid; - assign instruction = rvfi_probes_i.instruction; - assign is_compressed = rvfi_probes_i.is_compressed; + riscv::pmpcfg_t [15:0] pmpcfg_q, pmpcfg_d; + + rvfi_probes_csr_t csr; + rvfi_probes_scoreboard_t [CVA6ExtendCfg.NrCommitPorts-1:0] scoreboard; + rvfi_probes_instr_t instr; + + always_comb begin + csr = '0; + scoreboard = '0; + instr = '0; + + if ($size(rvfi_probes_i.instr) != 1) begin + instr = rvfi_probes_i.instr; + end + + if ($size(rvfi_probes_i.scoreboard) != 1) begin + for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin + commit_pointer[i] = rvfi_probes_i.scoreboard[i].commit_pointer; + commit_instr[i] = rvfi_probes_i.scoreboard[i].commit_instr; + wdata[i] = rvfi_probes_i.scoreboard[i].wdata; + commit_ack[i] = rvfi_probes_i.scoreboard[i].commit_ack; + end + end + + if ($size(rvfi_probes_i.csr) != 1) begin + csr = rvfi_probes_i.csr; + end + + end + - assign issue_pointer = rvfi_probes_i.issue_pointer; - assign commit_pointer = rvfi_probes_i.commit_pointer; + assign flush = instr.flush; + assign issue_instr_ack = instr.issue_instr_ack; + assign fetch_entry_valid = instr.fetch_entry_valid; + assign instruction = instr.instruction; + assign is_compressed = instr.is_compressed; - assign flush_unissued_instr = rvfi_probes_i.flush_unissued_instr; - assign decoded_instr_valid = rvfi_probes_i.decoded_instr_valid; - assign decoded_instr_ack = rvfi_probes_i.decoded_instr_ack; + assign issue_pointer = instr.issue_pointer; - assign rs1_forwarding = rvfi_probes_i.rs1_forwarding; - assign rs2_forwarding = rvfi_probes_i.rs2_forwarding; + assign flush_unissued_instr = instr.flush_unissued_instr; + assign decoded_instr_valid = instr.decoded_instr_valid; + assign decoded_instr_ack = instr.decoded_instr_ack; - assign commit_instr = rvfi_probes_i.commit_instr; - assign ex_commit = rvfi_probes_i.ex_commit; - assign priv_lvl = rvfi_probes_i.priv_lvl; + assign rs1_forwarding = instr.rs1_forwarding; + assign rs2_forwarding = instr.rs2_forwarding; - assign lsu_ctrl = rvfi_probes_i.lsu_ctrl; - assign wbdata = rvfi_probes_i.wbdata; - assign commit_ack = rvfi_probes_i.commit_ack; - assign mem_paddr = rvfi_probes_i.mem_paddr; - assign debug_mode = rvfi_probes_i.debug_mode; - assign wdata = rvfi_probes_i.wdata; + assign ex_commit = instr.ex_commit; + assign priv_lvl = instr.priv_lvl; + + assign lsu_ctrl = instr.lsu_ctrl; + assign wbdata = instr.wbdata[CVA6ExtendCfg.NrWbPorts-1:0]; //hardcoded size in probes struct + + assign mem_paddr = instr.mem_paddr; + assign debug_mode = instr.debug_mode; assign lsu_addr = lsu_ctrl.vaddr; assign lsu_rmask = lsu_ctrl.fu == LOAD ? lsu_ctrl.be : '0; @@ -263,32 +299,101 @@ module cva6_rvfi for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin logic exception; exception = commit_instr[i].valid && ex_commit.valid; - rvfi_o[i].valid = (commit_ack[i] && !ex_commit.valid) || + rvfi_instr_o[i].valid = (commit_ack[i] && !ex_commit.valid) || (exception && (ex_commit.cause == riscv::ENV_CALL_MMODE || ex_commit.cause == riscv::ENV_CALL_SMODE || ex_commit.cause == riscv::ENV_CALL_UMODE)); - rvfi_o[i].insn = mem_q[commit_pointer[i]].instr; + rvfi_instr_o[i].insn = mem_q[commit_pointer[i]].instr; // when trap, the instruction is not executed - rvfi_o[i].trap = exception; - rvfi_o[i].cause = ex_commit.cause; - rvfi_o[i].mode = (CVA6ExtendCfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; - rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1; - rvfi_o[i].rs1_addr = commit_instr[i].rs1[4:0]; - rvfi_o[i].rs2_addr = commit_instr[i].rs2[4:0]; - rvfi_o[i].rd_addr = commit_instr[i].rd[4:0]; - rvfi_o[i].rd_wdata = (CVA6ExtendCfg.FpPresent && is_rd_fpr(commit_instr[i].op)) ? + rvfi_instr_o[i].trap = exception; + rvfi_instr_o[i].cause = ex_commit.cause; + rvfi_instr_o[i].mode = (CVA6ExtendCfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; + rvfi_instr_o[i].ixl = riscv::XLEN == 64 ? 2 : 1; + rvfi_instr_o[i].rs1_addr = commit_instr[i].rs1[4:0]; + rvfi_instr_o[i].rs2_addr = commit_instr[i].rs2[4:0]; + rvfi_instr_o[i].rd_addr = commit_instr[i].rd[4:0]; + rvfi_instr_o[i].rd_wdata = (CVA6ExtendCfg.FpPresent && is_rd_fpr(commit_instr[i].op)) ? commit_instr[i].result : wdata[i]; - rvfi_o[i].pc_rdata = commit_instr[i].pc; - rvfi_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr; + rvfi_instr_o[i].pc_rdata = commit_instr[i].pc; + rvfi_instr_o[i].mem_addr = mem_q[commit_pointer[i]].lsu_addr; // So far, only write paddr is reported. TODO: read paddr - rvfi_o[i].mem_paddr = mem_paddr; - rvfi_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask; - rvfi_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata; - rvfi_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask; - rvfi_o[i].mem_rdata = commit_instr[i].result; - rvfi_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata; - rvfi_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata; + rvfi_instr_o[i].mem_paddr = mem_paddr; + rvfi_instr_o[i].mem_wmask = mem_q[commit_pointer[i]].lsu_wmask; + rvfi_instr_o[i].mem_wdata = mem_q[commit_pointer[i]].lsu_wdata; + rvfi_instr_o[i].mem_rmask = mem_q[commit_pointer[i]].lsu_rmask; + rvfi_instr_o[i].mem_rdata = commit_instr[i].result; + rvfi_instr_o[i].rs1_rdata = mem_q[commit_pointer[i]].rs1_rdata; + rvfi_instr_o[i].rs2_rdata = mem_q[commit_pointer[i]].rs2_rdata; + end + end + + + //---------------------------------------------------------------------------------------------------------- + // CSR + //---------------------------------------------------------------------------------------------------------- + + always_comb begin + + rvfi_csr_o = csr; + + if (riscv::XLEN == 32) begin + pmpcfg_q[3:0] = csr.pmpcfg0.rdata; + pmpcfg_q[7:4] = csr.pmpcfg1.rdata; + pmpcfg_q[11:8] = csr.pmpcfg2.rdata; + pmpcfg_q[15:12] = csr.pmpcfg3.rdata; + pmpcfg_d[3:0] = csr.pmpcfg0.rdata; + pmpcfg_d[7:4] = csr.pmpcfg1.rdata; + pmpcfg_d[11:8] = csr.pmpcfg2.rdata; + pmpcfg_d[15:12] = csr.pmpcfg3.rdata; + pmpcfg_q[3:0] = csr.pmpcfg0.wdata; + pmpcfg_q[7:4] = csr.pmpcfg1.wdata; + pmpcfg_q[11:8] = csr.pmpcfg2.wdata; + pmpcfg_q[15:12] = csr.pmpcfg3.wdata; + pmpcfg_q[3:0] = csr.pmpcfg0.wdata; + pmpcfg_q[7:4] = csr.pmpcfg1.wdata; + pmpcfg_q[11:8] = csr.pmpcfg2.wdata; + pmpcfg_q[15:12] = csr.pmpcfg3.wdata; + end else begin + pmpcfg_q[7:0] = csr.pmpcfg0.rdata; + pmpcfg_q[15:8] = csr.pmpcfg0.rdata; + pmpcfg_d[7:0] = csr.pmpcfg0.wdata; + pmpcfg_d[15:8] = csr.pmpcfg0.wdata; end + + rvfi_csr_o.pmpaddr0.rdata[0] = pmpcfg_q[0].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr0.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr1.rdata[0] = pmpcfg_q[1].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr1.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr2.rdata[0] = pmpcfg_q[2].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr2.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr3.rdata[0] = pmpcfg_q[3].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr3.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr4.rdata[0] = pmpcfg_q[4].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr4.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr5.rdata[0] = pmpcfg_q[5].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr5.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr6.rdata[0] = pmpcfg_q[6].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr6.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr7.rdata[0] = pmpcfg_q[7].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr7.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr8.rdata[0] = pmpcfg_q[8].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr8.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr9.rdata[0] = pmpcfg_q[9].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr9.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr10.rdata[0] = pmpcfg_q[10].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr10.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr11.rdata[0] = pmpcfg_q[11].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr11.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr12.rdata[0] = pmpcfg_q[12].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr12.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr13.rdata[0] = pmpcfg_q[13].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr13.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr14.rdata[0] = pmpcfg_q[14].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr14.rdata[0] : 1'b0; + rvfi_csr_o.pmpaddr15.rdata[0] = pmpcfg_q[15].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr15.rdata[0] : 1'b0; + + rvfi_csr_o.pmpaddr0.wdata[0] = pmpcfg_q[0].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr0.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr1.wdata[0] = pmpcfg_q[1].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr1.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr2.wdata[0] = pmpcfg_q[2].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr2.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr3.wdata[0] = pmpcfg_q[3].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr3.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr4.wdata[0] = pmpcfg_q[4].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr4.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr5.wdata[0] = pmpcfg_q[5].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr5.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr6.wdata[0] = pmpcfg_q[6].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr6.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr7.wdata[0] = pmpcfg_q[7].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr7.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr8.wdata[0] = pmpcfg_q[8].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr8.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr9.wdata[0] = pmpcfg_q[9].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr9.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr10.wdata[0] = pmpcfg_q[10].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr10.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr11.wdata[0] = pmpcfg_q[11].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr11.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr12.wdata[0] = pmpcfg_q[12].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr12.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr13.wdata[0] = pmpcfg_q[13].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr13.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr14.wdata[0] = pmpcfg_q[14].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr14.wdata[0] : 1'b0; + rvfi_csr_o.pmpaddr15.wdata[0] = pmpcfg_q[15].addr_mode[1] == 1'b1 ? rvfi_csr_o.pmpaddr15.wdata[0] : 1'b0; + end diff --git a/core/cva6_rvfi_probes.sv b/core/cva6_rvfi_probes.sv index 81d2c5df3df..320db65109a 100644 --- a/core/cva6_rvfi_probes.sv +++ b/core/cva6_rvfi_probes.sv @@ -13,7 +13,11 @@ module cva6_rvfi_probes import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter type rvfi_probes_t = logic + parameter type rvfi_probes_t = struct packed { + logic csr; + logic instr; + } + ) ( input logic flush_i, @@ -36,46 +40,65 @@ module cva6_rvfi_probes input exception_t ex_commit_i, input riscv::priv_lvl_t priv_lvl_i, - input lsu_ctrl_t lsu_ctrl_i, - input logic [ CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, - input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, - input logic [ riscv::PLEN-1:0] mem_paddr_i, - input logic debug_mode_i, - input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i, - output rvfi_probes_t rvfi_probes_o + input lsu_ctrl_t lsu_ctrl_i, + input logic [ CVA6Cfg.NrWbPorts-1:0][riscv::XLEN-1:0] wbdata_i, + input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i, + input logic [ riscv::PLEN-1:0] mem_paddr_i, + input logic debug_mode_i, + input logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_i, + + input rvfi_probes_csr_t csr_i, + + output rvfi_probes_t rvfi_probes_o ); always_comb begin rvfi_probes_o = '0; - rvfi_probes_o.flush = flush_i; - rvfi_probes_o.issue_instr_ack = issue_instr_ack_i; - rvfi_probes_o.fetch_entry_valid = fetch_entry_valid_i; - rvfi_probes_o.instruction = instruction_i; - rvfi_probes_o.is_compressed = is_compressed_i; + if ($size(rvfi_probes_o.instr) != 1) begin + rvfi_probes_o.instr.flush = flush_i; + rvfi_probes_o.instr.issue_instr_ack = issue_instr_ack_i; + rvfi_probes_o.instr.fetch_entry_valid = fetch_entry_valid_i; + rvfi_probes_o.instr.instruction = instruction_i; + rvfi_probes_o.instr.is_compressed = is_compressed_i; + + rvfi_probes_o.instr.issue_pointer = issue_pointer_i; + + rvfi_probes_o.instr.flush_unissued_instr = flush_unissued_instr_i; + rvfi_probes_o.instr.decoded_instr_valid = decoded_instr_valid_i; + rvfi_probes_o.instr.decoded_instr_ack = decoded_instr_ack_i; - rvfi_probes_o.issue_pointer = issue_pointer_i; - rvfi_probes_o.commit_pointer = commit_pointer_i; + rvfi_probes_o.instr.rs1_forwarding = rs1_forwarding_i; + rvfi_probes_o.instr.rs2_forwarding = rs2_forwarding_i; - rvfi_probes_o.flush_unissued_instr = flush_unissued_instr_i; - rvfi_probes_o.decoded_instr_valid = decoded_instr_valid_i; - rvfi_probes_o.decoded_instr_ack = decoded_instr_ack_i; + rvfi_probes_o.instr.ex_commit = ex_commit_i; + rvfi_probes_o.instr.priv_lvl = priv_lvl_i; - rvfi_probes_o.rs1_forwarding = rs1_forwarding_i; - rvfi_probes_o.rs2_forwarding = rs2_forwarding_i; + rvfi_probes_o.instr.lsu_ctrl = lsu_ctrl_i; + rvfi_probes_o.instr.wbdata[CVA6Cfg.NrWbPorts-1:0] = wbdata_i; + rvfi_probes_o.instr.mem_paddr = mem_paddr_i; + rvfi_probes_o.instr.debug_mode = debug_mode_i; + end - rvfi_probes_o.commit_instr = commit_instr_i; - rvfi_probes_o.ex_commit = ex_commit_i; - rvfi_probes_o.priv_lvl = priv_lvl_i; + if ($size(rvfi_probes_o.scoreboard) != 1) begin + for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin + rvfi_probes_o.scoreboard[i].commit_pointer = commit_pointer_i[i]; + rvfi_probes_o.scoreboard[i].commit_instr = commit_instr_i[i]; + rvfi_probes_o.scoreboard[i].commit_ack = commit_ack_i[i]; + rvfi_probes_o.scoreboard[i].wdata = wdata_i[i]; + end + end - rvfi_probes_o.lsu_ctrl = lsu_ctrl_i; - rvfi_probes_o.wbdata = wbdata_i; - rvfi_probes_o.commit_ack = commit_ack_i; - rvfi_probes_o.mem_paddr = mem_paddr_i; - rvfi_probes_o.debug_mode = debug_mode_i; - rvfi_probes_o.wdata = wdata_i; + if ($size(rvfi_probes_o.csr) != 1) begin + rvfi_probes_o.csr = csr_i; + end end endmodule + + + + + diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv index 1616fafa20a..e4f77a67089 100644 --- a/core/include/ariane_pkg.sv +++ b/core/include/ariane_pkg.sv @@ -675,6 +675,8 @@ package ariane_pkg; localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace; + + typedef struct packed { logic [riscv::VLEN-1:0] pc; // PC of instruction logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry @@ -834,6 +836,119 @@ package ariane_pkg; logic [DCACHE_USER_WIDTH-1:0] data_ruser; } dcache_req_o_t; + // RVFI instr + typedef struct packed { + logic [ariane_pkg::TRANS_ID_BITS-1:0] issue_pointer; + logic flush_unissued_instr; + logic decoded_instr_valid; + logic decoded_instr_ack; + logic flush; + logic issue_instr_ack; + logic fetch_entry_valid; + logic [31:0] instruction; + logic is_compressed; + riscv::xlen_t rs1_forwarding; + riscv::xlen_t rs2_forwarding; + ariane_pkg::exception_t ex_commit; + riscv::priv_lvl_t priv_lvl; + ariane_pkg::lsu_ctrl_t lsu_ctrl; + logic [4:0][riscv::XLEN-1:0] wbdata; // [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0] + logic [riscv::PLEN-1:0] mem_paddr; + logic debug_mode; + } rvfi_probes_instr_t; + + // RVFI instr + typedef struct packed { + logic [ariane_pkg::TRANS_ID_BITS-1:0] commit_pointer; + ariane_pkg::scoreboard_entry_t commit_instr; + logic commit_ack; + logic [riscv::XLEN-1:0] wdata; + } rvfi_probes_scoreboard_t; + + // RVFI CSR element + typedef struct packed { + riscv::xlen_t rdata; + riscv::xlen_t rmask; + riscv::xlen_t wdata; + riscv::xlen_t wmask; + } rvfi_probes_csr_elmt_t; + + // RVFI CSR structure + typedef struct packed { + rvfi_probes_csr_elmt_t fflags; + rvfi_probes_csr_elmt_t frm; + rvfi_probes_csr_elmt_t fcsr; + rvfi_probes_csr_elmt_t ftran; + rvfi_probes_csr_elmt_t dcsr; + rvfi_probes_csr_elmt_t dpc; + rvfi_probes_csr_elmt_t dscratch0; + rvfi_probes_csr_elmt_t dscratch1; + rvfi_probes_csr_elmt_t sstatus; + rvfi_probes_csr_elmt_t sie; + rvfi_probes_csr_elmt_t sip; + rvfi_probes_csr_elmt_t stvec; + rvfi_probes_csr_elmt_t scounteren; + rvfi_probes_csr_elmt_t sscratch; + rvfi_probes_csr_elmt_t sepc; + rvfi_probes_csr_elmt_t scause; + rvfi_probes_csr_elmt_t stval; + rvfi_probes_csr_elmt_t satp; + rvfi_probes_csr_elmt_t mstatus; + rvfi_probes_csr_elmt_t mstatush; + rvfi_probes_csr_elmt_t misa; + rvfi_probes_csr_elmt_t medeleg; + rvfi_probes_csr_elmt_t mideleg; + rvfi_probes_csr_elmt_t mie; + rvfi_probes_csr_elmt_t mtvec; + rvfi_probes_csr_elmt_t mcounteren; + rvfi_probes_csr_elmt_t mscratch; + rvfi_probes_csr_elmt_t mepc; + rvfi_probes_csr_elmt_t mcause; + rvfi_probes_csr_elmt_t mtval; + rvfi_probes_csr_elmt_t mip; + rvfi_probes_csr_elmt_t menvcfg; + rvfi_probes_csr_elmt_t menvcfgh; + rvfi_probes_csr_elmt_t mvendorid; + rvfi_probes_csr_elmt_t marchid; + rvfi_probes_csr_elmt_t mhartid; + rvfi_probes_csr_elmt_t mcountinhibit; + rvfi_probes_csr_elmt_t mcycle; + rvfi_probes_csr_elmt_t mcycleh; + rvfi_probes_csr_elmt_t minstret; + rvfi_probes_csr_elmt_t minstreth; + rvfi_probes_csr_elmt_t cycle; + rvfi_probes_csr_elmt_t cycleh; + rvfi_probes_csr_elmt_t instret; + rvfi_probes_csr_elmt_t instreth; + rvfi_probes_csr_elmt_t dcache; + rvfi_probes_csr_elmt_t icache; + rvfi_probes_csr_elmt_t acc_cons; + rvfi_probes_csr_elmt_t pmpcfg0; + rvfi_probes_csr_elmt_t pmpcfg1; + rvfi_probes_csr_elmt_t pmpcfg2; + rvfi_probes_csr_elmt_t pmpcfg3; + rvfi_probes_csr_elmt_t pmpaddr0; + rvfi_probes_csr_elmt_t pmpaddr1; + rvfi_probes_csr_elmt_t pmpaddr2; + rvfi_probes_csr_elmt_t pmpaddr3; + rvfi_probes_csr_elmt_t pmpaddr4; + rvfi_probes_csr_elmt_t pmpaddr5; + rvfi_probes_csr_elmt_t pmpaddr6; + rvfi_probes_csr_elmt_t pmpaddr7; + rvfi_probes_csr_elmt_t pmpaddr8; + rvfi_probes_csr_elmt_t pmpaddr9; + rvfi_probes_csr_elmt_t pmpaddr10; + rvfi_probes_csr_elmt_t pmpaddr11; + rvfi_probes_csr_elmt_t pmpaddr12; + rvfi_probes_csr_elmt_t pmpaddr13; + rvfi_probes_csr_elmt_t pmpaddr14; + rvfi_probes_csr_elmt_t pmpaddr15; + } rvfi_probes_csr_t; + + // alias for futur + typedef rvfi_probes_csr_t rvfi_csr_t; + + // ---------------------- // Arithmetic Functions // ---------------------- diff --git a/corev_apu/src/ariane.sv b/corev_apu/src/ariane.sv index 1ec15ef3d9d..b352318f5cb 100644 --- a/corev_apu/src/ariane.sv +++ b/corev_apu/src/ariane.sv @@ -15,8 +15,11 @@ module ariane import ariane_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter bit IsRVFI = bit'(0), - parameter type rvfi_probes_t = logic, + parameter type rvfi_probes_t = struct packed { + logic csr; + logic scoreboard; + logic instr; + }, parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth, parameter int unsigned AxiDataWidth = ariane_axi::DataWidth, parameter int unsigned AxiIdWidth = ariane_axi::IdWidth, @@ -51,7 +54,6 @@ module ariane import ariane_pkg::*; #( cva6 #( .CVA6Cfg ( CVA6Cfg ), - .IsRVFI ( IsRVFI ), .rvfi_probes_t ( rvfi_probes_t ), .axi_ar_chan_t (axi_ar_chan_t), .axi_aw_chan_t (axi_aw_chan_t), diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv index 3530da0a9a7..1fdc54e6685 100644 --- a/corev_apu/tb/ariane_testharness.sv +++ b/corev_apu/tb/ariane_testharness.sv @@ -36,6 +36,8 @@ module ariane_testharness #( localparam [7:0] hart_id = '0; + + // RVFI localparam type rvfi_instr_t = struct packed { logic [config_pkg::NRET-1:0] valid; logic [config_pkg::NRET*64-1:0] order; @@ -61,29 +63,13 @@ module ariane_testharness #( logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }; - + + localparam type rvfi_csr_t = ariane_pkg::rvfi_probes_csr_t ; + localparam type rvfi_probes_t = struct packed { - logic [ariane_pkg::TRANS_ID_BITS-1:0] issue_pointer; - logic [CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] commit_pointer; - logic flush_unissued_instr; - logic decoded_instr_valid; - logic decoded_instr_ack; - logic flush; - logic issue_instr_ack; - logic fetch_entry_valid; - logic [31:0] instruction; - logic is_compressed; - riscv::xlen_t rs1_forwarding; - riscv::xlen_t rs2_forwarding; - ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr; - ariane_pkg::exception_t ex_commit; - riscv::priv_lvl_t priv_lvl; - ariane_pkg::lsu_ctrl_t lsu_ctrl; - logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; - logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; - logic [riscv::PLEN-1:0] mem_paddr; - logic debug_mode; - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + ariane_pkg::rvfi_probes_csr_t csr; + ariane_pkg::rvfi_probes_scoreboard_t[CVA6Cfg.NrCommitPorts-1:0] scoreboard; + ariane_pkg::rvfi_probes_instr_t instr; }; // disable test-enable @@ -651,11 +637,11 @@ module ariane_testharness #( ariane_axi::req_t axi_ariane_req; ariane_axi::resp_t axi_ariane_resp; rvfi_probes_t rvfi_probes; + ariane_pkg::rvfi_csr_t rvfi_csr; rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; ariane #( .CVA6Cfg ( CVA6Cfg ), - .IsRVFI ( IsRVFI ), .rvfi_probes_t ( rvfi_probes_t ), .noc_req_t ( ariane_axi::req_t ), .noc_resp_t ( ariane_axi::resp_t ) @@ -698,20 +684,25 @@ module ariane_testharness #( end end + + cva6_rvfi #( .CVA6Cfg (CVA6Cfg), .rvfi_instr_t(rvfi_instr_t), + .rvfi_csr_t(ariane_pkg::rvfi_csr_t), .rvfi_probes_t(rvfi_probes_t) ) i_cva6_rvfi ( .clk_i (clk_i), .rst_ni (rst_ni), .rvfi_probes_i(rvfi_probes), - .rvfi_o(rvfi_instr) + .rvfi_instr_o(rvfi_instr), + .rvfi_csr_o(rvfi_csr) ); rvfi_tracer #( .CVA6Cfg(CVA6Cfg), .rvfi_instr_t(rvfi_instr_t), + .rvfi_csr_t(ariane_pkg::rvfi_csr_t), // .HART_ID(hart_id), .DEBUG_START(0), @@ -720,6 +711,7 @@ module ariane_testharness #( .clk_i(clk_i), .rst_ni(rst_ni), .rvfi_i(rvfi_instr), + .rvfi_csr_i(rvfi_csr), .end_of_test_o(rvfi_exit) ); diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv index 75f68beb576..a33b0585b20 100644 --- a/corev_apu/tb/rvfi_tracer.sv +++ b/corev_apu/tb/rvfi_tracer.sv @@ -10,6 +10,7 @@ module rvfi_tracer #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, parameter type rvfi_instr_t = logic, + parameter type rvfi_csr_t = logic, // parameter logic [7:0] HART_ID = '0, parameter int unsigned DEBUG_START = 0, @@ -18,6 +19,7 @@ module rvfi_tracer #( input logic clk_i, input logic rst_ni, input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i, + input ariane_pkg::rvfi_csr_t rvfi_csr_i, output logic[31:0] end_of_test_o ); diff --git a/pd/synth/cva6_synth.tcl b/pd/synth/cva6_synth.tcl index 5ba39d4234d..d05c2e2859c 100644 --- a/pd/synth/cva6_synth.tcl +++ b/pd/synth/cva6_synth.tcl @@ -58,6 +58,9 @@ set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcach set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*] + +set_false_path -to [get_ports {rvfi_probes_o}] + # Check the current design for consistency check_design -summary > ${DCRM_CHECK_DESIGN_REPORT} diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv index a63ebf0cd97..06a2a7797be 100644 --- a/verif/tb/uvmt/cva6_tb_wrapper.sv +++ b/verif/tb/uvmt/cva6_tb_wrapper.sv @@ -36,8 +36,8 @@ import "DPI-C" context function void read_section_sv(input longint address, inou module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter bit IsRVFI = 1'b0, parameter type rvfi_instr_t = logic, + parameter type rvfi_csr_t = logic, // parameter int unsigned AXI_USER_EN = 0, parameter int unsigned NUM_WORDS = 2**25 @@ -47,6 +47,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( input logic [XLEN-1:0] boot_addr_i, output logic [31:0] tb_exit_o, output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, + output ariane_pkg::rvfi_csr_t rvfi_csr_o, input cvxif_pkg::cvxif_resp_t cvxif_resp, output cvxif_pkg::cvxif_req_t cvxif_req, uvma_axi_intf axi_slave, @@ -54,31 +55,12 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( uvmt_default_inputs_intf default_inputs_vif ); - localparam type rvfi_probes_t = struct packed { - logic [ariane_pkg::TRANS_ID_BITS-1:0] issue_pointer; - logic [CVA6Cfg.NrCommitPorts-1:0][ariane_pkg::TRANS_ID_BITS-1:0] commit_pointer; - logic flush_unissued_instr; - logic decoded_instr_valid; - logic decoded_instr_ack; - logic flush; - logic issue_instr_ack; - logic fetch_entry_valid; - logic [31:0] instruction; - logic is_compressed; - riscv::xlen_t rs1_forwarding; - riscv::xlen_t rs2_forwarding; - ariane_pkg::scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr; - ariane_pkg::exception_t ex_commit; - riscv::priv_lvl_t priv_lvl; - ariane_pkg::lsu_ctrl_t lsu_ctrl; - logic [((CVA6Cfg.CvxifEn || CVA6Cfg.RVV) ? 5 : 4)-1:0][riscv::XLEN-1:0] wbdata; - logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack; - logic [riscv::PLEN-1:0] mem_paddr; - logic debug_mode; - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata; + ariane_pkg::rvfi_probes_csr_t csr; + ariane_pkg::rvfi_probes_scoreboard_t[CVA6Cfg.NrCommitPorts-1:0] scoreboard; + ariane_pkg::rvfi_probes_instr_t instr; }; - + ariane_axi::req_t axi_ariane_req; ariane_axi::resp_t axi_ariane_resp; @@ -87,13 +69,14 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr; rvfi_probes_t rvfi_probes; + ariane_pkg::rvfi_csr_t rvfi_csr; assign rvfi_o = rvfi_instr; - + assign rvfi_csr_o = rvfi_csr; + cva6 #( .CVA6Cfg ( CVA6Cfg ), - .rvfi_probes_t ( rvfi_probes_t ), - .IsRVFI ( IsRVFI ) - ) i_cva6 ( + .rvfi_probes_t ( rvfi_probes_t ) + ) i_cva6 ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), .boot_addr_i ( boot_addr_i ),//Driving the boot_addr value from the core control agent @@ -116,17 +99,20 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( cva6_rvfi #( .CVA6Cfg (CVA6Cfg), .rvfi_instr_t(rvfi_instr_t), + .rvfi_csr_t(rvfi_csr_t), .rvfi_probes_t(rvfi_probes_t) ) i_cva6_rvfi ( .clk_i (clk_i), .rst_ni (rst_ni), .rvfi_probes_i(rvfi_probes), - .rvfi_o(rvfi_instr) + .rvfi_instr_o(rvfi_instr), + .rvfi_csr_o(rvfi_csr) ); rvfi_tracer #( .CVA6Cfg(CVA6Cfg), .rvfi_instr_t(rvfi_instr_t), + .rvfi_csr_t(rvfi_csr_t), // .HART_ID(8'h0), .DEBUG_START(0), @@ -135,6 +121,7 @@ module cva6_tb_wrapper import uvmt_cva6_pkg::*; #( .clk_i(clk_i), .rst_ni(rst_ni), .rvfi_i(rvfi_instr), + .rvfi_csr_i(rvfi_csr), .end_of_test_o(tb_exit_o) ) ; diff --git a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv index bd9d2b62029..d580b251d1d 100644 --- a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv +++ b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv @@ -16,8 +16,8 @@ module uvmt_cva6_dut_wrap # ( parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty, - parameter bit IsRVFI = 1'b0, parameter type rvfi_instr_t = logic, + parameter type rvfi_csr_t = logic, // parameter int unsigned AXI_USER_EN = 0, parameter int unsigned NUM_WORDS = 2**25 @@ -31,15 +31,16 @@ module uvmt_cva6_dut_wrap # ( uvmt_default_inputs_intf default_inputs_vif, uvme_cva6_core_cntrl_if core_cntrl_if, output logic[31:0] tb_exit_o, - output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o + output rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_o, + output rvfi_csr_t rvfi_csr_o ); cva6_tb_wrapper #( .CVA6Cfg ( CVA6Cfg ), - .IsRVFI ( IsRVFI ), - .rvfi_instr_t ( rvfi_instr_t ), + .rvfi_instr_t ( rvfi_instr_t ), + .rvfi_csr_t ( rvfi_csr_t ), // .AXI_USER_EN (AXI_USER_EN), .NUM_WORDS (NUM_WORDS) @@ -54,6 +55,7 @@ module uvmt_cva6_dut_wrap # ( .axi_switch_vif ( axi_switch_vif ), .default_inputs_vif ( default_inputs_vif ), .tb_exit_o ( tb_exit_o ), + .rvfi_csr_o ( rvfi_csr_o ), .rvfi_o ( rvfi_o ) ); diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv index 986f165f778..7584415776b 100644 --- a/verif/tb/uvmt/uvmt_cva6_tb.sv +++ b/verif/tb/uvmt/uvmt_cva6_tb.sv @@ -34,7 +34,9 @@ module uvmt_cva6_tb; // CVA6 config localparam config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg; - localparam bit IsRVFI = bit'(cva6_config_pkg::CVA6ConfigRvfiTrace); + + // RVFI + localparam type rvfi_instr_t = struct packed { logic [config_pkg::NRET-1:0] valid; logic [config_pkg::NRET*64-1:0] order; @@ -60,6 +62,8 @@ module uvmt_cva6_tb; logic [config_pkg::NRET*riscv::XLEN-1:0] mem_rdata; logic [config_pkg::NRET*riscv::XLEN-1:0] mem_wdata; }; + + localparam type rvfi_csr_t = ariane_pkg::rvfi_probes_csr_t; localparam AXI_USER_EN = ariane_pkg::AXI_USER_EN; localparam NUM_WORDS = 2**24; @@ -117,9 +121,9 @@ module uvmt_cva6_tb; */ uvmt_cva6_dut_wrap #( - .CVA6Cfg ( CVA6Cfg ), - .IsRVFI ( IsRVFI ), - .rvfi_instr_t ( rvfi_instr_t ), + .CVA6Cfg ( CVA6Cfg ), + .rvfi_instr_t ( rvfi_instr_t ), + .rvfi_csr_t ( rvfi_csr_t ), // .AXI_USER_EN (AXI_USER_EN), .NUM_WORDS (NUM_WORDS) @@ -131,7 +135,8 @@ module uvmt_cva6_tb; .default_inputs_vif (default_inputs_vif), .core_cntrl_if(core_cntrl_if), .tb_exit_o(rvfi_if.tb_exit_o), - .rvfi_o(rvfi_if.rvfi_o) + .rvfi_o(rvfi_if.rvfi_o), + .rvfi_csr_o() ); for (genvar i = 0; i < RVFI_NRET; i++) begin