diff --git a/.gitlab-ci/expected_synth.yml b/.gitlab-ci/expected_synth.yml index f5a2080d1c..b1b7a1e917 100644 --- a/.gitlab-ci/expected_synth.yml +++ b/.gitlab-ci/expected_synth.yml @@ -1,2 +1,2 @@ cv32a65x: - gates: 129216 + gates: 128464 diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index bce13e9f98..b47d6398c3 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1742,7 +1742,11 @@ module csr_regfile mstatus_d.vs = riscv::Dirty; end // hardwired extension registers - mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty); + if (CVA6Cfg.RVS || CVA6Cfg.RVF) begin + mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty); + end else begin + mstatus_d.sd = riscv::Off; + end if (CVA6Cfg.RVH) begin vsstatus_d.sd = (vsstatus_q.xs == riscv::Dirty) | (vsstatus_q.fs == riscv::Dirty); end @@ -1814,14 +1818,16 @@ module csr_regfile trap_to_v = v_q; end end else begin - if (CVA6Cfg.RVS && (ex_i.cause[CVA6Cfg.XLEN-1] && mideleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN - )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && medeleg_q[ex_i.cause[$clog2( - CVA6Cfg.XLEN - )-1:0]])) begin - // traps never transition from a more-privileged mode to a less privileged mode - // so if we are already in M mode, stay there - trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S; + if (CVA6Cfg.RVS) begin + if ((ex_i.cause[CVA6Cfg.XLEN-1] && mideleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]]) || (~ex_i.cause[CVA6Cfg.XLEN-1] && medeleg_q[ex_i.cause[$clog2( + CVA6Cfg.XLEN + )-1:0]])) begin + // traps never transition from a more-privileged mode to a less privileged mode + // so if we are already in M mode, stay there + trap_to_priv_lvl = (priv_lvl_o == riscv::PRIV_LVL_M) ? riscv::PRIV_LVL_M : riscv::PRIV_LVL_S; + end end end @@ -2069,7 +2075,11 @@ module csr_regfile else // otherwise we go with the regular settings en_ld_st_translation_d = en_translation_o; - ld_st_priv_lvl_o = (mprv) ? mstatus_q.mpp : priv_lvl_o; + if (CVA6Cfg.RVU) begin + ld_st_priv_lvl_o = (mprv) ? mstatus_q.mpp : priv_lvl_o; + end else begin + ld_st_priv_lvl_o = priv_lvl_o; + end en_ld_st_translation_o = en_ld_st_translation_q; ld_st_v_o = 1'b0; en_ld_st_g_translation_o = 1'b0; @@ -2206,12 +2216,12 @@ module csr_regfile assign irq_ctrl_o.sie = (CVA6Cfg.RVH && v_q) ? vsstatus_q.sie : mstatus_q.sie; assign irq_ctrl_o.mideleg = mideleg_q; assign irq_ctrl_o.hideleg = (CVA6Cfg.RVH) ? hideleg_q : '0; - assign irq_ctrl_o.global_enable = (~debug_mode_q) + assign irq_ctrl_o.global_enable = ~(CVA6Cfg.DebugEn & debug_mode_q) // interrupts are enabled during single step or we are not stepping // No need to check interrupts during single step if we don't support DEBUG mode & (~CVA6Cfg.DebugEn | (~dcsr_q.step | dcsr_q.stepie)) & ((mstatus_q.mie & (priv_lvl_o == riscv::PRIV_LVL_M)) - | (priv_lvl_o != riscv::PRIV_LVL_M)); + | (CVA6Cfg.RVU & priv_lvl_o != riscv::PRIV_LVL_M)); always_comb begin : privilege_check if (CVA6Cfg.RVH) begin @@ -2388,7 +2398,7 @@ module csr_regfile // privilege level we are jumping and whether the vectored mode is // activated for _that_ privilege level. if (ex_i.cause[CVA6Cfg.XLEN-1] && - ((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && mtvec_q[0]) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && mtvec_q[0])) + ((((CVA6Cfg.RVS || CVA6Cfg.RVU) && trap_to_priv_lvl == riscv::PRIV_LVL_M && (!CVA6Cfg.DirectVecOnly && mtvec_q[0])) || (!CVA6Cfg.RVS && !CVA6Cfg.RVU && (!CVA6Cfg.DirectVecOnly && mtvec_q[0]))) || (CVA6Cfg.RVS && trap_to_priv_lvl == riscv::PRIV_LVL_S && !trap_to_v && stvec_q[0]))) begin trap_vector_base_o[7:2] = ex_i.cause[5:0]; end @@ -2477,7 +2487,7 @@ module csr_regfile `ifdef PITON_ARIANE assign icache_en_o = icache_q[0]; `else - assign icache_en_o = icache_q[0] & (~debug_mode_q); + assign icache_en_o = icache_q[0] & ~(CVA6Cfg.DebugEn && debug_mode_q); `endif assign dcache_en_o = dcache_q[0]; assign acc_cons_en_o = CVA6Cfg.EnableAccelerator ? acc_cons_q[0] : 1'b0; diff --git a/spyglass/reference_summary.rpt b/spyglass/reference_summary.rpt index 69f7567ba9..5405353c7e 100644 --- a/spyglass/reference_summary.rpt +++ b/spyglass/reference_summary.rpt @@ -4,7 +4,7 @@ # This file has been generated by SpyGlass: # Report Name : summary # Report Created by: akassimi -# Report Created on: Mon Jul 1 15:26:27 2024 +# Report Created on: Tue Jul 2 16:35:29 2024 # SpyGlass Version : SpyGlass_vS-2021.09-SP2-3 # Policy Name : SpyGlass(SpyGlass_vS-2021.09-SP2-03) # clock-reset(SpyGlass_vS-2021.09-SP2-03) @@ -19,9 +19,9 @@ # starc2005(SpyGlass_vS-2021.09-SP2-03) # txv(SpyGlass_vS-2021.09-SP2-03) # -# Total Number of Generated Messages : 1306 +# Total Number of Generated Messages : 1327 # Number of Waived Messages : 2 -# Number of Reported Messages : 1304 +# Number of Reported Messages : 1325 # Number of Overlimit Messages : 0 # # @@ -86,9 +86,10 @@ INFO ElabSummary 1 Generates Elaborated design units Severity Rule Name Count Short Help =============================================================================== ERROR InferLatch 2 Latch inferred -ERROR UndrivenInTerm-ML 5 Undriven but loaded input terminal of + +ERROR UndrivenInTerm-ML 4 Undriven but loaded input terminal of an instance detected -ERROR W123 21 A signal or variable has been read but +ERROR W123 20 A signal or variable has been read but is not set ERROR W416 1 Width of return type and return value of a function should be same (Verilog) @@ -104,27 +105,27 @@ WARNING STARC05-1.3.1.3 1 Asynchronous reset/preset signals must WARNING STARC05-2.1.3.1 2 Bit-width of function arguments must match bit-width of the corresponding function inputs. -WARNING STARC05-2.1.4.5 1 Bit-wise operators must be used instead +WARNING STARC05-2.1.4.5 4 Bit-wise operators must be used instead of logic operators in multi-bit operations. WARNING STARC05-2.1.5.3 1 Conditional expressions should evaluate to a scalar. -WARNING STARC05-2.2.3.3 13 Do not assign over the same signal in +WARNING STARC05-2.2.3.3 14 Do not assign over the same signal in an always construct for sequential circuits WARNING W224 1 Multi-bit expression found when one-bit expression expected -WARNING W240 310 An input has been declared but is not +WARNING W240 311 An input has been declared but is not read WARNING W263 4 A case expression width does not match case select expression width -WARNING W287b 37 Output port of an instance is not +WARNING W287b 38 Output port of an instance is not connected -WARNING W415a 530 Signal may be multiply assigned (beside +WARNING W415a 537 Signal may be multiply assigned (beside initialization) in the same scope. WARNING W480 3 Loop index is not of type integer WARNING W486 2 Shift overflow - some bits may be lost -WARNING W528 285 A signal or variable is set but never +WARNING W528 295 A signal or variable is set but never read INFO W240 1 An input has been declared but is not read